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Datasheet: U6264AS1G10 (Zentrum Mikroelektronik Dresden GmbH)

 

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Zentrum Mikroelektronik Dresden GmbH
1
November 01, 2001
U6264A
Standard 8K x 8 SRAM
F
ESD protection > 2000 V
(MIL STD 883C M3015.7)
F
Latch-up immunity > 100 mA
F
Packages: PDIP28 (600 mil)
SOP28 (300 mil)
SOP28 (330 mil)
Description
The U6264A is a static RAM manu-
factured using a CMOS process
technology with the following ope-
rating modes:
- Read
- Standby
- Write
- Data Retention
The memory array is based on a
6-transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the
information of W and G, the data
inputs, or outputs, are active.
During the active state (E1 = L and
E2 = H), each address change
leads to a new Read or Write cycle.
In a Read cycle, the data outputs
are activated by the falling edge of
G, afterwards the data word read
will be available at the outputs
DQ0 - DQ7. After the address
change, the data outputs go High-Z
until the new read information is
available. The data outputs have
no preferred state. If the memory is
driven by CMOS levels in the
active state, and if there is no
change of the address, data input
and control signals W or G, the
operating current (at I
O
= 0 mA)
drops to the value of the operating
current in the Standby mode. The
Read cycle is finished by the falling
edge of E2 or W, or by the rising
edge of E1, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E2, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required. This gate circuit
allows to achieve low power
standby requirements by activation
with TTL-levels too.
If the circuit is inactivated by
E2 = L, the standby current (TTL)
drops to 150
A typ.
F
8192 x 8 bit static CMOS RAM
F
70 and 100 ns Access Times
F
Common data inputs and
outputs
F
Three-state outputs
F
Typ. operating supply current
70 ns: 45 mA
100 ns: 37 mA
F
Data retention current
at 3 V: < 10
A (standard)
F
Standby current standard < 30
A
F
Standby current low power
(L) < 10
A
F
Standby current very low power
(LL) < 1
A
F
Standby current for LL-version
at 25
C and 5 V: typ. 50 nA
F
TTL/CMOS-compatible
F
Automatic reduction of power dis-
sipation in long Read or Write
cycles
F
Power supply voltage 5 V
F
Operating temperature ranges:
0 to 70
C
-25 to 85
C
-40 to 85
C
F
Quality assessment according to
CECC 90000, CECC 90100 and
CECC 90111
Pin Description
Signal Name
Signal Description
A0 - A12
Address Inputs
DQ0 - DQ7
Data In/Out
E1
Chip Enable 1
E2
Chip Enable 2
G
Output Enable
W
Write Enable
VCC
Power Supply Voltage
VSS
Ground
n.c.
not connected
Pin Configuration
1
n.c.
VCC
28
2
A12
W (WE)
27
4
A6
A8
25
5
A5
A9
24
3
A7
E2 (CE2)
26
6
A4
A11
23
7
A3
G (OE)
22
8
A2
A10
21
12
DQ1
DQ5
17
9
A1
E1 (CE1)
20
10
A0
DQ7
19
11
DQ0
DQ6
18
13
DQ2
DQ4
16
14
VSS
DQ3
15
PDIP
Top View
SOP
Features
2
November 01, 2001
U6264A
Block Diagram
* H or L
Operating Mode
E1
E2
W
G
DQ0 - DQ7
Standby/not
selected
*
L
*
*
High-Z
H
*
*
*
High-Z
Internal Read
L
H
H
H
High-Z
Read L
H
H
L
Data
Outputs
Low-Z
Write
L
H
L
*
Data Inputs High-Z
Truth Table
Maximum Ratings
Symbol
Min.
Max.
Unit
Power Supply Voltage
V
CC
-0.3
7
V
Input Voltage
V
I
-0.3
V
CC
+ 0.5
V
Output Voltage
V
O
-0.3
V
CC
+ 0.5
V
Power Dissipation
P
D
-
1
W
Operating Temperature
C-Type
G-Type
K-Type
T
a
0
-25
-40
70
85
85
C
C
C
Storage Temperature
T
stg
-55
125
C
Characteristics
All voltages are referenced to V
SS
= 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
5 ns, measured between 10 % and 90 % of V
I
, as well as
input levels of V
IL
= 0 V and V
IH
= 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the t
dis
-times, in which cases transition is measured
200 mV from steady-state voltage.
Address
Change
Detector
A0
A1
A2
A3
A10
Memory Cell
Array
256 Rows x
256 Columns
Ro
w De
c
o
d
e
r
Ro
w
A
d
d
r
e
s
s
In
p
u
ts
Co
l
u
m
n
De
c
o
d
e
r
C
o
m
m
o
n
D
a
ta

I/O
Sense Amplifier/
Write Control Logic
Clock
Generator
1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
E2
E1
Co
l
u
m
n
A
d
d
r
e
s
s
In
p
u
ts
V
CC
V
SS
W
G
A4
A5
A6
A7
A8
A9
A11
A12
3
November 01, 2001
U6264A
* -2 V at Pulse Width 10 ns
Recommended
Operating Conditions
Symbol
Conditions
Min.
Max.
Unit
Power Supply Voltage
V
CC
4.5
5.5
V
Data Retention Voltage
V
CC(DR)
2.0
V
Input Low Voltage*
V
IL
-0.3
0.8
V
Input High Voltage
V
IH
2.2
V
CC
+ 0.3
V
Electrical Characteristics
Symbol
Conditions
Min.
Max.
Unit
Supply Current - Operating Mode
Standard
Low Power (L)
Very Low Power (LL)
I
CC(OP)
V
CC
V
IL
V
IH
t
cW
t
cW
t
cW
t
cW
t
cW
t
cW
= 5.5 V
= 0.8 V
= 2.2 V
= 70 ns
= 100 ns
= 70 ns
= 100 ns
= 70 ns
= 100 ns
70
60
70
60
55
45
mA
mA
mA
mA
mA
mA
Supply Current - Standby Mode
(CMOS level)
Standard
Low Power (L)
Very Low Power (LL)
I
CC(SB)
V
CC
V
E1
= V
E2
or V
E2
= 5.5 V
= V
CC
- 0.2 V
= 0.2 V
30
10
1
A
A
A
Supply Current - Standby Mode
(TTL level)
Standard
Low Power (L)
Very Low Power (LL)
I
CC(SB)1
V
CC
V
E1
= V
E2
or V
E2
= 5.5 V
= 2.2 V
= 0.2 V
5
5
3
mA
mA
mA
Supply Current - Data Retention
Mode
Standard
Low Power (L)
Very Low Power (LL)
I
CC(DR)
V
CC(DR)
V
E1
= V
E2
or V
E2
= 3
V
= V
CC(DR)
- 0.2 V
= 0.2 V
10
10
1
A
A
A
4
November 01, 2001
U6264A
Electrical Characteristics
Symbol
Conditions
Min.
Max.
Unit
Output High Voltage
Output Low Voltage
V
OH
V
OL
V
CC
I
OH
V
CC
I
OL
= 4.5 V
= -1.0 mA
= 4.5 V
= 3.2 mA
2.4
0.4
V
V
Input Leakage Current
Standard &
Low Power (L)
Very Low Power (LL)
High
Low
High
Low
I
IH
I
IL
I
IH
I
IL
V
CC
V
IH
V
CC
V
IL
V
CC
V
IH
V
CC
V
IL
= 5.5 V
= 5.5 V
= 5.5 V
=
0 V
= 5.5 V
= 5.5 V
= 5.5 V
=
0 V
-2
-1
2
1
A
A
A
A
Output High Current
Output Low Current
I
OH
I
OL
V
CC
V
OH
V
CC
V
OL
= 4.5 V
= 2.4 V
= 4.5 V
= 0.4 V
3.2
-1
mA
mA
Output Leakage Current
Standard & Low Power (L)
High at Three-State Outputs
Low at Three-State Outputs
Very Low Power (LL)
High at Three-State Outputs
Low at Three-State Outputs
I
OHZ
I
OLZ
I
OHZ
I
OLZ
V
CC
V
OH
V
CC
V
OL
V
CC
V
OH
V
CC
V
OL
= 5.5 V
= 5.5 V
= 5.5 V
=
0 V
= 5.5 V
= 5.5 V
= 5.5 V
=
0 V
-2
-2
2
1
-
A
A
A
A
5
November 01, 2001
U6264A
Switching Characteristics
Symbol
Min.
Max.
Unit
Alt.
IEC
07
10
07
10
Time to Output in Low-Z
t
LZ
t
t(QX)
5
5
10
10
ns
Cycle Time
Write Cycle Time
Read Cycle Time
t
WC
t
RC
t
cW
t
cR
70
70
100
100
ns
ns
Access Time
E1 LOW or E2 HIGH to Data Valid
G LOW to Data Valid
Address to Data Valid
t
ACE
t
OE
t
AA
t
a(E)
t
a(G)
t
a(A)
-
-
-
-
-
-
70
40
70
100
50
100
ns
ns
ns
Pulse Widths
Write Pulse Width
Chip Enable to End of Write
t
WP
t
CW
t
w(W)
t
w(E)
50
65
70
90
ns
ns
Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time
t
AS
t
CW
t
WP
t
DS
t
su(A)
t
su(E)
t
su(W)
t
su(D)
0
65
50
35
0
90
70
40
ns
ns
ns
ns
Data Hold Time
Address Hold from End of Write
t
DH
t
AH
t
h(D)
t
h(A)
0
0
0
0
ns
ns
Output Hold Time from Address Change
t
OH
t
v(A)
5
5
ns
E1 HIGH or E2 LOW to Output in High-Z
W LOW to Output in High-Z
G HIGH to Output in High-Z
t
HZCE
t
HZWE
t
HZOE
t
dis(E)
t
dis(W)
t
dis(G)
0
0
0
0
0
0
25
30
25
35
35
35
ns
ns
ns
Data Retention Mode E1-Controlled
Data Retention
4.5 V
t
DR
t
rec
V
CC
E1
V
CC(DR)
2 V
V
E2(DR)
V
CC(DR)
- 0.2 V or V
E2(DR)
0.2 V
V
CC(DR)
- 0.2 V
V
E1(DR)
V
CC(DR)
+ 0.3 V
0 V
2.2 V
2.2 V
V
CC(DR)
2 V
Data Retention Mode E2-Controlled
Data Retention
t
rec
t
DR
0.8 V
0.8 V
V
E2(DR)
0.2 V
4.5 V
0 V
V
CC
E2
Chip Deselect to Data Retention Time
t
DR
: min
0
ns
Operating Recovery Time
t
rec
: min t
cR
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