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Datasheet: A2SI (Zentrum Mikroelektronik Dresden GmbH)

 

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Zentrum Mikroelektronik Dresden GmbH
Rev. 2.5, Copyright 2002, ZMD AG
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
1/30
ASI
Data Sheet
Advanced AS-Interface IC
1 Features
AS-i Complete Specification V2.11 compliant
Integrated EEPROM
Additional addressing channel using an opto-
electronic interface
Extended address mode operation as
programmable option (up to 62 slaves)
High impedance AS-i line input, additional pins
for further impedance optimizations
DC voltage output, approximately 24 volts, not
stabilized
5 volt DC voltage output, stabilized, CMOS logic
can be supplied directly (e.g. C)
LED status indicator output (compliant with the
standard indication recommendation)
Integrated watchdog
2 Description
ASI is a monolithic CMOS integrated circuit certified
for AS-i (Actuator Sensor-interface) networks. AS-i
networks are intended for industrial automation.
The main advantage of AS-i solutions is that actuators
and sensors are connected using a two-wire
unshielded cable that is easy to install. This cable
transports both power and information/data.
AS-i network communication is based on the master-
slave principle. The network can be extended (to
cable lengths greater than 100m) by using the ASI in
the repeater mode configuration.
AS-i is a standard for the automation industry based
on IEC 62026-2 and EN 50295.
The device is available in a 28-pin SSOP package.
3 Block Diagram


Figure 1: Block Diagram
RECEIVE
TRANSMIT
ELECTRONIC
INDUCTOR
POWER
SUPPLY
OSCILLATOR
4
4
4
DIGITAL
LOGIC
THERMAL
PROTECTION
A
2
SI
GND2
GND1
ASI+
ASI
8 MHz
DOx
DIx
DSR
PST
Px
FID
LED
IRD
GND
0V
U
IN
U
OUT
U5R
U5RD
OSC1/2
CAP
ASIP
ASIN
10
F
2.2
F
5V
24V
POWERFAIL
DETECTION
IRD
AMP
C
CAP
R
CAP
Rev. 2.5, Copyright 2002, ZMD AG
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
2/30
ASI
Data Sheet
Advanced AS-Interface IC
4 Pin Description
Table 1: Pin Description
PIN #
Name
Type
Description
1
ASIP
INOUT
To be connected to the AS-i-line ASI+ via reverse polarity protection diode
2
ASIN
INOUT
To be connected to the AS-i-line ASI-
3
0V
SUPPLY
Common 0V for all ports except ASIP/ASIN (to be connected to ASI- line)
4
IRD
IN
Addressing channel input
5
FID
IN
Input peripheral fault indication
6
OSC2
INOUT
Crystal oscillator (8 MHz x-tal)
7
OSC1
IN
Crystal oscillator / external clock input
8
DO3
OUT
Output of data D3
9
DO2
OUT
Output of data D2
10
DO1
OUT
Output of data D1
11
DO0
OUT
Output of data D0
12
GND
SUPPLY
Digital IO ground, must be connected to pin 0V
13
P3
I/O
Input/output of parameter P3
14
P2
I/O
Input/output of parameter P2 / receive strobe in "Master Mode"
15
P1
I/O
Input/output of parameter P1 / power fail in "Master Mode"
16
P0
I/O
Input/output of parameter P0 / data clock in "Master Mode"
17
DI0
IN
Input of data D0
18
DI1
IN
Input of data D1
19
DI2
IN
Input of data D2
20
DI3
IN
Input of data D3
21
PST
OUT
Parameter strobe output
22
DSR
I/O
Data strobe output/reset input
23
U5RD
SUPPLY Digital 5V supply input, should be connected to U5R
24
LED
OUT
Output LED "AS-i-Diagnosis" / addressing channel output
25
CAP
IN/OUT
For connection of external RC components
26
U5R
OUT
Internal 5V supply that might be used to supply external circuits as well
27
U
OUT
OUT
Supply of external circuitry (e.g. sensor, actuator, etc.), approx. V
UIN
minus 7 volt
28
U
IN
SUPPLY
Input of the power supply block (usually to be connected to the AS-i-line ASI+ via
reverse polarity protection diode)
Rev. 2.5, Copyright 2002, ZMD AG
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
3/30
ASI
Data Sheet
Advanced AS-Interface IC
5 Pin Configuration
Figure 2: Pin Configuration, 28-Pin SSOP













6 Functional Block Description
6.1 Power Supply
An on-chip electronic inductor provides a de-coupled voltage at pin U
OUT
and the power supply regulates the
internal 5V operating voltage. The de-coupling circuit (electronic coil) is connected between U
IN
and U
OUT
pins
and guarantees a high impedance seen at U
IN
. An external capacitor and resistor are required to allow a low-
pass filter with a very high time constant. This high time-constant value is necessary to maximize the input
impedance. The de-coupling circuit limits the current that can be drawn from U
OUT
. The power supply will shut
down the de-coupling circuit in case of an overload condition to prevent a total malfunction of the complete AS-i
line. The regulated 5 volt supply voltage is connected to pin U5R. Two external capacitors are necessary to cope
with fast internal and external load changes (spikes). Current drawn from pin U5R (up to 4 mA) has to be
subtracted from the total load current. The power supply circuit dissipates the major amount of power.
The total power dissipation shall not exceed the specified values of Figure 6. The ground reference voltage for
both UOUT and U5R is defined by the 0V pin. This pin must be connected to ASI- (ref.
Figure 1: Block Diagram
).
6.2 Receiver
The receiver detects signals on the AS-i line and delivers the appropriate pulses to the digital logic. The DC
value of the input signal is removed and the AC signal is band-pass filtered. The digital output signals are
extracted from the sin
2
-shaped input pulses by a set of comparators. The maximum voltage of the first negative
pulse determines the threshold level for all following pulses. The maximum value is digitally filtered to guarantee
stable conditions (burst spikes have no effect). This approach combines a fast adaptation to changing signal
amplitudes with a high detection safety. The receiver delivers positive (P-PULSE) and negative (N-PULSE)
pulses to the IC's logic. The logic resets the comparators after receiving the REC-RESET signal. When the
receiver is turned on, the transmitter is turned off to reduce power consumption.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ASIP
ASIN
0V
IRD
FID
OSC2
OSC1
DO1
DO3
DO2
GND
P3
P2
P1
U
IN
U
OUT
U5R
CAP
LED
U5RD
DSR
PST
DI3
DO0
DI2
DI1
DI0
A
2
SI
P0
Rev. 2.5, Copyright 2002, ZMD AG
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
4/30
ASI
Data Sheet
Advanced AS-Interface IC
6.3 Transmitter
The transmitter draws a modulated current between ASIP and ASIN pins to generate the communication signals.
The shape of the current corresponds to the integral of a sin-function. The transmitter uses a current DAC and a
high current driver. In order to activate high current drive capability, a small current will be turned on
automatically prior to each transmission (slave mode only). The current will be ramped up slowly to avoid false
voltage pulses on the AS-I line. The amount of circuitry between ASI+ and ASI- pins is minimized to allow high
impedance values. When the transmitter is turned on, the receiver is turned off to reduce power consumption.
6.4 Digital Logic
The digital logic block performs analysis of the received signal, controls reaction of the IC, transmits slave
response, switches I/O-ports, and controls the internal EEPROM. Its principal function is described in detail in
section 7.
6.5 Protection Circuitry
The device has several protection cells that prevent disruption and malfunction of the complete AS-i line.
The thermal detection shuts down the power supply in case of over-heating condition (silicon temperature
> 140C typically for more than 2 seconds) and when U
OUT
is shorted to GND for more than 2 seconds. The
device can only be reactivated by a power-on reset. An over-heating condition can occur by overloading any
output pin. Therefore, the circuit monitors the operating conditions of the power supply (effectively monitors
U
OUT
) and measures the temperature of the silicon.
6.6 Infrared Diode Input
The photo current input can be used as an alternative communication pin in slave mode. The IRD circuitry will be
turned off when the communication has been switched to AS-i line. In Slave mode the logic sets IRD input to
photo-detector mode and disables CMOS mode. In this photo-detector mode, signals of an external photo diode
are amplified. In CMOS mode (master/repeater mode only), input signals have to be CMOS levels between 0V
and V
U5R
.
6.7 Power-Fail Detection
The power-fail detector consists of a comparator that generates a logic signal in case the power supply drops
below 22V
DC
(Power-Fail) for a time of more than t
Loff
(0.8
0.1 ms). The power fail signal will be presented at
pin P1 in master mode only.
Power-fail detection monitors the value of the ASIP voltage. It will activate a logic signal if power fails for more
than 1ms. The device is then buffered by the external capacitor at U
OUT
and the internal circuitry will be reset
when U5R supply voltage fails
Rev. 2.5, Copyright 2002, ZMD AG
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
5/30
ASI
Data Sheet
Advanced AS-Interface IC
Figure 3 : Functional Block Diagram
Rev. 2.5, Copyright 2002, ZMD AG
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
6/30
ASI
Data Sheet
Advanced AS-Interface IC
7 Description of Digital Logic
The digital logic is structured in four (4) parts:

1)
the UART, which analyses the incoming signal from the AS-i line and ensures correct timing of output
signals;
2)
the STATE MACHINE, which controls the reaction of the IC;
3)
the PORTS, which contain registers and digital I/O's;
4)
and finally the EPROM, which contains the non-volatile data of the
A
2
SI circuit.
DATA-OUT-0
DATA-OUT-1
DATA-OUT-2
DATA-OUT-3
DATA-STRB
RESET
DATA-IN-0
DATA-IN-1
DATA-IN-2
DATA-IN-3
PARAM-OUT-0
PARAM-OUT-1
PARAM-OUT-2
PARAM-OUT-3
PARAM-STRB
PARAM-IN-0
PARAM-IN-1
PARAM-IN-2
PARAM-IN-3
IRD-IN
FAULT-IN
LED-OUT
OVER-HEAT
U
OUT
S
HOUTDOWN
PORTS
DO-R
EG
-0
DO-R
EG
-1
DO-R
EG
-2
DO-R
EG
-3
DI-R
EG
-0
DI-R
EG
-1
DI-R
EG
-2
DI-R
EG
-3
PO-R
EG
-0
PO-R
EG
-1
PO-R
EG
-2
PO-R
EG
-3
PI-0
PI-1
PI-2
PI-3
E
2
PROM
STATE MACHINE
R
EC
-R
EG
-0
R
EC
-R
EG
-1
R
EC
-R
EG
-2
R
EC
-R
EG
-3
R
EC
-R
EG
-4
R
EC
-R
EG
-5
R
EC
-R
EG
-6
R
EC
-R
EG
-7
R
EC
-R
EG
-8
R
EC
-R
EG
-9
R
EC
-R
EG
-10
R
EC
-S
TRB
S
END
-R
EG
-0
S
END
-R
EG
-1
S
END
-R
EG
-2
S
END
-R
EG
-3
S
END
-S
TRB
ADD-CLK
ADD-OUT
ADD-IN
P-PULSE
N-PULSE
SEND-D
SEND-SBY
REC-RESET
Digital Logic
POWER-FAIL
POWER-ON RESET
P-Pulse
UART
Figure 4: Digital Logic
Rev. 2.5, Copyright 2002, ZMD AG
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
7/30
ASI
Data Sheet
Advanced AS-Interface IC
7.1 Operational Modes
7.1.1 Master/Repeater Mode
7.1.1.1
IRD Input (CMOS Input)
The IC sends signals retrieved from pin IRD to AS-i line as an AS-i telegram. The input signal is Manchester-
coded and active low. A falling edge of the IRD signal, which is conducted to ADD-IN, starts the receiving
process and triggers the Activity-Checker. Receive-Muxer selects pin IRD as input for the receive data
The IRD signal is connected with Send-Muxer to SEND-D via ADD-IN. The IRD signal is latched every 500 ns as
long as there is activity on the input pin. If there is a high level on the IRD input longer then 7.0 s, Activity-
Check
er will recognize this as no activity and Receive-Muxer is returning to idle state. The information on pin
IRD is transported to pin SEND-D with a delay of 2.0 s up to 2.5 s. The sender is always in non-standby
mode. The SEND-SBY signal is constant low and there is no generation of ADD-CLK.
R
EC
-R
EG
-0
R
EC
-R
EG
-1
R
EC
-R
EG
-2
R
EC
-R
EG
-3
R
EC
-R
EG
-4
R
EC
-R
EG
-5
R
EC
-R
EG
-6
R
EC
-R
EG
-7
R
EC
-R
EG
-8
R
EC
-R
EG
-9
R
EC
-R
EG
-10
UART
S
END
-R
EG
-0
S
END
-R
EG
-1
S
END
-R
EG
-2
S
END
-R
EG
-3
RECEIVE
REGISTER
SEND
MUXER
SEND-D
ADD-OUT
RECEIVE
MUXER
MAN CODE
CHECKER
CONTROL
UNIT
PULSE
ENCODER
ACTIVITY
CHECKER
SEND
REGISTER
STROBE
UNIT
P-PULSE
N-PULSE
ADD-IN
SEND-STRB
REC-STRB
ADD-CLK
SEND-SBY
REC-RESET
Figure 5: UART Block Diagram
Rev. 2.5, Copyright 2002, ZMD AG
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
8/30
ASI
Data Sheet
Advanced AS-Interface IC
7.1.1.2
AS-i Input
A signal on the AS-i-line generates signals at the receiver output that are pulse coded with a minimal pulse width
of 750 ns up to 875 ns. A pulse on the AS-i line starts the receiver and triggers the Activity-Checker through N-
PULSE or P-PULSE. The Receive-Muxer selects AS-i-line pins as input for the receive data. The N-PULSE and
P-PULSE signals are latched every 250 ns as long as there is activity on the input pins. If there is a pulse
distance on the AS-i-line inputs longer then 7.0 s, the receiver will recognize this as no activity and the Receive-
Muxer
is going to the idle state.
The Pulse-Encoder is used to convert the active high pulse-coded signal to a active low Manchester-II-coded
(MAN) signal. It will also check the pulse stream for timing and pulse errors (e.g. alternation error). In
Master/Repeater mode the Pulse-Encoder additionally resynchronizes an error-free MAN telegram into a proper
3 s time base. This is to eliminate the pulse jitter of the transformed AS-i telegram. The synchronized MAN
signal is sent to ADD-OUT through the Send-Muxer. ADD-OUT is connected to LED-OUT on a higher hierarchy
level. All in all, information on the AS-i-line pins is transported to pin LED-OUT with a delay of 2.5 s up to
3.0 s. In Master/Repeater mode the sender is never in standby mode, hence SEND-SBY signal is always low.
A generation of ADD-CLK is provided to simplify external processing of Manchester-coded data. The rising edge
of the ADD-CLK signal is in the middle of the second half of the Manchester data assuring that correct binary
data can be clocked into a shift register. The ADD-CLK starts with a rising edge 2.0 s after the falling edge of
the start bit at ADD-OUT with a period of 6.0 s and a ratio of 1:1. The last rising edge of the ADD-CLK signal
occurs 2.0 s after the falling edge of the end bit at ADD-OUT.
If the received signal in the Master Mode is a valid slave answer with start bit, four (4) data bits, parity, and end
bit and if a pause is following with a length greater than 6.0 s, the UART generates the active high REC-STRB
signal with a pulse width of 500 ns. The REC-STRB signal is connected to the P2 Parameter Output in this
mode. It appears 10.0 to 10.5 s after the rising edge of the end bit on AS-i-line.
7.1.1.3
Ports
Functional assignments of some IC ports depend on the operational mode of the IC. Thus, these ports perform
multiple functions that are related to a particular mode of the IC.
In Master Mode, following signals and ports are connected:
PIN
Slave Function
Master
Repeater
P0
Parameter output
port bit 0
REC-CLK
REC-CLK
P1
Parameter output
port bit 1
POWER-
FAIL
-
P2
Parameter output
port bit 2
REC-STRB
-
LED
LED
Fault indicator
output/addressing
channel output
MAN-OUT
MAN-OUT
IRD
Addressing channel
input
MAN-IN
MAN-IN
Rev. 2.5, Copyright 2002, ZMD AG
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
9/30
ASI
Data Sheet
Advanced AS-Interface IC
7.1.2 Slave Mode
After IC-reset, Receive-Muxer is watching the two input channels (AS-i-line and IRD pin) depending on a
multiplex select signal MPX. MPX has a frequency of about 1.0 kHz. If MPX is low, the Receive-Muxer selects
the AS-i-line and vice versa if it is high, it selects the IRD pin as data input. The channel, from which a valid
master call is received first, will be locked until the next IC-reset occurs.
7.1.2.1
IRD Input Mode (Photo Diode Input)
The photo diode current on the IRD input is Manchester-coded and low active (ref. 8.2.2 Addressing Channel
Input IRD). A low level of the IRD signal starts the receiver and triggers the Activity-Checker. The Control-Unit is
enabling the Receive-Register and the received information is clocked every 6 s into the Receive-Register. If
there is a high level on the IRD input longer then 7.0 s, the Control-Unit will recognize this as no activity and the
Receive-Register will be disabled. If the received information is a correct master call with Start-Bit, eleven Data-
Bits
, Parity-Bit, End-Bit, and following pause of either greater than 6.0 s (Synchronous Mode) or 18.0 s
(Asynchronous Mode), the UART generates the internal active high REC-STRB signal with a pulse width of
500 ns.
If the received telegram contained an error, the Control-Unit will not generate the REC-STRB signal but go to its
asynchronous state waiting for a pause at the IRD input. After a pause was detected, the UART is ready to
receive the next telegram from the IRD input.
If a REC-STRB signal is generated, it occurs 9.5 s up to 10.0 s (Synchronous Mode) or 21.0 s up to 21.5 s
(Asynchronous Mode), respectively, after the rising edge of the End-Bit on the IRD pin signal. If the slave was in
asynchronous state, it now transforms to synchronous state. The Rec-Muxer is locked to the IRD input until the
next IC-reset. After the generation of a REC-STRB signal the Control-Unit is waiting for about 6.0 s for the
SEND-STRB to be generated by the Main-State-Machine.
If the Control-Unit receives the active high SEND-STRB signal, it starts the transmission of the Send-Register
data. Therefore, the Send-Register data will be converted to an active low Manchester II-coded (MAN) signal
which is sent to the LED-OUT pin via ADD-OUT. The first falling edge of the MAN signal occurs 11.75 s
(Synchronous Mode) or 12.25 s (Asynchronous Mode) after the rising edge of the REC-STRB signal. Hence,
the delay from the rising edge of the End-Bit of the master call (IRD input) to the first falling edge of the slave
response (LED output) is 21.25 to 21.75 s (Synchronous Mode) or 33.25 to 33.75 s (Asynchronous Mode).
After the pause was detected, the UART is ready to receive the next telegram from the IRD input.
In case the Control-Unit will not receive a SEND-STRB signal within the given time frame (for instance, if this
slave was not addressed), it will check for activity on the IRD input. Otherwise, it will just wait for the end of the
response time (60 s). In both cases the Control-Unit stays synchronous. Once a slave pause was detected, the
UART is ready to receive the next telegram from the IRD input
7.1.2.2
AS-i Input Mode
A signal on the AS-i-line generates two pulse-coded signals (N-PULSE, P-PULSE) at the receiver output with a
minimum pulse width of 750 to 875 ns. A pulse on the AS-i line starts the receiver and triggers the Activity-
Checker
through N-PULSE or P-PULSE.
The Pulse-Encoder is used to convert the active high pulse coded signal to an active low Manchester-II-coded
(MAN) signal. It will also check the pulse stream for timing and pulse errors (e.g. alternation error). The Control-
Unit
enables the Receive-Register so that the received information can be clocked in every 6 s. If there is a
pulse distance on the AS-i-line input longer than 7.0 s, the Control-Unit recognizes this as no activity and
disables the Receive-Register.
Rev. 2.5, Copyright 2002, ZMD AG
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
10/30
ASI
Data Sheet
Advanced AS-Interface IC
If the received information is a correct master call with Start-Bit, eleven (11) Data-Bits, Parity-Bit, End-Bit, and
following pause of either greater than 6.0 s (Synchronous Mode) or 18.0 s (Asynchronous Mode), the UART
generates the internal active high REC-STRB signal. If the received telegram contained an error, the Control-
Unit will not generate the REC-STRB signal but go to its asynchronous state waiting for a pause at the AS-i line
input. After a pause was detected the UART is ready to receive the next telegram from the AS-i line input.
If a REC-STRB signal is generated, it occurs 10.0 to 10.5 s (Synchronous Mode) or 21.5 to 22 s
(Asynchronous Mode), respectively, after the rising edge (receiver comparator switching point) of the End-Bit on
the AS-i line input. If the slave was in asynchronous state, it now transforms to synchronous state. The Rec-
Muxer is locked to the AS-i line input until the next IC-reset. After the generation of a REC-STRB signal the
Control-Unit is waiting for about 6.0 s for the SEND-STRB to be generated by the Main-State-Machine.
If the Control-Unit receives the active high SEND-STRB signal (pulse width 500 ns), it starts the transmission of
the Send-Register data. Therefore, the Send-Register data will be converted to an active low Manchester II-
coded (MAN) signal which is sent to the AS-i line transmitter via SEND-D. The first falling edge of the MAN
signal occurs 11.75 s (Synchronous Mode) or 12.25 s (Asynchronous Mode) after the rising edge of the REC-
STRB signal.
Hence, the delay from the rising edge of the End-Bit of the master call (AS-i input) to the first falling edge of the
slave response (AS-i output) is 21.75 to 22.25 s (Synchronous Mode) or 33.75 to 34.25 s (Asynchronous
Mode).
The SEND-SBY will always be set low 0.5 s after the rising edge of REC-STRB. This is to turn on the
transmitter and let it settle at its operation point. The small offset current, which is required to operate the
transmitter, will be ramped up slowly to avoid any false voltage pulses on the AS-i line.
If all data is sent, the Control-Unit sets the sender in standby mode (SEND-SBY is high) and checks for a slave
pause on the AS-i line input. After the pause was detected, the UART is ready to receive the next telegram from
the AS-i line input.
In case the Control-Unit will not receive a SEND-STRB signal within the given time frame (for instance, if this
slave was not addressed), it will check for activity on the AS-i line. If any activity is detected in a time frame of
about 60 s (another slave is transmitting data), the Control-Unit will wait for the next pause (slave pause).
Otherwise, it will just wait for the end of the response time (60 s). In both cases the Control-Unit stays
synchronus. Once a slave pause was detected, the UART is ready to receive the next telegram from the AS-i
line input.
7.1.2.3
Ports
Although the ASI can still store the AS-i Slave IO-Configuration Code it does not decode the value to configure
the direction of the Data-Port signals. The ASI rather has distinctive Data-Out and Data-In ports which do
always work in parallel.
If bi-directional Data I/O is desired on top of a single Data-Port only (for backwards compatibility), the Data-Out
pins and the Data-In pins need to be shorted on the circuit board respectively and the non-volatile Multiplex flag
has to be set TRUE.
In that case the output ports will switch to high impedance state for a certain time following the rising edge of the
Data-Strobe and allow the input data to be put on the Data-Port.
The input data will be read inverted if the non-volatile Invert_Data_In flag is TRUE. This feature will simplify the
circuitry for NPN-inputs.
Note: The Multiplex and the Invert_Data_In flags are Configuration flags which are stored in the Firmware region
of the internal EPROM. For a complete overview of the EPROM content please see the ASI Application
Notes.
Rev. 2.5, Copyright 2002, ZMD AG
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
11/30
ASI
Data Sheet
Advanced AS-Interface IC
The parameter port is always in bi-directional mode. The input data is the result of a wired-AND between the
open drain output drivers and the application drivers.
7.1.2.4
Watchdog
Compliant to the AS-i Complete Specification, the IC contains an independent watchdog which is generally
enabled by setting Watchdog_Active flag in the EPROM to TRUE.
The watchdog will be activated for any slave address uneven to zero (0) after the reception of a
Write_Parameter Request at the particular Slave Address. It will be deactivated by any circuit Reset and after
the reception of a Delete_Address Request.
When activated, the Watchdog will be reset by every Write_Parameter and Data_Exchange Request received
by the Slave. If no such request was received by the particular Slave within 40ms, a Hardware Reset will be
performed and all Data and Parameter Outputs are switched inactive.
7.1.2.5
LED Output
An active FID (logic high) signal causes a flashing status LED (frequency approx. 2Hz) and Bit 1 of the AS-i
Slave Status-Register (S1) is set as well. If FID is not active (logic low), S1 is cleared. In that case the status
LED operation depends on the Data-Exchange-Disable flag.
The Data-Exchange-Disable is set to TRUE by each Reset of the ASI. It becomes cleared (set to FALSE) after
the first reception of a Write_Parameter Request.
If the Data-Exchange-Disable flag is set, no data exchange can be performed through the Data Ports which is
indicated by a steady-on LED.
Note: An active FID has priority and will cause a flashing LED even if the Data-Exchange-Disable flag is set.
If the UART has selected the IRD input channel, the LED output is again overwritten by the Addressing Channel
output. In this mode the LED pin does not operate as indicator LED output and periphery failures or status
information can not be signaled.
7.1.2.6
Overtemp shutdown
The ASI continuously observes its silicon die temperature. If the temperature rises above 140C the IC will be
put into shut-down and stay there until the next power-on reset occurs.
7.1.2.7
State Machine
The so-called Main-State-Machine performs the central control of the A2SI IC in terms of operation mode
selection, EEPROM access control, processing of master requests and the control of the IC ports. The Main-
State-Machine interfaces with the UART through the Receive- and the Send-Register as well as certain strobe
signals.
To avoid the situation in which a slave IC gets locked in a not allowed state (i.e by emission of strong
electromagnetic radiation) and thereby would jeopardize the entire system, all prohibited states of the state
machine will lead to a RESET which is comparable to the AS-i call "Reset Slave (RES)".
7.2
Summary of Master Calls
In the following diagram all Master Calls that will be decoded by the A2SI are listed. The "Enter Program Mode"
call is intended for factory programming of the IC only. In order to achieve EEPROM firmware protection and to
comply to the complete AS-i specification, the call "Enter Program Mode" has to be deactivated before shipment
of the slave.
Rev. 2.5, Copyright 2002, ZMD AG
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
12/30
ASI
Data Sheet
Advanced AS-Interface IC
Table 2: ASI Master Calls and Related Save Responses
Master Request
Slave Response
Instruction
MNE
ST
CB
A4
A3
A2
A1
A0
I4
I3
I2
I1
I0
PB
EB
SB
I3
I2
I1
I0
PB
EB
Data Exchange
DEXG
0
0
A4
A3
A2
A1
A0
0
D3
~Sel
D2
D1
D0
PB
1
0
D3
E3
D2
E2
D1
E1
D0
E0
PB
1
Write Parameter
WPAR
0
0
A4
A3
A2
A1
A0
1
P3
~Sel
P2
P1
P0
PB
1
0
P3
I3
P2
I2
P1
I1
P0
I0
PB
1
Address Assignment ADRA
0
0
0
0
0
0
0
A4
A3
A2
A1
A0
PB
1
0
0
1
1
0
PB
1
Write Extented ID
Code-1
WID1
0
1
0
0
0
0
0
0
ID3 ID2 ID1 ID0
PB
1
0
0
0
0
0
PB
1
Delete Address
DELA
0
1
A4
A3
A2
A1
A0
0
0 Sel
0
0
0
PB
1
0
0
0
0
0
PB
1
Reset Slave
RES
0
1
A4
A3
A2
A1
A0
1
1
~Sel
1
0
0
PB
1
0
0
1
1
0
PB
1
Read IO
Configuration
RDIO
0
1
A4
A3
A2
A1
A0
1
0
Sel
0
0
0
PB
1
0
IO3 IO2 IO1 IO0
PB
1
Read ID Code
RDID
0
1
A4
A3
A2
A1
A0
1
0
Sel
0
0
1
PB
1
0
ID3 ID2 ID1 ID0
PB
1
Read ID Code-1
RID1
0
1
A4
A3
A2
A1
A0
1
0
Sel
0
1
0
PB
1
0
ID3 ID2 ID1 ID0
PB
1
Read ID Code-2
RID2
0
1
A4
A3
A2
A1
A0
1
0
Sel
0
1
1
PB
1
0
ID3 ID2 ID1 ID0
PB
1
Read Status
RDST
0
1
A4
A3
A2
A1
A0
1
1
~Sel
1
1
0
PB
1
0
S3
S2
S1
S0
PB
1
Broadcast (Reset)
BR01
0
1
1
1
1
1
1
1
0
1
0
1
PB
1
--- no slave response ---
Enter Program Mode PRGM
0
1
0
0
0
0
0
1
1
1
0
1
PB
1
--- no slave response ---
Note: In extended address mode the "Select Bit" defines whether the A-Slave or B-Slave is being
addressed. Dependent on the type of master call the I3 bit carries the select bit information (Sel) or the
inverted select bit information (~Sel).
7.3 Program Mode
Provided that the non-volatile configuration flag, Program-Mode-Disable, has not been set, the device can be
transferred in program mode by utilizing the "Enter Program Mode" call.
Please refer to the ASI Application Notes [4] for details of the programming process.
AS-i Complete Specification compliance note:
In order to ensure full compliance with the AS-i Complete Specification, the Program-Mode-Disable flag must
be set in the final manufacturing and configuration process before an AS-i slave device is being delivered to
field application users.
Rev. 2.5, Copyright 2002, ZMD AG
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
13/30
ASI
Data Sheet
Advanced AS-Interface IC
8 Electrical Specification
8.1 Absolute Maximum Ratings
Any stress above the listed Absolute Maximum Ratings may cause permanent damage to the device. The given
conditions represent a stress rating only. Functional operation of the device at those conditions or at any other
stress above the Operational Limits is not implied. Exposure to maximum rating conditions for extended times
may effect device performance, functionality, and reliability.
Table 3: Absolute Maximum Ratings
SYMBOL
PARAMETER
MIN.
MAX.
UNITS NOTE
V
0V
,V
GND
Voltage reference
0
0
V
V
ASIP
Positive AS-i supply voltage
-0.3
40
V
V
ASIN
Negative AS-i supply voltage
-0.3
20
V
1
V
ASIP-ASIN
Voltage difference from ASIP to ASIN (V
ASIP
- V
ASIN
)
-0.3
40
V
2
V
ASIPP
AS-i supply pulse voltage, voltage difference between pins
ASIP and ASIN (from ASIP to ASIN)
50
V
3
V
UIN
Aux. power supply input voltage
-0.3
40
V
V
UINPV
Aux. power supply input voltage pulse
50
V
3
V
inputs1
Voltage at pins DI3 - DI0, DO3 - DO0, P3 - P0, DSR, PST,
LED, FID, U
OUT
-0.3
V
UIN
+
0.3
V
V
inputs1
40V
V
inputs2
Voltage at pins OSC1, OSC2, IRD, CAP, U5R, U5RD
-0.3
7
V
I
in
Input current into any pin except supply pins
-25
25
mA
H
Humidity non-condensing
4
V
HBM1
Electrostatic discharge human body model (HBM1)
4000
V
5
V
HBM2
Electrostatic discharge human body model (HBM2)
2000
V
6
V
EDM
Electrostatic discharge equipment discharge model (EDM)
400
V
7
STG
Storage temperature
-55
125
C
P
tot
Total power dissipation
0.85
W
8
1 ASIN-pin shall be shorted to 0V-pin on PCB.
2 Reverse polarity protection has to be performed externally.
3 Pulse with
50s, repetition rate
0.5 Hz.
4 Level 4 according to JEDEC-020A is guaranteed
5 HBM1: C = 100pF charged to V
HBM1
with resistor R = 1.5k
in series, valid for ASIP-ASIN only.
6
HBM2: C = 100pF charged to V
HBM2
with resistor R = 1.5k
in series, valid for all pins except ASIP-ASIN.
7
EDM: C = 200pF charged to V
EDM
with no resistor in series, valid for ASIP-ASIN only.
8 At maximum operating temperature, the allowed total power dissipation depends on the additional thermal resistance from case to
ambient and on the operation ambient temperature (see Figure 6).
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance
may occur if this device is subjected to high-energy electrostatic discharge.
Rev. 2.5, Copyright 2002, ZMD AG
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Information furnished in this publication is preliminary and subject to changes without notice.
14/30
ASI
Data Sheet
Advanced AS-Interface IC
Figure 6: Maximum Power Dissipation,
P
TOT
= f(Ambient Temperature)











Table 4: Operating Conditions
SYMBOL
PARAMETER
MIN.
MAX.
UNITS NOTE
V
UIN
Positive supply voltage
16
33.1
V
1
V
ASIN
Negative AS-i supply voltage
0
0
V
2
V
0V
, V
GND
Negative supply voltage
0
0
V
I
ASI
Supply current at V
ASI
= 30V
9
mA
3
I
CL1
Max. output sink current at pins DO3 - DO0, DSR
10
mA
I
CL2
Max. output sink current at pins P0 - P3, PST
10
mA
amb
Ambient temperature range, operating range
-25
85
C
1 DC voltage
2 ASIN shall be shorted with 0V to ensure proper functionality of transmitter circuit.
3 f
c
= 8.000 MHz, no load at any pin without reaction of the circuit, ASIP is short-cut to UIN and ASIN to 0V respectively.
8.2 DC and AC Characteristics
All parameters are valid for the recommended range of V
ASIP
- V
ASIN
, V
UIN
- V
0V
, and
amb. The devices are
tested within the recommended range of V
ASIP
- V
ASIN
, V
IN
- V
0V
,
amb = +25C (+ 85C and - 25C on sample
base only) unless otherwise stated. Unused input pins shall be connected to a suitable potential within the
application circuit because there are no internal pull-up/down resistors. It is recommended to connect these pins
either to 0V or via resistor to U
OUT
or U5R respectively.
With an external LOW signal at the data strobe pin DSR (pull-down open drain driver) for more than 44s, the IC
will execute its reset procedure. During power on procedure all data and parameter ports will stay on high-
impedance state.
If the IC has been put in its initialization procedure by an external reset via DSR, the LED pin should not be
toggled externally to avoid that the IC control logic transfers to test mode.
Ptot = f (Ta); 1L / 2L = 1 layer / 2 layer PCB
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
-25
0
25
50
75
100
Ta
Ptot (2L)
Ptot (1L)
Rev. 2.5, Copyright 2002, ZMD AG
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Information furnished in this publication is preliminary and subject to changes without notice.
15/30
ASI
Data Sheet
Advanced AS-Interface IC
8.2.1 Digital Input and Output Pins
Table 5: Input/Output Voltage and Current
SYMBOL PARAMETER
MIN.
MAX.
UNITS
NOTE
Pins DI0 - DI3, P0 - P3, DSR, FID, PST
V
IL
Voltage range for input "low" level, not P0 P3
0
2.5
V
V
IL
Voltage range for input "low" level, only P0 P3
0
2.4
V
V
ICH
Voltage range for input "high" level
3.5
V
UOUT
V
V
HYST
Hysteresis for switching level
0.25
V
1
I
IL
Current range for input "low" level
-20
-5
A
I
ICH
Current range for input "high" level
-10
10
A
V
O
= 5V
I
IHV
Current range for high voltage input
2
mA
V
O
= 30V
Pins DO0 - DO3, P0 - P3, DSR, PST
V
OL1
Voltage range for output "low" level
0
1
V
I
OL1
= 10mA
V
OL2
Voltage range for output "low" level
0
0.4
V
I
OL2
= 2mA
I
OH
Output leakage current
-10
10
A
V
OH
= 4.5V
CDL
Capacitance at pin DSR
10
pF
2
Pin LED
V
OL
Voltage range for output "low" level
0
1
V
I
OL1
= 10mA
3
I
OH
Output leakage current
-10
30
A
V
OH
= 40V
4
1 Switching level approximately 3V, i.e. 3V
V
HYST
.
2 For higher capacitive load an external pull-up resistor connected to UOUT is necessary to reach V
IH
3.5V at DSR in less than 35 s
after the beginning of a DSR = Low pulse, otherwise a reset will be executed.
3 The output driver sends a "low" (LED on).
4 The output driver sends a "high" (equivalent to tri-state, LED off).
Rev. 2.5, Copyright 2002, ZMD AG
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Information furnished in this publication is preliminary and subject to changes without notice.
16/30
ASI
Data Sheet
Advanced AS-Interface IC
Table 6: Timing Parameter Port
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
NOTE
t
setup
Valid output data; P0 - P3 to PST-H/L
0.1
0.5
s
Figure 7
t
PST
PST pulse width
5
6
s
t
PI-latch
PST-H/L to parameter input latch
11
13.5
s
1
t
CYCLE
Next cycle
150
s
1 The parameter input data must be stable within the period that is defined by minimum and maximum t
PI-latch
.
PST
tsetup
tPST
tCYCLE
tPI-latch
Parameter port output data
parameter input value (PIx) = parameter output value (POx) wired AND
with external signal source value
keep stable
m in
max
PO0-PO3
Figure 7: Timing Diagram Parameter Port P0 - P3
Rev. 2.5, Copyright 2002, ZMD AG
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Information furnished in this publication is preliminary and subject to changes without notice.
17/30
ASI
Data Sheet
Advanced AS-Interface IC
Table 7: Timing Data Port Outputs
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
NOTE
t
setup
Valid output data; DO0 - DO3 to DSR-H/L
0.1
0.5
s
Figure 8
t
hold
Valid output data; DO0 - DO3 to DSR-L/H
0.1
0.5
s
t
DSTR
DSR pulse width
5
6
s
t
DI-latch
DSR-H/L to data input latch
11
13.5
s
1
t
CYCLE
Next cycle
150
s
1 The data input must be stable within the period that is defined by minimum and maximum of t
DI-latch
.
DSR
tsetup
tDSR
tCYCLE
tDI-latch
Data port output data
keep stable
min
max
DO0-DO3
DI0-DI3
Data port input data
thold
data remains, if multiplex
flag is not set
hi-z, if multiplex flag is set
Figure 8: Timing Diagram Data Port DO0 - DO3
Rev. 2.5, Copyright 2002, ZMD AG
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Information furnished in this publication is preliminary and subject to changes without notice.
18/30
ASI
Data Sheet
Advanced AS-Interface IC
Table 8: Timing Reset Signal
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
NOTE
t
ALM1
Ext. DSR (no reset)
35
s
Figure 9
t
ALM2
Ext. DSR to DO0 - DO3 Hi-Z
44
s
t
RESET1
Reset time after DSR = external L ->H transition
2
ms
DSR
DO0-DO3
tALM1
tALM2
>0
tRESET1
hi-z
PO0-PO3
hi-z
Data port output data
Parameter port output data
Figure 9: Timing Diagram External Reset via DSR
Rev. 2.5, Copyright 2002, ZMD AG
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Information furnished in this publication is preliminary and subject to changes without notice.
19/30
ASI
Data Sheet
Advanced AS-Interface IC
8.2.2 Addressing Channel Input IRD
The addressing channel input IRD is a dedicated photo-diode input. The photo-diode can be connected to the
pins IRD and 0V directly. The IRD input is a AC current input. A valid signal at the current input has to have a
certain amplitude (range) and should not exceed a certain offset value. A logic "low" at the IRD input will be
detected, if the present signal value drops below I
IRDO
, and a "high" will be detected, if its present value is greater
than I
IRDO
+ I
IRDA
.
Table 9: AC Current Amplitude of IR Diode Input in Slave Mode
SYMBOL PARAMETER
MIN.
MAX.
UNITS NOTE
I
IRDO
Input current offset
10
A
PP
I
IRDA
Input current amplitude
10
100
A
PP
IC Revision A&B
I
IRDA
Input current amplitude
25
100
A
PP
IC Revision C
Table 10: Digital Input IRD in Master/Repeater Mode
SYMBOL PARAMETER
MIN.
MAX.
UNITS NOTE
V
IL
Voltage range for input "low" level
0
2.5
V
V
ICH
Voltage range for input "high" level
3.5
V
U5R
V
T
r
/T
f
Rise/fall time
100
ns
1
1 In order to avoid jittery on the AS-i line, the rise/fall time of the IRD input signal should be as low as possible.
8.2.3 Fault Indication Input, FID
The fault indication input FID is a digital input dedicated for a periphery fault messaging signal. The S1 status bit
is equivalent to the FID input signal. A FID transition will occur at S1 with a certain delay, because a synchronizer
circuit is put in between.
MIN
I
IRDA
MAX
I
IRDA
MAX
I
IRDO
time
IRD
input
current
Figure 10:
Photo Current Waveform
Rev. 2.5, Copyright 2002, ZMD AG
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20/30
ASI
Data Sheet
Advanced AS-Interface IC
8.3 Voltage Outputs
Table 11: Properties of Voltage Output Pins U
OUT
and U5R
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
NOTE
V
UOUT
U
OUT
output supply voltage
V
UIN
-
V
DROPmax
V
UIN
-
V
DROPmin
V
I
UOUT
= 30mA
V
UOUTp
U
OUT
output voltage pulse deviation
1.5
V
1
t
UOUTp
U
OUT
output voltage pulse deviation width
2
ms
1
V
DROP
Voltage drop from pin U
IN
to pin U
OUT
6.5
7.7
V
V
UIN
> 22V
V
U5R
5V supply voltage
4.5
5.5
V
I
UOUT
U
OUT
output supply current
0
30
mA
I
U5R
= 0 mA
I
5V
U5R output supply current
0
4
mA
I
UOUT
< 26 mA
I
o
Total voltage output current I
UOUT
+ I
5V
30
mA
I
UOUTS
Short circuit output current
50
mA
C
LUOUT
Load capacitance at U
OUT
10
470
F
C
L5V
Load capacitance at U5R
1
F

1 COUT = 10 F, output current switches from 0 to 30 mA and vice versa.
2 11.0V < VOUT < 27.6V.
Rev. 2.5, Copyright 2002, ZMD AG
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21/30
ASI
Data Sheet
Advanced AS-Interface IC
8.3.1 AS-i Bus Load
The following parameters are determined with short-cut between the pins ASIP and UIN and the pins ASIN and
0V, respectively.
Table 12: AS-i Bus Interface Properties (Pins ASIP/ASIN and U
IN
)
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
NOTE
V
UIN
Input AS-i voltage at U
IN
V
UOUTmin
+
V
DROPmax
V
UOUTmax
+ V
DROPmin
V
1
I
LIN
Input current limit at U
IN
56
mA
V
SIG
Input signal voltage difference between ASIP and
ASIN
3
8
V
PP
I
SIG
Modulated output peak current from ASIP to ASIN
55
68
mA
P
C
Zener
Parasitic capacitance of the external over-voltage
protection diode (zener diode)
20
pF
2
R
IN1
Equivalent resistor of the device
16
k
2, 3
L
IN1
Equivalent inductor of the device
18
mH
2, 3
C
IN1
Equivalent capacitor of the device
30
pF
2, 3
R
IN2
Equivalent resistor of the device
16
k
2, 3
L
IN2
Equivalent inductor of the device
12
18
mH
2, 3
C
IN2
Equivalent capacitor of the device
15 + (L-12mH)*
2.5pF/mH
pF
2, 3
1 DC Parameter
2 The equivalent circuit of a slave (which is calculated from the impedance of the device and the paralleled external over-voltage
protection diode (zener diode)) has to satisfy the Complete AS-i-Specification v.2.1 concerning the requirements for the extended
address range.
3 Subtracting the maximum parasitic capacitance of the external over voltage protection diode (20pF) either the triple RIN1, LIN1 and
CIN1 or the triple R
IN2
, L
IN2
and C
IN2
has to be committed by the device to fulfill the Complete AS-i-Specification v2.1.
8.3.2 Input Impedance Control
Table 13: CAP Pin
SYMBOL
PARAMETER
MIN.
MAX.
UNITS NOTE
R
CAP
External filter resistor
0
2.2
k
1
C
CAP
External filter capacitor
4.7
100
nF
1, 2
1 Recommended values for optimal impedance are:
R
CAP
= 1.2 k
and C
CAP
= 10 nF
(IC Revision A)
R
CAP
= 430 680
and C
CAP
= 4.7 nF
(IC Revision B and C)
See chapter 11, Package Marking, for details on how to distinguish different IC versions.
2 The de-coupling capacitor and serial resistor define internal low-pass filter time constant; lower values decrease the impedance but
improve the turn-on time. Higher values do not improve the impedance but do increase the turn-on time. The turn-on time also
depends on the load capacitor at UOUT. After connecting the slave to the power the capacitor is charged with the maximum current
IUOUT. The impedance will increase when the voltage allows the analog circuitry to fully operate.
Rev. 2.5, Copyright 2002, ZMD AG
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
22/30
ASI
Data Sheet
Advanced AS-Interface IC
8.3.3 Oscillator
Table 14: Oscillator Pins (OSC1 and OSC2)
SYMBOL PARAMETER
MIN.
MAX.
UNITS NOTE
C
OSC
External parasitic capacitor at oscillator pins
OSC1, OSC2
0
5
pF
V
IL
Input "low" voltage
0
1.5
V
1
V
ICH
Input "high" voltage
3.5
V
U5R
V
1 For external clock applied to OSC1 only.
9 Development Information Data
Table 15: Information Data
Conditions: Asynchronous mode, reset to default comparator level at ,,line pause".
Symbol
PARAMETER
MIN.
MAX.
UNITS NOTE
V
LSIGon
Receiver comparator threshold level
(see Figure 11)
45
50
%
Related to
amplitude of 1
st
pulse
t
reset1
Reset time after Master Call ,,Reset AS-i-Slave" or
DSR = external L ->H transition
2
ms
1
t
reset2
Reset time after power on
30
ms
2
t
reset3
Reset time after power on with high capacitive load
1000
ms
3
V
ASIP-PF
V
ASIP
voltage to detect power fail (master mode
only)
21.5
23.5
V
t
Loff
Power supply break down time (master mode only)
0.7
0.9
ms
4
V
POR1F
V
U5R
voltage to trigger internal reset procedure,
falling voltage
3.0
4.0
V
1
V
POR1R
V
U5R
voltage to trigger INIT procedure, rising
voltage
2.5
3.5
V
1
t
Low
Power-on reset pulse width
4
6
s
T
Shut
Chip temperature for thermal shut down
(overheating)
125
160
C

1 Guaranteed by design only.
2 `Power_on' starts latest at VUIN = 18V, external capacitor at pin UOUT = 10F.
3 CUOUT = 470F, treset3 is guaranteed by design only.
4 CUOUT > 10F, no power fail generated at VASIP < VASIP-PF for t < tLoff (in master mode only).
Rev. 2.5, Copyright 2002, ZMD AG
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
23/30
ASI
Data Sheet
Advanced AS-Interface IC
First negative
pulse of the
AS-i telegram
V
LSIGon
V
LSIGon
= (0.45 - 0.50) * V
SIG
/ 2
The IC determines the
amplitude of the first
negative pulse of the
AS-i telegram. This
amplitude is asserted
to be V
SIG
/ 2.
"DC level"
V
SIG
/ 2
Figure 11: Receiver Comparator Set Up
V
ASIP
V
POR1R
V
POR1F
V
UIN
V
U5R
POR (active low)
No reset, but if the break down
time exceeds t
Loff
, a power-fail
signal will be generated
Reset will
be initalized
< ca. 15V
0V
t
Loff
V
ASIP-PF
t
Low
Power-on Reset will
be active, if the V
U5R
drops below V
POR1F
MASTER MODE only
All Modes
V
ASIN
Figure 12: Power-Fail Generation (in Master Mode) and Reset Behavior (All Modes)
Rev. 2.5, Copyright 2002, ZMD AG
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
24/30
ASI
Data Sheet
Advanced AS-Interface IC
10 Application Circuits
The following figures show typical application cases of the A
2
SI IC. Figure 14 shows an application circuit in
which the A
2
SI is replacing an ASI3+ circuit. Finally, Figure 15 shows how the A
2
SI circuit can be used to
perform the analog/digital interface between the AS-i-line and the master electronics. Furthermore this figure
shows that the IC can be used in repeater applications as well.
10.1 EMC Precautions
Precaution must be taken to avoid radio frequency interference. It is recommended to keep input lines as short
as possible and to connect unused inputs to U
OUT
through a pull-up resistor. Furthermore, the supply pins should
be de-coupled with ceramic capacitors (10 to 100 nF) in addition to the normal de-coupling capacitors. Also, it is
recommended to connect a pull-up resistor from DSR (pin 22) to U
OUT
or U5R in order to avoid unintentional
reset under difficult EMC conditions.
10.2 Typical Slave Application
Note: Figure 13 and Figure 14 show all digital (data and parameter) ports without the application specific
connections. For correct function, it is important to consider that all output drivers are open drain stages and
hence each port must be connected with an appropriate pull-up resistor.
ASI
ASI
8 MHz
C
CAP
DSR
PST
FID
LED
IRD
GND
0V
U
IN
U
OUT
U5R
U5RD
OSC1
CAP
ASIP
ASIN
10
F
2.2F
A
2
SI
OSC2
0V
+24V
+5V
DI0
DI1
DI2
DI3
DO0
DO1
DO2
DO3
P0
P1
P2
P3
DI_0
DI_1
DI_2
DI_3
DO_0
DO_1
DO_2
DO_3
P0
P1
P2
P3
DS&Reset
PST
Fault Input
39V/1W
R
CAP
RED
GREEN
10n
10n
17
18
19
20
11
10
9
8
16
15
14
13
22
21
5
23
26
27
24
4
12
3
25
2
1
6
7
28
22 k
Figure 13: Typical Application, Slave Mode
Rev. 2.5, Copyright 2002, ZMD AG
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
25/30
ASI
Data Sheet
Advanced AS-Interface IC
10.3 Typical ASI3+ Compatible Application
Note: Depending on I/O-configuration, DO- and DI-ports are connected and Multiplex-Flag is set.
ASI
ASI
C
CAP
DSR
PST
FID
LED
IRD
GND
0V
U
IN
U
OUT
U5R
U5RD
CAP
ASIP
ASIN
10
F
2.2F
A
2
SI
8 MHz
OSC1
OSC2
0V
+24V
+5V
DI0
DI1
DI2
DI3
DO0
DO1
DO2
DO3
P0
P1
P2
P3
DIO-0
DIO-1
DIO-2
DIO-3
P0
P1
P2
P3
DS&Reset
PS
39V/1W
R
CAP
10n
10n
22
21
5
24
4
26
17
18
19
20
11
10
9
8
16
15
14
13
23
27
12
7
6
28
1
2
25
3
22 k
Figure 14: Typical ASI3+ Compatible Application
Rev. 2.5, Copyright 2002, ZMD AG
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
26/30
ASI
Data Sheet
Advanced AS-Interface IC
10.4 Typical Master/Repeater Application
For further information see also ASI Application Note.
ASI+
ASI
8 MHz
C
CAP
DSR
PST
FID
LED
IRD
GND
0V
U
IN
U
OUT
U5R
U5RD
OSC1
CAP
ASIP
ASIN
2.2F
10
F
A
2
SI
OSC2
DI0
DI1
DI2
DI3
DO0
DO1
DO2
DO3
P0
P1
P2
P3
39V
+U
B
Vo
GND
+U
B
Vo
GND
+U
B
Vo
GND
+U
B
Vo
GND
+5V
REC-CLK
(optional)
REC-STRB
(optional)
RECEIVE
DATA
SEND
0V
ISOLATION
/POWER-FAIL
R
CAP
10n
10n
27
16
15
14
13
22
5
24
23
26
4
21
12
3
25
2
1
6
7
28
Figure 15: Master/Repeater Application
Rev. 2.5, Copyright 2002, ZMD AG
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
27/30
ASI
Data Sheet
Advanced AS-Interface IC
11 Package Outline

Table 16: Package Dimensions (mm)
Symbol
A
A1
A2
B
C
D
E
e
H
L
Nominal
1.86
0.13
1.73
0.30
0.15
10.20
5.30
7.80
0.75
4
Maximum
1.99
0.21
1.78
0.38
0.20
10.33
5.38
7.90
0.95
8
Minimum
1.73
0.05
1.68
0.25
0.13
10.07
5.20
0.65
BSC
7.65
0.55
0
Figure 16: SSOP Package
Figure 17: Package Dimensions
Rev. 2.5, Copyright 2002, ZMD AG
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
28/30
ASI
Data Sheet
Advanced AS-Interface IC
12 Package Marking
Top Marking:
ASI
Product name
ZMD
Manufacturer
R-
Revision code
XXXX
Date code (year and week)
Y
Assembly location
ZZ
Traceability

Bottom Marking:
LLLLLL
ZMD Lot Number

The yellow dot indicating pre-programmed Master function is printed at the pin 1 marking
.

Note: IC Revision A did not have a revision code marking. ICs without a Revision Code are equivalent to
Revision A. Revision B shows "B-", Revision C shows "C-".
PIN 1
TOP VIEW
BOTTOM
VIEW
PIN 1
LLLLLL
A
2
SI ZMD
R-XXXXYZZ
+
Figure 18: Package Marking
Rev. 2.5, Copyright 2002, ZMD AG
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
29/30
ASI
Data Sheet
Advanced AS-Interface IC
13 Evaluation boards for ASI
Evaluation board equipped with ASI can be ordered from Bihl+Wiedeman GmbH
(www.bihl-wiedemann.de)
Figure 19: Evaluation board dimensions (L x W x H):(34 x 31 x 8) mm
14 Ordering Information
Ordering
Code
Description
Operating Temperature
Range
Package Type
Device
Marking
Shipping Form
A2SI-ST Standard version of
ASI
-25C to 85C
28-pin SSOP
(5.3 mm)
ASI
Tubes
(47 parts/tube)
A2SI-SR Standard version of
ASI
-25C to 85C
28-pin SSOP
(5.3 mm)
ASI
Tape-and-Reel
(1500 parts/reel)
A2SI-MT
Pre-programmed
master function
-25C to 85C
28-pin SSOP
(5.3 mm)
ASI
+ yellow dot
Tubes
(47 parts/tube)
A2SI-MR
Pre-programmed
master function
-25C to 85C
28-pin SSOP
(5.3 mm)
ASI
+ yellow dot
Tape-and-Reel
(1500 parts/reel)
Rev. 2.5, Copyright 2002, ZMD AG
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The
Information furnished in this publication is preliminary and subject to changes without notice.
30/30
ASI
Data Sheet
Advanced AS-Interface IC
15 Application Support
15.1 AS-International Association
Documentation and promotional materials as well as detailed technical specifications regarding the AS-Interface
Bus Standard are available from:
AS-
International
Association:
Contact - Rolf Becker
Zum Taubengarten 52
D-63571 Gelnhausen
PO Box 1103 Zip (63551)
Tel: +49 6051 47 32 12
Fax: +49 6051 4732 82
Email: as-interface@t-online.de
http://www.as-interface.net
Refer to the Association's website here above for contact info on nine local AS-Interface associations which
provide local support within Europe, in the US and in Japan.
15.2 ZMD
An Application Note an ASI can be found under www.zmd.biz
ASI device related application support requests can be addressed to asi@zmd.de
15.3 ZMD
Since the ASI-E is a high performance package option of the ASI the application notes ASI apply. The
Application Note ASI can be found under www.biz.com.
ASI/ASI-E device related application support requests can be addressed to asi@zmd.de.
15.4 ZMD Application Support Partners
ZMD
Application
Support
Partners:
Bihl+Wiedemann
Flosswoerthstrasse 41
D-68199 Mannheim, Germany
Tel.: +49 621 3 3996 0
Fax: +49 621 3 3922 39
Email: mail@bihl-wiedemann.de
http://www.bihl-wiedemann.de
Fieldbus specialists
217 Colchester Road, Kilsyth
3137 Victoria, Australia
Tel.: +61 3 9761 4653
Fax: +61 3 9761 5525
Email:
fs_sales@fieldbus.com.au
http://www.fieldbus.com.au
16
Sales Contacts
For further
information:
ZMD Stuttgart Office
Nord-West-Ring 34
70974 Filderstadt - Bernhausen
Tel.: +49 (0)711.674.517-0
Fax: +49 (0)711.674.517-99
sales@zmd.de
ZMD AG
Grenzstrasse 28
01109 Dresden, Germany
Tel.: +49 (0)351.8822.310
Fax: +49 (0)351.8822.337
sales@zmd.de
ZMD America Inc.
201 Old Country Road, Ste 204
Melville, NY 11747
Tel.: (631) 549-2666
Fax: (631) 549-2882
sensors@zmda.com

Products sold by ZMD are covered exclusively by the warranty, patent indemnification and other provisions appearing in ZMD standard "Terms of Sale". ZMD
makes no warranty (express, statutory, implied and/or by description), including without limitation any warranties of merchantability and/or fitness for a particular
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notice. ZMD products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements,
or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional mutually
agreed upon processing by ZMD for such applications.
ZMD reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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