--Active Read Current Less Than 1mA
--Active Write Current Less Than 3mA
--Standby Current Less Than 1
--Software Write Protection
--Programmable hardware Write Protect
--Minimizes Total Write Time Per Byte
--Typical Write Cycle Time of 5ms
--Endurance: 100,000 Cycles
--Data Retention: 100 Years
--8-Lead SOIC (JEDEC)
serial interface and software protocol allowing opera-
tion on a simple two wire bus.
tion, FFFh, provides three new write protection
features: Software Write Protect, Block Write Protect,
and Hardware Write Protect. The Software Write
Protect feature prevents any nonvolatile writes to the
X24325 until the WEL bit in the write protect register is
set. The Block Write Protection feature allows the user
to individually write protect four blocks of the array by
programming two bits in the write protect register. The
Programmable Hardware Write Protect feature allows
the user to install the X24325 with WP tied to V
enable the hardware write protection by programming
a WPEN bit in the write protect register. After this,
selected blocks of the array, including the write protect
register itself, are permanently write protected.
retention is greater than 100 years.
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs.
resistor. For selecting typical values, refer to the Pull-
Up Resistor selection graph at the end of this data
allows up to eight X24325's to share a common bus.
These inputs can be static or actively driven. If used
statically they must be tied to V
CMOS levels (driven to V
protect feature. When held LOW, hardware write
protection is disabled and the X24325 can be written
normally. When this input is held HIGH, and the WPEN
bit in the write protect register is set HIGH, write
protection is enabled, and nonvolatile writes are
disabled to the selected blocks as well as the write
protect register itself.
tocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers, and pro-
vide the clock for both transmit and receive operations.
Therefore, the X24325 will be considered a slave in all
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24325 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus.
successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 3.
recognition of a start condition and its slave address. If
both the device and a write operation have been
selected, the X24325 will respond with an acknowl-
edge after the receipt of each subsequent eight-bit
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the X24325
will continue to transmit data. If an acknowledge is not
detected, the X24325 will terminate further data trans-
missions. The master must then issue a stop condition
to return the X24325 to the standby power mode and
place the device into a known state.
address of the slave it is accessing (see Figure 4). The
next three bits are the device select bits. A system
could have up to eight X24325's on the bus. The eight
addresses are defined by the state of the S
sion of the array's address and are concatenated with
the eight bits of address in the word address field,
providing direct access to the whole 4096 x 8 array.
be performed. When set HIGH a read operation is
selected, when set LOW a write operation is selected.
SDA bus comparing the slave address being transmitted
with its slave address device type identifier. Upon a
correct compare the X24325 outputs an acknowledge on
the SDA line. Depending on the state of the R/W bit, the
X24325 will execute a read or write operation.
dress field. This address field is the word address, com-
prised of eight bits, providing access to any one of 4096
words in the array. Upon receipt of the word address, the
X24325 responds with an acknowledge and awaits the
next eight bits of data, again responding with an acknowl-
edge. The master then terminates the transfer by gener-
ating a stop condition, at which time the X24325 begins
the internal write cycle to the nonvolatile memory. While
the internal write cycle is in progress the X24325 inputs
are disabled, and the device will not respond to any re-
quests from the master. Refer to Figure 5 for the address,
acknowledge and data transfer sequence.