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Datasheet: X24325PI-2.7 (Xicor Inc.)

Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection

 

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Xicor Inc.

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Advanced 2-Wire Serial E
2
PROM with Block Lock
TM
Protection
32K
4096 x 8 Bit
Preliminary Information
Xicor, 1995, 1996 Patents Pending
6552-2.4 5/13/96 T1/C10/D0 NS
1
Characteristics subject to change without notice
X24325
FUNCTIONAL DIAGRAM
FEATURES
2.7V to 5.5V Power Supply
Low Power CMOS
--Active Read Current Less Than 1mA
--Active Write Current Less Than 3mA
--Standby Current Less Than 1
A
Internally Organized 4096 x 8
New Programmable Block Lock Protection
--Software Write Protection
--Programmable hardware Write Protect
Block Lock (0, 1/4, 1/2, or all of the E
2
PROM
array)
2 Wire Serial Interface
Bidirectional Data Transfer Protocol
32 Byte Page Write Mode
--Minimizes Total Write Time Per Byte
Self Timed Write Cycle
--Typical Write Cycle Time of 5ms
High Reliability
--Endurance: 100,000 Cycles
--Data Retention: 100 Years
Available Packages
--8-Lead PDIP
--8-Lead SOIC (JEDEC)
--14-Lead TSSOP
DESCRIPTION
The X24325 is a CMOS 32,768 bit serial E
2
PROM,
internally organized 4096 x 8. The X24325 features a
serial interface and software protocol allowing opera-
tion on a simple two wire bus.
Three device select inputs (S
0
, S
1
, S
2
) allow up to
eight devices to share a common two wire bus.
A Write Protect Register at the highest address loca-
tion, FFFh, provides three new write protection
features: Software Write Protect, Block Write Protect,
and Hardware Write Protect. The Software Write
Protect feature prevents any nonvolatile writes to the
X24325 until the WEL bit in the write protect register is
set. The Block Write Protection feature allows the user
to individually write protect four blocks of the array by
programming two bits in the write protect register. The
Programmable Hardware Write Protect feature allows
the user to install the X24325 with WP tied to V
CC
,
program the entire memory array in place, and then
enable the hardware write protection by programming
a WPEN bit in the write protect register. After this,
selected blocks of the array, including the write protect
register itself, are permanently write protected.
Xicor E
2
PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
START
STOP
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER
+COMPARATOR
H.V. GENERATION
TIMING &
CONTROL
WORD
ADDRESS
COUNTER
XDEC
YDEC
DOUT
ACK
E
2
PROM
128 X 256
DATA REGISTER
START CYCLE
VCC
R/W
PIN
VSS
SDA
SCL
S0
S1
DOUT
LOAD
INC
CK
8
6552 ILL F01.1
WRITE PROTECT
REGISTER AND
LOGIC
WP
S2
X24325
2
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-
Up Resistor selection graph at the end of this data
sheet.
Device Select (S
0
, S
1
, S
2
)
The device select inputs (S
0
, S
1
, S
2
) are used to set
the first three bits of the 8-bit slave address. This
allows up to eight X24325's to share a common bus.
These inputs can be static or actively driven. If used
statically they must be tied to V
SS
or V
CC
as appro-
priate. If actively driven, they must be driven with
CMOS levels (driven to V
CC
or V
SS
).
Write Protect (WP)
The write protect input controls the hardware write
protect feature. When held LOW, hardware write
protection is disabled and the X24325 can be written
normally. When this input is held HIGH, and the WPEN
bit in the write protect register is set HIGH, write
protection is enabled, and nonvolatile writes are
disabled to the selected blocks as well as the write
protect register itself.
PIN NAMES
6552 FRM T01.1
Symbol
Description
S
0
, S
1
,
S
2
Device Select Inputs
SDA
Serial Data
SCL
Serial Clock
WP
Write Protect
V
SS
Ground
V
CC
Supply Voltage
NC
No Connect
PIN CONFIGURATIONS
6552 ILL F02.5
S0
S1
NC
NC
NC
S2
VSS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
WP
NC
NC
NC
SCL
SDA
X24325
14-LEAD TSSOP
VCC
WP
SCL
SDA
S0
S1
S2
VSS
1
2
3
4
8
7
6
5
X24325
8-LEAD DIP & SOIC
X24325
3
DEVICE OPERATION
The X24325 supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers, and pro-
vide the clock for both transmit and receive operations.
Therefore, the X24325 will be considered a slave in all
applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24325 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
SCL
SDA
DATA STABLE
DATA
CHANGE
6552 ILL F04
SCL
SDA
START BIT
STOP BIT
6552 ILL F05
Figure 1. Data Validity
Figure 2. Definition of Start and Stop
Notes:
(5) Typical values are for T
A
= 25
C and nominal supply voltage (5V)
(6) t
WR
is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the
device requires to perform the internal write operation.
X24325
4
Figure 3. Acknowledge Response From Receiver
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 3.
The X24325 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write operation have been
selected, the X24325 will respond with an acknowl-
edge after the receipt of each subsequent eight-bit
word.
In the read mode the X24325 will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the X24325
will continue to transmit data. If an acknowledge is not
detected, the X24325 will terminate further data trans-
missions. The master must then issue a stop condition
to return the X24325 to the standby power mode and
place the device into a known state.
6552 ILL F06
SCL FROM
MASTER
DATA OUTPUT
FROM
TRANSMITTER
1
8
9
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
X24325
5
Figure 5. Byte Write
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24325
S
T
A
R
T
SLAVE
ADDRESS
S
S
T
O
P
P
A
C
K
A
C
K
A
C
K
WORD
ADDRESS
DATA
6552 ILL F08
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing (see Figure 4). The
next three bits are the device select bits. A system
could have up to eight X24325's on the bus. The eight
addresses are defined by the state of the S
0
, S
1
and
S
2
inputs. S
0
and S
2
of the slave address must be the
inverse of the S
0
and S
2
input pins.
Figure 4. Slave Address
The next four bits of the slave address are an exten-
sion of the array's address and are concatenated with
the eight bits of address in the word address field,
providing direct access to the whole 4096 x 8 array.
6552 ILL F07.2
S2
A9
A8
R/W
DEVICE
SELECT
S1
S0
HIGH ORDER
WORD
ADDRESS
A11
A10
The last bit of the slave address defines the operation to
be performed. When set HIGH a read operation is
selected, when set LOW a write operation is selected.
Following the start condition, the X24325 monitors the
SDA bus comparing the slave address being transmitted
with its slave address device type identifier. Upon a
correct compare the X24325 outputs an acknowledge on
the SDA line. Depending on the state of the R/W bit, the
X24325 will execute a read or write operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24325 requires a second ad-
dress field. This address field is the word address, com-
prised of eight bits, providing access to any one of 4096
words in the array. Upon receipt of the word address, the
X24325 responds with an acknowledge and awaits the
next eight bits of data, again responding with an acknowl-
edge. The master then terminates the transfer by gener-
ating a stop condition, at which time the X24325 begins
the internal write cycle to the nonvolatile memory. While
the internal write cycle is in progress the X24325 inputs
are disabled, and the device will not respond to any re-
quests from the master. Refer to Figure 5 for the address,
acknowledge and data transfer sequence.
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