serial interface and software protocol allowing operation
on a simple two wire bus.
tention is greater than 100 years.
--Active Read Current Less Than 1 mA
--Active Write Current Less Than 3 mA
--Standby Current Less Than 50
--Bidirectional Data Transfer Protocol
--Minimizes Total Write Time Per Byte
--Typical Write Cycle Time of 5 ms
--Endurance: 100,000 Cycles
--Data Retention: 100 Years
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open
resistor. For selecting typical values, refer to the Pull-Up
Resistor selection graph at the end of this data sheet.
This allows up to eight X24164's to share a common
bus. These inputs can be static or actively driven. If used
statically they must be tied to V
tied to V
LOW. SDA state changes during SCL HIGH are re-
served for indicating start and stop conditions. Refer to
Figures 1 and 2.
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24164 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
col. The protocol defines any device that sends data onto
the bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is a master
and the device being controlled is the slave. The master
will always initiate data transfers, and provide the clock for
both transmit and receive operations. Therefore, the
X24164 will be considered a slave in all applications.
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus.
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 3.
recognition of a start condition and its slave address. If
both the device and a write operation have been se-
lected, the X24164 will respond with an acknowledge
after the receipt of each subsequent eight bit word.
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the X24164
will continue to transmit data. If an acknowledge is not
detected, the X24164 will terminate further data trans-
missions. The master must then issue a stop condition
to return the X24164 to the standby power mode and
place the device into a known state.
address of the slave it is accessing. The most significant
bit of the slave is a one (see Figure 4). The next three bits
are the device select bits. A system could have up to
eight X24164's on the bus. The eight addresses are
defined by the state of the S
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
SDA bus comparing the slave address being transmit-
ted with its slave address device type identifier. Upon a
correct compare the X24164 outputs an acknowledge
on the SDA line. Depending on the state of the R/
address field. This address field is the word address,
comprised of eight bits, providing access to any one of
2048 words in the array. Upon receipt of the word
address the X24164 responds with an acknowledge,
and awaits the next eight bits of data, again responding
with an acknowledge. The master then terminates the
transfer by generating a stop condition, at which time the
X24164 begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress the
X24164 inputs are disabled, and the device will not
respond to any requests from the master. Refer to
Figure 5 for the address, acknowledge and data transfer
of the array's address and are concatenated with the
eight bits of address in the word address field, providing
direct access to the whole 2048 x 8 array.