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Datasheet: X20C04E-20 (Xicor Inc.)

Nonvolatile Static RAM

 

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Xicor Inc.

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X20C04
1
Xicor, Inc. 1992, 1995, 1996 Patents Pending
Characteristics subject to change without notice
3825-2.8 7/31/97 T4/C0/D0 SH
Nonvolatile Static RAM
DESCRIPTION
The Xicor X20C04 is a 512 x 8 NOVRAM featuring a
static RAM overlaid bit-for-bit with a nonvolatile electri-
cally erasable PROM (E
2
PROM). The X20C04 is fabri-
cated with advanced CMOS floating gate technology to
achieve low power and wide power-supply margin. The
X20C04 features the JEDEC approved pinout for byte-
wide memories, compatible with industry standard RAMs,
ROMs, EPROMs, and E
2
PROMs.
The NOVRAM design allows data to be easily trans-
ferred from RAM to E
2
PROM (store) and E
2
PROM to
RAM (recall). The store operation is completed in 5ms or
less and the recall operation is completed in 5
s or less.
Xicor NOVRAMS are designed for unlimited write
operations to RAM, either from the host or recalls from
E
2
PROM, and a minimum 1,000,000 store operations to
the E
2
PROM. Data retention is specified to be greater
than 100 years.
FEATURES
High Reliability
--Endurance: 1,000,000 Nonvolatile Store
Operations
--Retention: 100 Years Minimum
Power-on Recall
--E
2
PROM Data Automatically Recalled Into
SRAM Upon Power-up
Lock Out Inadvertent Store Operations
Low Power CMOS
--Standby: 250
A
Infinite E
2
PROM Array Recall, and RAM Read
and Write Cycles
Compatible with X2004
4K
X20C04
512 x 8 Bit
PIN CONFIGURATION
A
7
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
A8
NC
NC
NC
OE
NC
CE
I/O7
I/O6
NC
NE
NC
V
CC
WE
NC
I/O
1
I/O
2
V
SS
NC
I/O
3
I/O
4
I/O
5
4
3
2
1 32 31 30
14 15 16 17 18 19 20
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
X20C04
(TOP VIEW)
3825 FHD F03
LCC
PLCC
NE
NC
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
VCC
WE
NC
A8
NC
NC
OE
NC
CE
I/O7
I/O6
I/O5
I/O4
I/O3
X20C04
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
3825 FHD F02
PLASTIC
CERDIP
X20C04
2
PIN DESCRIPTIONS
Addresses (A
0
A
8
)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (
CE
)
The Chip Enable input must be LOW to enable all read/
write operations. When
CE
is HIGH, power consumption
is reduced.
Output Enable (
OE
)
The Output Enable input controls the data output buffers
and is used to initiate read and recall operations. Output
Enable LOW disables a store operation regardless of
the state of
CE
,
WE
, or
NE
.
Data In/Data Out (I/O
0
I/O
7
)
Data is written to or read from the X20C04 through the
I/O pins. The I/O pins are placed in the high impedance
state when either
CE
or
OE
is HIGH or when
NE
is LOW.
Write Enable (
WE
)
The Write Enable input controls the writing of data to
both the static RAM and stores to the E
2
PROM.
Nonvolatile Enable (
NE
)
The Nonvolatile Enable input controls all accesses to
the E
2
PROM array (store and recall functions).
PIN NAMES
Symbol
Description
A
0
A
8
Address Inputs
I/O
0
I/O
7
Data Input/Output
WE
Write Enable
CE
Chip Enable
OE
Output Enable
NE
Nonvolatile Enable
V
CC
+5V
V
SS
Ground
NC
No Connect
3825 PGM T01
VCC SENSE
ROW
SELECT
CONTROL
LOGIC
COLUMN
SELECT
&
I/OS
EEPROM ARRAY
512 x 8
SRAM
ARRAY
CE
OE
WE
NE
A3A6
I/O0I/O7
A0A2
A7A8
RECALL
ST
ORE
3825 FHD F01
FUNCTIONAL DIAGRAM
X20C04
3
Power-Up Recall
Upon power-up (V
CC
), the X20C04 performs an auto-
matic array recall. When V
CC
minimum is reached, the
recall is initiated, regardless of the state of
CE
,
OE
,
WE
and
NE
.
Write Protection
The X20C04 has five write protect features that are
employed to protect the contents of both the nonvolatile
memory and the RAM.
V
CC
Sense--All functions are inhibited when V
CC
is
3.5V.
A RAM write is required before a Store Cycle is
initiated.
Write Inhibit--Holding either
OE
LOW,
WE
HIGH,
CE
HIGH, or
NE
HIGH during power-up and power-
down will prevent an inadvertent store operation.
Noise Protection--A combined
WE
,
NE
,
OE
and
CE
pulse of less than 20ns will not initiate a Store
Cycle.
Noise Protection--A combined
WE
,
NE
,
OE
and
CE
pulse of less than 20ns will not initiate a recall
cycle.
DEVICE OPERATION
The
CE
,
OE
,
WE
and
NE
inputs control the X20C04
operation. The X20C04 byte-wide NOVRAM uses a
2-line control architecture to eliminate bus contention in
a system environment. The I/O bus will be in a high
impedance state when either
OE
or
CE
is HIGH, or
when
NE
is LOW.
RAM Operations
RAM read and write operations are performed as they
would be with any static RAM. A read operation requires
CE
and
OE
to be LOW with
WE
and
NE
HIGH. A write
operation requires
CE
and
WE
to be LOW with
NE
HIGH. There is no limit to the number of read or write
operations performed to the RAM portion of the X20C04.
Nonvolatile Operations
With
NE
LOW, recall operation is performed in the same
manner as RAM read operation. A recall operation
causes the entire contents of the E
2
PROM to be written
into the RAM array. The time required for the operation
to complete is 5
s or less. A store operation causes the
entire contents of the RAM array to be stored in the
nonvolatile E
2
PROM. The time for the operation to
complete is 5ms or less.
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don't Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
X20C04
4
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias .................. 65
C to +135
C
Storage Temperature ....................... 65
C to +150
C
Voltage on any Pin with
Respect to V
SS .......................................
1V to +7V
D.C. Output Current ........................................... 10mA
Lead Temperature (Soldering, 10 seconds) ..... 300
C
*COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
l
CC1
V
CC
Current (Active)
100
mA
NE
=
WE
= V
IH
,
CE
=
OE
= V
IL
Address Inputs = 0.4V/2.4V levels
@ f = 5MHz. All I/Os = Open
I
CC2
V
CC
Current During Store
10
mA
All Inputs = V
IH
All I/Os = Open
I
SB1
V
CC
Standby Current
10
mA
CE
= V
IH
(TTL Input)
All Other Inputs = V
IH
, All I/Os = Open
I
SB2
V
CC
Standby Current
250
A
All Inputs = V
CC
0.3V
(CMOS Input)
All I/Os = Open
I
LI
Input Leakage Current
10
A
V
IN
= V
SS
to V
CC
I
LO
Output Leakage Current
10
A
V
OUT
= V
SS
to V
CC
,
CE
= V
IH
V
IL
(1)
Input LOW Voltage
1
0.8
V
V
IH
(1)
Input HIGH Voltage
2
V
CC
+ 0.5
V
V
OL
Output LOW Voltage
0.4
V
I
OL
= 2.1mA
V
OH
Output HIGH Voltage
2.4
V
I
OH
= 400
A
3825 PGM T04.3
POWER-UP TIMING
Symbol
Parameter
Max.
Units
t
PUR
(2)
Power-Up to RAM Operation
100
s
t
PUW
(2)
Power-Up to Nonvolatile Operation
5
ms
3825 PGM T05
Notes: (1) V
IL
min. and V
IH
max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
CAPACITANCE T
A
= +25
C, F = 1MHz, V
CC
= 5V.
Symbol
Test
Max.
Units
Conditions
C
I/O
(2)
Input/Output Capacitance
10
pF
V
I/O
= 0V
C
IN
(2)
Input Capacitance
6
pF
V
IN
= 0V
3825 PGM T06.1
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Commercial
0
C
+70
C
Industrial
40
C
+85
C
Military
55
C
+125
C
3825 PGM T02.1
Supply Voltage
Limits
X20C04
5V
10%
3825 PGM T03
X20C04
5
5V
1.92K
1.37K
OUTPUT
100pF
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Endurance
100,000
Data Changes Per Bit
Store Cycles
1,000,000
Store Cycles
Data Retention
100
Years
3825 PGM T07.1
EQUIVALENT A.C. LOAD CIRCUIT
A.C. CONDITIONS OF TEST
Input Pulse Levels
0V to 3V
Input Rise and
Fall Times
10ns
Input and Output
Timing Levels
1.5V
3825 PGM T08.2
3825 FHD F04.1
MODE SELECTION
CE
WE
NE
OE
Mode
I/O
Power
H
X
X
X
Not Selected
Output High Z
Standby
L
H
H
L
Read RAM
Output Data
Active
L
L
H
H
Write "1" RAM
Input Data High
Active
L
L
H
H
Write "0" RAM
Input Data Low
Active
L
H
L
L
Array Recall
Output High Z
Active
L
L
L
H
Nonvolatile Storing
Output High Z
Active
L
H
H
H
Output Disabled
Output High Z
Active
L
L
L
L
Not Allowed
Output High Z
Active
L
H
L
H
No Operation
Output High Z
Active
3825 PGM T09.1
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