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Datasheet: VIAVT82C694X (VIA Tech.)

Apollo Pro133a

 

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VT82C694X
Revision 1.0 September 8, 1999
-1-
Features
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VIA VT82C694X
A
POLLO
P
RO
133A
66 / 100 /133 MHz
Single-Chip Slot-1 / Socket-370 North Bridge
for Desktop and Mobile PC Systems
with AGP 4x and PCI
plus Advanced ECC Memory Controller
supporting PC100 / PC133 SDRAM,
Virtual Channel Memory (VCM), and ESDRAM
·
AGP / PCI / ISA Mobile and Deep Green PC Ready
-
GTL+ compliant host bus supports write-combine cycles
-
Supports separately powered 3.3V (5V tolerant) interface to system memory, AGP, and PCI bus
-
Modular power management and clock control for mobile system applications
-
Combine with VIA VT82C596B south bridge chip for state-of-the-art system power management
·
High Integration
-
Single chip implementation for 64-bit Slot-1/Socket-370 CPU, 64-bit system memory, 32-bit PCI and 32-bit AGP
interfaces
-
Apollo Pro133A Chipset: VT82C694X system controller and VT82C596B PCI to ISA bridge
-
Chipset includes UltraDMA-33/66 EIDE, USB, and Keyboard / PS2-Mouse Interfaces plus RTC / CMOS on chip
·
High Performance CPU Interface
-
Supports Slot-1 and Socket-370 (Intel Pentium II
TM
and Celeron
TM
) processors
-
66 / 100 /133 MHz CPU Front Side Bus (FSB)
-
Built-in PLL (Phase Lock Loop) circuitry for optimal skew control within and between clocking regions
-
Five outstanding transactions (four In-Order Queue (IOQ) plus one input latch)
-
Supports WC (Write Combining) cycles
-
Dynamic deferred transaction support
-
Sleep mode support
-
System management interrupt, memory remap and STPCLK mechanism
VT82C694X
Revision 1.0 September 8, 1999
-2-
Features
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·
Full Featured Accelerated Graphics Port (AGP) Controller
-
Synchronous and pseudo-synchronous with the host CPU bus with optimal skew control
PCI
AGP
CPU
Mode
33 MHz
66 MHz
133 MHz
4x synchronous
33 MHz
66 MHz
100 MHz
3x synchronous
33 MHz
66 MHz
66 MHz
2x synchronous
-
AGP v2.0 compliant
-
Supports SideBand Addressing (SBA) mode (non-multiplexed address / data)
-
Supports 266 MHz 4x mode for AD and SBA signaling
-
Pipelined split-transaction long-burst transfers up to 1GB/sec
-
Eight level read request queue
-
Four level posted-write request queue
-
Thirty-two level (quadwords) read data FIFO (256 bytes)
-
Sixteen level (quadwords) write data FIFO (128 bytes)
-
Intelligent request reordering for maximum AGP bus utilization
-
Supports Flush/Fence commands
-
Graphics Address Relocation Table (GART)
-
One level TLB structure
-
Sixteen entry fully associative page table
-
LRU replacement scheme
-
Independent GART lookup control for host / AGP / PCI master accesses
-
Windows 95 OSR-2 VXD and integrated Windows 98 / NT5 miniport driver support
·
Concurrent PCI Bus Controller
-
PCI buses are synchronous / pseudo-synchronous to host CPU bus
-
33 MHz operation on the primary PCI bus
-
66 MHz PCI operation on the AGP bus
-
PCI-to-PCI bridge configuration on the 66MHz PCI bus
-
Supports up to five PCI masters
-
Peer concurrency
-
Concurrent multiple PCI master transactions; i.e., allow PCI masters from both PCI buses active at the same time
-
Zero wait state PCI master and slave burst transfer rate
-
PCI to system memory data streaming up to 132Mbyte/sec
-
PCI master snoop ahead and snoop filtering
-
Two lines of CPU to PCI posted write buffers
-
Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilities
-
Enhanced PCI command optimization (MRL, MRM, MWI, etc.)
-
Forty-eight levels (double-words) of post write buffers from PCI masters to DRAM
-
Sixteen levels (double-words) of prefetch buffers from DRAM for access by PCI masters
-
Delay transaction from PCI master accessing DRAM
-
Read caching for PCI master reading DRAM
-
Transaction timer for fair arbitration between PCI masters (granularity of two PCI clocks)
-
Symmetric arbitration between Host/PCI bus for optimized system performance
-
Complete steerable PCI interrupts
-
PCI-2.1 compliant, 32 bit 3.3V PCI interface with 5V tolerant inputs
VT82C694X
Revision 1.0 September 8, 1999
-3-
Features
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·
Advanced High-Performance DRAM Controller
-
DRAM interface synchronous with host CPU (66/100/133 MHz) or AGP (66MHz) for most flexible configuration
-
DRAM interface may be faster than CPU by 33 MHz to allow use of PC100 memory modules with 66MHz Celeron
or use of PC133 with 100MHz Pentium II or Pentium III
-
DRAM interface may be slower than CPU by 33 MHz to allow use of older memory modules with newer CPUs (e.g.,
PC66 memory modules with 100 MHz Pentium II or Pentium III)
-
Concurrent CPU, AGP, and PCI access
-
Supports FP, EDO, SDRAM, ESDRAM, and VCM SDRAM memory types
-
Different DRAM types may be used in mixed combinations
-
Different DRAM timing for each bank
-
Dynamic Clock Enable (CKE) control for SDRAM power reduction in high speed systems
-
Mixed 1M / 2M / 4M / 8M / 16M / 32MxN DRAMs
-
Pinouts support 8 banks up to 2 GB DRAMs (256Mb DRAM technology) at 100 MHz
(PC133 specifications, however, recommend a limit of 3 DIMMs or 6 banks at 133 MHz for 1.5 GB max memory)
-
Flexible row and column addresses
-
64-bit data width only
-
3.3V DRAM interface with 5V-tolerant inputs
-
Programmable I/O drive capability for MA, command, and MD signals
-
Dual copies of MA signals for improved drive
-
Optional bank-by-bank ECC (single-bit error correction and multi-bit error detection)
or EC (error checking only) for DRAM integrity
-
Two-bank interleaving for 16Mbit SDRAM support
-
Two-bank and four bank interleaving for 64Mbit SDRAM support
-
Supports maximum 8-bank interleave (i.e., 8 pages open simultaneously); banks are allocated based on LRU
-
Independent SDRAM control for each bank
-
Seamless DRAM command scheduling for maximum DRAM bus utilization
(e.g., precharge other banks while accessing the current bank)
-
Four cache lines (16 quadwords) of CPU to DRAM write buffers
-
Four cache lines of CPU to DRAM read prefetch buffers
-
Read around write capability for non-stalled CPU read
-
Speculative DRAM read before snoop result
-
Burst read and write operation
-
x-2-2-2-2-2-2-2 back-to-back accesses for EDO DRAM from CPU or from DRAM controller
-
x-1-1-1-1-1-1-1 back-to-back accesses for SDRAM
-
BIOS shadow at 16KB increment
-
Decoupled and burst DRAM refresh with staggered RAS timing
-
CAS before RAS or self refresh
·
Advanced System Power Management Support
-
Dynamic power down of SDRAM (CKE)
-
Independent clock stop controls for CPU / SDRAM, AGP, and PCI bus
-
PCI and AGP bus clock run and clock generator control
-
VTT suspend power plane preserves memory data
-
Suspend-to-DRAM and Self-Refresh operation
-
EDO self-refresh and SDRAM self-refresh power down
-
8 bytes of BIOS scratch registers
-
Low-leakage I/O pads
·
Built-in NAND-tree pin scan test capability
·
3.3V, 0.35um, high speed / low power CMOS process
·
35 x 35 mm, 510 pin BGA Package
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