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Datasheet: D-16 (Texas Instruments)

Low-power Dissipation Adsl Line Driver

 

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Texas Instruments

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www.ti.com
FEATURES
DESCRIPTION
TYPICAL ADSL CO-LINE DRIVER CIRCUIT
APPLICATIONS
+
-
THS6182a
+12 V
-12 V
+
-
1:1.2
-12 V
+12V
8.68
100
1 k
1 k
1.33 k
1.33 k
953
CODEC
V
IN-
CODEC
V
IN+
8.68
20-dBm
Line
Power
THS6182b
THS6182
SLLS544G SEPTEMBER 2002 REVISED NOVEMBER 2004
LOW-POWER DISSIPATION ADSL LINE DRIVER
Low-Power Dissipation Increases ADSL Line
The THS6182 is a current feedback differential line
Card Density
driver ideal for full rate ADSL systems. Its extremely
low-power dissipation is ideal for ADSL systems that
Low THD of -88 dBc (100
, 1 MHz)
must achieve high densities in ADSL central office
Low MTPR Driving +20 dBm on the Line
rack applications. The unique architecture of the
-76 dBc With High Bias Setting
THS6182 allows the quiescent current to be much
lower than existing line drivers while still achieving
-74 dBc With Low Bias Setting
high linearity without the need for excess open loop
Wide Output Swing of 44 V
PP
Differential Into
gain. Fixed multiple bias settings of the amplifiers
a 200-
Differential Load (V
CC
=
12 V)
allow for enhanced power savings for line lengths
High Output Current of 600 mA (Typ)
where the full performance of the amplifier is not
required. To allow for even more flexibility and power
Wide Supply Voltage Range of
5 V to
15 V
savings, an I
ADJ
pin is available to further lower the
Pin Compatible with EL1503C and EL1508C
bias currents while maintaining stable operation with
Multiple Package Options
as little as 1.8 mA per channel. The wide output
swing of 44 Vpp differentially with
12-V power
Multiple Power Control Modes
supplies allows for more dynamic headroom, keeping
11 mA/ch Full Bias Mode
distortion at a minimum. With a low 3.2 nV/
Hz
7.5 mA/ch Mid Bias Mode
voltage noise coupled with a low 10 pA/
Hz inverting
4 mA/ch Low Bias Mode
current noise, the THS6182 increases the sensitivity
of the receive signals, allowing for better margins and
0.25 mA/ch Shutdown Mode
reach.
I
ADJ
Pin for User Controlled Bias Current
Stable Operation Down to 1.8 mA/ch
USING ACTIVE IMPEDANCE
Low Noise for Increased Receiver Sensitivity
3.2 nV/
Hz Voltage Noise
1.5 pA/
Hz Noninverting Current Noise
10 pA/
Hz Inverting Current Noise
Ideal for Full Rate ADSL Applications
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 20022004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
www.ti.com
PACKAGE DISSIPATION RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
THS6182
SLLS544G SEPTEMBER 2002 REVISED NOVEMBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE CODE
SYMBOL
ORDER NUMBER
TRANSPORT MEDIA
Tape and reel
THS6182RHFR
(3000 devices)
Leadless 24-pin
THS6182RHF
RHF-24
6182
4, mm x 5, mm PowerPADTM
Tape and reel
THS6182RHFT
(250 devices)
THS6182D
Tube (40 devices)
THS6182D
SOIC-16
D-16
THS6182
Tape and reel
THS6832DR
(2500 devices)
THS6182DW
Tube (25 devices)
THS6182DW
SOIC-20
DW-20
THS6182
Tape and reel
THS6182DWR
(2000 devices)
THS6182DWP
Tube (25 devices)
THS6182DWP
SOIC-20 PowerPAD
DWP-20
THS6182
Tape and reel
THS6182DWPR
(2000 devices)
PowerPAD SOLDERED
(2)
PowerPAD NOT SOLDERED
(3)
PACKAGE
JC
JA
JC
RHF-24
(2)
32
C/W
74
C/W
1.7
C/W
D-16
--
62.9
C/W
25.7
C/W
DW-20
--
45.4
C/W
16.4
C/W
DWP-20
(2)
21.5
C/W
43.9
C/W
0.37
C/W
(1)
JA
values shown are typical for standard test PCBs only.
(2)
For high-power dissipation applications, use of the PowerPAD package with the PowerPad on the underside of the chip. This acts as a
heatsink and must be connected to a thermally dissipating plane for proper dissipation. Failure to do so may result in exceeding the
maximum junction temperature which could permanently damage and/or reduce the lifetime the device. See TI technical brief SLMA002
for more information about utilizing the PowerPAD thermally enhanced package.
(3)
Use of packages without the PowerPAD or not soldering the PowerPAD to the PCB, should be limited to low-power dissipation
applications.
MIN NOM
MAX UNIT
Dual supply
5
12
15
V
CC+
to V
CC-
Supply voltage
V
Single supply
10
24
30
2
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ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
THS6182
SLLS544G SEPTEMBER 2002 REVISED NOVEMBER 2004
over operating free-air temperature range unless otherwise noted
(1)
ELECTRICAL
THS6132
V
CC
Supply voltage
16.5 V
V
I
Input voltage
V
CC
I
O
Output current
1000 mA
V
IO
Differential input voltage
2 V
THERMAL
Maximum junction temperature, any condition
150
C
T
J
Maximum junction temperature, continuous operation, long term reliability
(2)
125
C
T
Sgt
Storage temperature
65
C to 150
C
Lead temperature, 1,6 mm (1/16-inch) from case for 10 seconds
300
C
ESD
HBM
500 V
ESD ratings
CDM
1500 V
MM
200 V
(1)
The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute-maximum-rated conditions for extended periods may degrade device reliability. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those ispecified is not implied.
(2)
The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
over recommended operating free-air temperature range, T
A
= 25
C, V
CC
=
12 V, R
F
= 2 k
,
Gain = +5, I
ADJ
= Bias1 = Bias2 = 0 V, R
L
= 50
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
NOISE/DISTORTION PERFORMANCE
Gain =+9.5, 163 kHz to 1.1 MHz DMT,
MTPR
Multitone power ratio
-76
dBc
+20 dBm Line Power, See Figure 1 for circuit
Gain =+5, 25 kHz to 138 kHz with MTPR signal applied,
Receive band spill-over
-95
dBc
See Figure 1 for circuit
Differential load = 200
-88
2
nd
harmonic
dBc
Differential load = 50
-70
Harmonic distortion, V
O(PP)
= 2 V
HD
f = 1 MHz
Differential load = 200
-107
3
rd
harmonic
dBc
Differential load = 50
-84
V
n
Input voltage noise
V
CC
=
5 V,
12 V,
15 V, f = 100 kHz
3.2
nV/
Hz
+Input
1.5
I
n
Input current noise
V
CC
=
5 V,
12 V,
15 V, f = 100 kHz
pA/
Hz
-Input
10
R
L
= 100
-65
dBc
f = 1 MHz, V
O(PP)
= 2 V,
Crosstalk
V
CC
=
5 V,
12 V,
15 V
R
L
= 25
-60
dBc
3
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THS6182
SLLS544G SEPTEMBER 2002 REVISED NOVEMBER 2004
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT CHARACTERISTICS
R
L
= 100
3.9
4.1
V
CC
=
5 V
V
R
L
= 25
3.7
3.9
R
L
= 100
10.7
11.0
V
O
Single-ended output voltage swing
V
CC
=
12 V
V
R
L
= 25
10
10.6
R
L
= 100
13.5
13.9
V
CC
=
15 V
V
R
L
= 25
12.7
13.4
R
L
= 5
V
CC
=
5 V
350
400
I
O
Output current
(1)
V
CC
=
12 V
450
600
mA
R
L
= 10
V
CC
=
15 V
450
600
I
(SC)
Short-circuit current
(1)
R
L
= 1
V
CC
=
12 V
1000
mA
Output resistance
Open-loop
6
Output resistance--terminate mode
f = 1 MHz,
Gain = +10
0.05
Output resistance--shutdown mode
f = 1 MHz,
Open-loop
8.5
k
POWER SUPPLY
Dual supply
4
12
16.5
V
CC
Operating range
V
Single supply
8
24
33
T
A
= 25
C
9.7
10.7
V
CC
=
5 V
mA
T
A
= full range
11.7
Quiescent current (each driver)
(2)
T
A
= 25
C
11
12
Full-bias mode (Bias-1 = 0,
V
CC
=
12 V
mA
Bias-2 = 0)
T
A
= full range
12.5
(Trimmed with V
CC
=
12 V at 25
C)
I
CC
T
A
= 25
C
11.5
12.5
V
CC
=
15 V
mA
T
A
= full range
13
Mid; Bias-1 - 1, Bias-2 = 0
7.5
8.5
Quiescent current (each driver)
Low; Bias-1 = 0, Bias-2 = 1
4
5
mA
Variable bias modes, V
CC
=
12 V
Shutdown; Bias-1 = 1, Bias-2 = 1
0.25
0.9
T
A
= 25
C
-50
-56
V
CC
=
5 V,
V
CC
=
0.5 V
T
A
= full range
-47
PSRR
Power supply rejection ratio
dB
T
A
= 25
C
-56
-60
V
CC
=
12 V,
15 V,
V
CC
=
1 V
T
A
= full range
-53
DYNAMIC PERFORMANCE
Gain = +1, RF = 1.2 k
100
Gain = +2, RF = 1 k
80
R
L
= 100
MHz
Gain = +5, RF = 1 k
35
Gain = +10, RF = 1 k
20
Single-ended small-signal bandwidth
BW
(-3 dB), V
O
= 0.1 Vrms
Gain = +1, RF = 1.5 k
65
Gain = +2, RF = 1 k
60
R
L
= 25
MHz
Gain = +5, RF = 1 k
40
Gain = +10, RF = 1 k
22
SR
Single-ended slew rate
(3)
V
O
= 10 Vpp,
Gain = +5
450
V/s
(1)
A heatsink is required to keep the junction temperature below absolute maximum rating when an output is heavily loaded or shorted.
See Absolute Maximum Ratings section for more information.
(2)
Approximately 0.5 mA (total) flows from V
CC+
to GND for internal logic control bias.
(3)
Slew rate is defined from the 25% to the 75% output levels.
4
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THS6182
SLLS544G SEPTEMBER 2002 REVISED NOVEMBER 2004
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC PERFORMANCE
T
A
= 25
C
1
20
Input offset voltage
T
A
= full range
25
mV
V
OS
V
CC
=
5 V,
12 V,
15 V
T
A
= 25
C
0.5
10
Differential offset voltage
T
A
= full range
15
Offset drift
T
A
= full range
50
V/
C
T
A
= 25
C
8
15
-Input bias current
T
A
= full range
20
I
IB
V
CC
=
5 V,
12 V,
15 V
A
T
A
= 25
C
8
15
+Input bias current
T
A
= full range
20
Z
OL
Open loop transimpedance
R
L
= 1 k
, V
CC
=
12 V,
15 V
900
k
INPUT CHARACTERISTICS
T
A
= 25
C
2.7
3.0
V
CC
=
5 V
V
T
A
= full range
2.6
T
A
= 25
C
9.5
9.8
V
ICR
Input common-mode voltage range
V
CC
=
12 V
V
T
A
= full range
9.3
T
A
= 25
C
12.4
12.7
V
CC
=
15 V
V
T
A
= full range
12.1
T
A
= 25
C
48
54
CMRR
Common-mode rejection ratio
V
CC
=
5 V,
12 V,
15 V
dB
T
A
= full range
44
+Input
800
k
R
I
Input resistance
-Input
30
C
i
Input capacitance
1.7
pF
LOGIC CONTROL CHARACTERISTICS
V
IH
Bias pin voltage for logic 1
2.0
Relative to GND pin voltage
V
V
IL
Bias pin voltage for logic 0
0.8
I
IH
Bias pin current for logic 1
V
IH
= 3.3 V, GND = 0 V
4
30
A
I
IL
Bias pin current for logic 0
V
IL
= 0.5 V, GND = 0 V
1
10
A
Transition time, logic 0 to logic 1
(4)
1
s
Transition time, logic 1 to logic 0
(4)
1
s
(4)
Transition time is defined as the time from when the logic signal is applied to the time when the supply current has reached half its final
value.
LOGIC TABLE
(1) (2)
BIAS-1
BIAS-2
FUNCTION
DESCRIPTION
0
0
Full bias mode
Amplifiers ON with lowest distortion possible (default state)
1
0
Mid bias mode
Amplifiers ON with power savings with a reduction in distortion performance
0
1
Low bias mode
Amplifiers ON with enhanced power savings and a reduction of distortion performance
1
1
Shutdown mode
Amplifiers OFF and output has high impedance
(1)
The default state for all logic pins is a logic zero (0).
(2)
The GND pin useable range is from V
CC-
to (V
CC+
- 4 V).
5
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