2014 2.1 8/2/00
-- Integrated memory write lockout
-- Standby current less than 25µA
Standard 100KHz and Fast 400KHz
-- Data retention: 100 years
bits of serial E
tures the I
100,000 erase/write cycles and unlimited read cycles. It
provides 100 years of secure data retention, with or without
power applied, after the execution of 100,000 erase/write
and low power consumption. This device provides
microcontroller RESET control and can be manually
resettable. This device also uses a cost effective, space-
saving, 8-pin SOIC or PDIP plastic package. Typical
applications include alarm devices, electronic locks,
meters, keys, pagers and cellular phones.
microcontroller and it's associated circuitry ensuring cor-
rect system operation during power-up/down conditions
and brownout situations. The output is open drain, allow-
ing control of the reset function by multiple devices.
state until V
is valid whenever V
active state can also manually reset the device. Because
the I/O needs to be an open drain, the internal timer can
only be triggered by the leading edge of the input. The
resulting reset output will either be t
provide an affective debounce or reset signal extender
two lines are a serial data line (SDA), and a serial clock line
(SCL). The SDA line must be connected to a positive
supply by a pull-up resistor, located somewhere on the
bus (See Figure 1). Data transfer between devices may
be initiated with a START condition only when SCL and
SDA are HIGH (bus is not busy).
into and out of the device. In the WRITE mode data must
remain stable while SCL is HIGH. In the READ mode data
is clocked out on the falling edge of SCL.
used to transfer data into and out of the device. Data may
change only when SCL is LOW, except START and STOP
conditions. It is an open-drain output and may be wire-
ORed with any number of open-drain or open-collector
It is driven low whenever V
perform signal conditioning. The pin has an internal pull-up
and should be left unconnected if the signal is not used in
the system. However, an external pull-up resistor must be
connected when the pin is tied to a system RESET# line.
However, to ensure proper operation, they can be uncon-
nected or tied to ground. They must not be tied to V
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock
HIGH time, because changes on the data line while SCL
is HIGH will be interpreted as start or stop condition (See
When both the data and clock lines are HIGH, the bus is
said to be not busy. A HIGH-to-LOW transition on the data
line, while the clock is HIGH, is defined as the "START"
condition. A LOW-to-HIGH transition on the data line, while
the clock is HIGH, is defined as the "STOP" condition (See
bus as a "transmitter" and any device which receives data
as a "receiver." The device controlling data transmission
is called the "master" and the controlled device is called
the "slave." Since it never initiates any data transfers the
S24163 is always a "slave" device.
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device, either
the master or the slave, will release the bus after transmit-
ting eight bits. During the ninth clock cycle, the receiver
will pull the SDA line LOW to ACKnowledge that it
received the eight bits of data (See Figure 4).
recognition of a START condition and its slave address
byte. If both the device and a write operation are selected,
the S24163 will respond with an ACKnowledge after the
receipt of each subsequent 8-bit word.
then releases the SDA line, and monitors the line for an
ACKnowledge signal. If an ACKnowledge is detected,
and no STOP condition is generated by the master, the
S24163 will continue to transmit data. If an ACKnowledge is
not detected the S24163 will terminate further data transmis-
sions and await a STOP condition before returning to the
standby power mode.
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type identifier
(see figure 5). For the S24163 this is fixed as 1010[B
The next three bits of the slave address are an extension
of the array's address and are concatenated with the eight
bits of address in the word address field, providing direct
access to the 2,048 X 8 array.
The last bit of the data stream defines the operation to be
performed. When set to "1" a read operation is selected;
when set to "0" a write operation is selected.
write and page write. The byte write operation writes a
single byte during the nonvolatile write period (t
page to be written during t
After the slave address is sent (to identify the slave
device, specify high order word address and a read or
write operation), a second byte is transmitted which
contains the low 8 bit addresses of any one of the 2,048
words in the array.
with an ACKnowledge. After receiving the next byte of
data, it again responds with an ACKnowledge. The master
then terminates the transfer by generating a STOP condi-
tion, at which time the S24163 begins the internal write
inputs are disabled, and the device will not respond to any
requests from the master. Refer to Figure 6 for the
address, ACKnowledge and data transfer sequence.
The S24163 is capable of a 16-byte page write operation.
It is initiated in the same manner as the byte-write
operation, but instead of terminating the write cycle after
the first data word, the master can transmit up to 15 more
words of data. After the receipt of each word, the S24163
will respond with an ACKnowledge.
subsequent data words. After the receipt of each word, the
four low order address bits are internally incremented by
one. The high order five bits of the address byte remain
constant. Should the master transmit more than sixteen
words, prior to generating the STOP condition, the ad-
dress counter will "roll over," and the previously written
data will be overwritten. As with the byte-write operation,
all inputs are disabled during the internal write cycle.
Refer to Figure 6 for the address, ACKnowledge and data
Request to Slave
Address to Slave
Data to Slave
Data to Slave
Data to Slave