2011 2.1 8/2/00
-- Standby current less than 25µA
Standard 100KHz and Fast 400KHz
-- Data retention: 100 years
with 4,096 bits of serial E
other (RESET#) drives low whenever V
It is driven low whenever V
perform signal conditioning. The pin has an internal pull-
up and should be left unconnected if the signal is not used
in the system. However, when the pin is tied to a system
RESET# line an external pull-up resistor should be
driven high whenever V
perform signal conditioning. The RESET pin does have
an internal pull-down and should be left unconnected if
the signal is not used in the system. However, when the
pin is tied to a system reset line an external pull-down
resistor should be employed.
100,000 erase/write cycles and unlimited read cycles. It
provides 100 years of secure data retention, with or
without power applied, after the execution of 100,000
The S24042/43 provides a precision RESET controller
that ensures correct system operation during brown-out
and power-up/-down conditions. It is configured with two
open drain RESET outputs; pin 7 is an active high output
and pin 2 is an active low output.
begin driving active when V
act as a signal conditioning circuit for an externally
applied reset. The inputs are edge triggered; that is, the
RESET input will initiate a reset timeout after detecting a
low to high transition and the RESET# input will initiate a
reset timeout after detecting a high to low transition. Refer
to the applications Information section for more details on
device operation as a reset conditioning circuit.
into and out of the device. In the WRITE mode, data must
remain stable while SCL is HIGH. In the READ mode, data
is clocked out on the falling edge of SCL.
used to transfer data into and out of the device. Data may
change only when SCL is LOW, except START and STOP
conditions. It is an open-drain output and may be wire-
ORed with any number of open-drain or open-collector
floating or tied to ground. They cannot be tied high.
two lines are: a serial data line (SDA), and a serial clock
line (SCL). The SDA line must be connected to a positive
supply by a pull-up resistor, located somewhere on the
bus (See Figure 1). Data transfer between devices may
be initiated with a START condition only when SCL and
SDA are HIGH (bus is not busy).
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock
HIGH time, because changes on the data line while SCL
is HIGH will be interpreted as start or stop condition, refer
to Figure 10.
When both the data and clock lines are HIGH, the bus is
said to be not busy. A HIGH-to-LOW transition on the data
line, while the clock is HIGH, is defined as the "START"
condition. A LOW-to-HIGH transition on the data line,
while the clock is HIGH, is defined as the "STOP" condi-
tion (See Figure 2).
bus as a "transmitter" and any device which receives data
as a "receiver." The device controlling data transmission
is called the "master" and the controlled device is called
the "slave." In all cases, the S24042/43 will be a "slave"
device, since it never initiates any data transfers.
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device, either
the master or the slave, will release the bus after transmit-
ting eight bits. During the ninth clock cycle, the receiver
will pull the SDA line LOW to ACKnowledge that it re-
ceived the eight bits of data (See Figure 3).
recognition of a START condition and its slave address
byte. If both the device and a write operation are selected,
the S24042/43 will respond with an ACKnowledge after
the receipt of each subsequent 8-bit word.
data, then releases the SDA line, and monitors the line for
an ACKnowledge signal. If an ACKnowledge is detected,
and no STOP condition is generated by the master, the
S24042/43 will continue to transmit data. If an
ACKnowledge is not detected, the S24042/43 will termi-
nate further data transmissions and awaits a STOP condi-
tion before returning to the standby power mode.
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type identifier
(see figure 4). For the S24042/43 this is fixed as 1010[B].
order address bit A8.
write and page write. The byte write operation writes a
single byte during the nonvolatile write period (t
page to be written during t
Upon receipt of the slave address and word address, the
S24042/43 responds with an ACKnowledge. After receiv-
ing the next byte of data, it again responds with an
ACKnowledge. The master then terminates the transfer
by generating a STOP condition, at which time the
S24042/43 begins the internal write cycle.
43 inputs are disabled, and the device will not respond to
any requests from the master. Refer to Figure 5 for the
address, ACKnowledge and data transfer sequence.
The S24042/43 is capable of a 16-byte page write opera-
tion. It is initiated in the same manner as the byte-write
operation, but instead of terminating the write cycle after
the first data word, the master can transmit up to 15 more
bytes of data. After the receipt of each byte, the S24042/
43 will respond with an ACKnowledge.
subsequent data words. After the receipt of each word,
the low order address bits are internally incremented by
one. The high order five bits of the address byte remain
constant. Should the master transmit more than 16 bytes,
prior to generating the STOP condition, the address
counter will "roll over," and the previously written data will
be overwritten. As with the byte-write operation, all inputs
are disabled during the internal write cycle. Refer to
Figure 5 for the address, ACKnowledge and data transfer
The last bit of the data stream defines the operation to be
performed. When set to "1," a read operation is selected;
when set to "0," a write operation is selected.
Request to Slave
Address to Slave
Data to Slave
Data to Slave
Data to Slave