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Datasheet: K1S1616B1A (Samsung semiconductor)

1Mx16 bit Uni-Transistor Random Access Memory

 

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Samsung semiconductor
Revision 0.0
October 2003
K1S1616B1A
- 1 -
UtRAM
Preliminary
Document Title
1Mx16 bit Uni-Transistor Random Access Memory
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision History
Revision No.
0.0
Remark
Preliminary
History
Initial Draft
Draft Date
October 6, 2003
Revision 0.0
October 2003
K1S1616B1A
- 2 -
UtRAM
Preliminary
PRODUCT FAMILY
Product Family
Operating Temp.
Vcc Range
Speed
Power Dissipation
PKG Type
Standby
(I
SB1
, Max.)
Operating
(I
CC2
, Max.)
K1S1616B1A-I
Industrial(-40~85
C)
1.7V~2.1V
70/85ns
80
A
25mA
48-FBGA-6.00x7.00
1M x 16 bit Uni-Transistor CMOS RAM
GENERAL DESCRIPTION
The K1S1616B1A is fabricated by SAMSUNG
s advanced
CMOS technology using one transistor memory cell. The device
supports Industrial temperature range and 48 ball Chip Scale
Package for user flexibility of system design. The device also
supports dual chip selection for user interface.
FEATURES
Process Technology: CMOS
Organization: 1M x16 bit
Power Supply Voltage: 1.7V~2.1V
Three State Outputs
Compatible with Low Power SRAM
Dual Chip selection support
Package Type: 48-FBGA-6.00x7.00
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice
.
PIN DESCRIPTION
1) Reserved for future use.
Name
Function
Name
Function
CS1,CS2
Chip Select Inputs
Vcc
Power
OE
Output Enable Input
Vss
Ground
WE
Write Enable Input
UB
Upper Byte(I/O
9
~
16
)
A
0
~A
19
Address Inputs
LB
Lower Byte(I/O
1
~
8
)
I/O
1
~I/O
16
Data Inputs/Outputs
DNU
Do Not Use
1)
48-FBGA: Top View(Ball Down)
LB
OE
A0
A1
A2
CS2
I/O9
UB
A3
A4
CS1
I/O1
I/O10
I/O11
A5
A6
I/O2
I/O3
Vss
I/O12
A17
A7
I/O4
Vcc
Vcc
I/O13
DNU
A16
I/O5
Vss
I/O15
I/O14
A14
A15
I/O6
I/O7
I/O16
A19
A12
A13
WE
I/O8
A18
A8
A9
A10
A11
DNU
1
2
3
4
5
6
A
B
C
D
E
F
G
H
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Row
select
I/O
1
~I/O
8
Data
cont
Data
cont
Data
cont
I/O
9
~I/O
16
Vcc
Vss
Precharge circuit.
Memory array
I/O Circuit
Column select
WE
OE
UB
CS1
LB
Control Logic
CS2
Row
Addresses
Column Addresses
Revision 0.0
October 2003
K1S1616B1A
- 3 -
UtRAM
Preliminary
POWER UP SEQUENCE
1. Apply power.
2. Maintain stable power(Vcc min.=1.7V) for a minimum 200
s with CS1=high.or CS2=low.
Min. 200
s
TIMING WAVEFORM OF POWER UP(1)
(CS
1
controlled)
TIMING WAVEFORM OF POWER UP(2)
(CS
2
controlled)
POWER UP(2)
1. After V
CC
reaches V
CC
(Min.), wait 200
s with CS
2
low. Then the device gets into the normal operation.

V
CC
CS
1
CS
2
V
CC(Min)
POWER UP(1)
1. After V
CC
reaches V
CC
(Min.), wait 200
s with CS
1
high. Then the device gest into the normal operation.
Min. 200
s
V
CC
CS
1
CS
2
V
CC(Min)

Normal Operation
Power Up Mode
Normal Operation
Power Up Mode
Revision 0.0
October 2003
K1S1616B1A
- 4 -
UtRAM
Preliminary
ABSOLUTE MAXIMUM RATINGS
1)
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reli-
ability.
Item
Symbol
Ratings
Unit
Voltage on any pin relative to Vss
V
IN
, V
OUT
-0.2 to V
CC
+0.3V
V
Voltage on Vcc supply relative to Vss
V
CC
-0.2 to 2.5V
V
Power Dissipation
P
D
1.0
W
Storage temperature
T
STG
-65 to 150
C
Operating Temperature
T
A
-40 to 85
C
FUNCTIONAL DESCRIPTION
1. X means don
t care.(Must be low or high state)
CS1
CS2
OE
WE
LB
UB
I/O
1~8
I/O
9~16
Mode
Power
H
X
1)
X
1)
X
1)
X
1)
X
1)
High-Z
High-Z
Deselected
Standby
X
1)
L
X
1)
X
1)
X
1)
X
1)
High-Z
High-Z
Deselected
Standby
X
1)
X
1)
X
1)
X
1)
H
H
High-Z
High-Z
Deselected
Standby
L
H
H
H
L
X
1)
High-Z
High-Z
Output Disabled
Active
L
H
H
H
X
1)
L
High-Z
High-Z
Output Disabled
Active
L
H
L
H
L
H
Dout
High-Z
Lower Byte Read
Active
L
H
L
H
H
L
High-Z
Dout
Upper Byte Read
Active
L
H
L
H
L
L
Dout
Dout
Word Read
Active
L
H
X
1)
L
L
H
Din
High-Z
Lower Byte Write
Active
L
H
X
1)
L
H
L
High-Z
Din
Upper Byte Write
Active
L
H
X
1)
L
L
L
Din
Din
Word Write
Active
Revision 0.0
October 2003
K1S1616B1A
- 5 -
UtRAM
Preliminary
RECOMMENDED DC OPERATING CONDITIONS
1)
1. T
A
=-40 to 85
C, otherwise specified.
2. Overshoot: Vcc+1.0V in case of pulse width
20ns.
3. Undershoot: -1.0V in case of pulse width
20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
Item
Symbol
Min
Typ
Max
Unit
Supply voltage
Vcc
1.7
1.8/2.0
2.1
V
Ground
Vss
0
0
0
V
Input high voltage
V
IH
1.4
-
V
CC
+0.3
2)
V
Input low voltage
V
IL
-0.2
3)
-
0.4
V
CAPACITANCE
1)
(f=1MHz, T
A
=25
C)
1. Capacitance is sampled, not 100% tested.
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C
IN
V
IN
=0V
-
8
pF
Input/Output capacitance
C
IO
V
IO
=0V
-
10
pF
DC AND OPERATING CHARACTERISTICS
Item
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
I
LI
V
IN
=Vss to Vcc
-1
-
1
A
Output leakage current
I
LO
CS1=V
IH
or CS2=V
IL
or OE=V
IH
or WE=V
IL
or LB=UB=V
IH
,
V
IO
=Vss to Vcc
-1
-
1
A
Average operating current
I
CC1
Cycle time=1
s, 100% duty, I
IO
=0mA, CS1
0.2V, LB
0.2V
or/and UB
0.2V, CS2
V
CC
-
0.2V, V
IN
0.2V or V
IN
V
CC
-
0.2V
-
-
5
mA
I
CC2
Cycle time=Min, I
IO
=0mA
,
100% duty,
CS1=V
IL,
CS2
=
V
IH
LB=V
IL
or/and UB=V
IL
, V
IN
=V
IH
or V
IL
-
-
25
mA
Output low voltage
V
OL
I
OL
= 0.1mA
-
-
0.2
V
Output high voltage
V
OH
I
OH
= -0.1mA
1.4
-
-
V
Standby Current(CMOS)
I
SB1
Other inputs=0~Vcc
1) CS1
V
CC
-0.2V
,
CS2
V
CC
-
0.2V(CS1 controlled) or
2) 0V
CS2
0.2V(CS2 controlled)
-
-
80
A
PRODUCT LIST
1. Lead Free Product
Industrial Temperature Products(-40~85
C)
Part Name
Function
K1S1616B1A-FI70
K1S1616B1A-FI85
K1S1616B1A-BI70
1)
K1S1616B1A-BI85
1)
48-FBGA-6.00x7.00, 70ns
48-FBGA-6.00x7.00, 85ns
48-FBGA-6.00x7.00, 70ns
48-FBGA-6.00x7.00, 85ns
Revision 0.0
October 2003
K1S1616B1A
- 6 -
UtRAM
Preliminary
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level: 0.2 to Vcc-0.2V
Input rising and falling time: 5ns
Input and output reference voltage: 0.5 x V
CC
Output load (See right): C
L
=50pF
C
L
1. Including scope and jig capacitance
Dout
AC CHARACTERISTICS
(Vcc=1.7~2.1V, T
A
=-40 to 85
C)
1. t
WP
(min)=70ns for continuous write operation over 50 times.
Parameter List
Symbol
Speed Bins
Units
70ns
85ns
Min
Max
Min
Max
Read
Read Cycle Time
t
RC
70
-
85
-
ns
Address Access Time
t
AA
-
70
-
85
ns
Chip Select to Output
t
CO
-
70
-
85
ns
Output Enable to Valid Output
t
OE
-
35
-
40
ns
UB, LB Access Time
t
BA
-
70
-
85
ns
Chip Select to Low-Z Output
t
LZ
10
-
10
-
ns
UB, LB Enable to Low-Z Output
t
BLZ
10
-
10
-
ns
Output Enable to Low-Z Output
t
OLZ
5
-
5
-
ns
Chip Disable to High-Z Output
t
HZ
0
25
0
25
ns
UB, LB Disable to High-Z Output
t
BHZ
0
25
0
25
ns
Output Disable to High-Z Output
t
OHZ
0
25
0
25
ns
Output Hold from Address Change
t
OH
5
-
5
-
ns
Write
Write Cycle Time
t
WC
70
-
85
-
ns
Chip Select to End of Write
t
CW
60
-
70
-
ns
Address Set-up Time
t
AS
0
-
0
-
ns
Address Valid to End of Write
t
AW
60
-
70
-
ns
UB, LB Valid to End of Write
t
BW
60
-
70
-
ns
Write Pulse Width
t
WP
55
1)
-
60
1)
-
ns
Write Recovery Time
t
WR
0
-
0
-
ns
Write to Output High-Z
t
WHZ
0
25
0
25
ns
Data to Write Time Overlap
t
DW
30
-
35
-
ns
Data Hold from Write Time
t
DH
0
-
0
-
ns
End Write to Output Low-Z
t
OW
5
-
5
-
ns
Revision 0.0
October 2003
K1S1616B1A
- 7 -
UtRAM
Preliminary
Address
Data Out
Previous Data Valid
Data Valid
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS
1
=OE=V
IL
, CS
2
=WE=V
IH
, UB or/and LB=V
IL
)
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
Data Valid
High-Z
t
RC
CS
1
Address
UB, LB
OE
Data out
t
AA
t
RC
t
OH
t
OH
t
AA
t
CO
t
BA
t
OE
t
OLZ
t
BLZ
t
LZ
t
OHZ
t
BHZ
t
HZ
NOTES (READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
3. If invalid address signals shorter than min. t
RC
are continuously repeated for over 4us, the device needs a normal read timing(t
RC
) or
needs to sustain standby state for min. t
RC
at least once in every 4us.
CS
2
Revision 0.0
October 2003
K1S1616B1A
- 8 -
UtRAM
Preliminary
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
Address
CS
1
Data Undefined
UB, LB
WE
Data in
Data out
t
WC
t
CW(2)
t
WR(4)
t
AW
t
BW
t
WP(1)
t
AS(3)
t
DH
t
DW
t
WHZ
t
OW
High-Z
High-Z
Data Valid
CS
2
TIMING WAVEFORM OF WRITE CYCLE(2)
(CS
1
Controlled)
Address
Data Valid
UB, LB
WE
Data in
Data out
High-Z
High-Z
t
WC
t
CW(2)
t
AW
t
BW
t
WP(1)
t
DH
t
DW
t
WR(4)
t
AS(3)
CS
1
CS
2
Revision 0.0
October 2003
K1S1616B1A
- 9 -
UtRAM
Preliminary
NOTES
(WRITE CYCLE)
1. A wri
t
e occurs during the overlap(t
WP
) of low CS
1
and low WE. A write begins when CS
1
goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-
sition when CS
1
goes high and WE goes high. The
t
WP
is measured from the beginning of write to the end of write.
2.
t
CW
is measured from the CS
1
going low to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4.
t
WR
is measured from the end of write to the address change.
t
WR
is applied in case a write ends with CS
1
or WE going high.
TIMING WAVEFORM OF WRITE CYCLE(3)
(CS
2
Controlled)
Address
Data Valid
UB, LB
WE
Data in
Data out
High-Z
High-Z
t
WC
t
CW(2)
t
AW
t
BW
t
WP(1)
t
DH
t
DW
t
WR(4)
t
AS(3)
CS
1
CS
2
Address
Data Valid
UB, LB
WE
Data in
Data out
High-Z
High-Z
TIMING WAVEFORM OF WRITE CYCLE(4)
(UB, LB Controlled)
t
WC
t
CW(2)
t
BW
t
WP(1)
t
DH
t
DW
t
WR(4)
t
AW
t
AS(3)
CS
1
CS
2
Revision 0.0
October 2003
K1S1616B1A
- 10 -
UtRAM
Preliminary
C
1
/
2
PACKAGE DIMENSION
6
5
4
3
2
1
A
B
C
D
E
F
G
H
C
B/2
B
C
1
B
C
Bottom View
Top View
D
E
2
E
1
E
C
Side View
0
.
5
5
/
T
y
p
.
0
.
3
5
/
T
y
p
.
A
Y
Detail A
Min
Typ
Max
A
-
0.75
-
B
5.90
6.00
6.10
B1
-
3.75
-
C
6.90
7.00
7.10
C1
-
5.25
-
D
0.40
0.45
0.50
E
-
0.90
1.00
E1
-
0.55
-
E2
0.30
0.35
0.40
Y
-
-
0.10
B1
#A1
Notes.
1. Bump counts: 48(8 row x 6 column)
2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are
0.050 unless
specified beside figures.
4. Typ : Typical
5. Y is coplanarity: 0.10(Max)
Unit: millimeters
48 TAPE BALL GRID ARRAY(0.75mm ball pitch)
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