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Datasheet: M16C/28Group (Renesas Technology Corp.)

The M16C/28 Group of Single-chip Microcomputers is Built Using The High-performance Silicon Gate CMOSprocess UsingA M16C/60 Series Cpu Core and is Packaged inA 64-pin and 80-pin Plastic Molded Qfp.these Single-chip Microcomputers Operate Using Sophisticated Instructions FeaturingA High Level of Instructionefficiency. With 1M Bytes of Address Space, They Are Capable of Executing Instructions at High Speed. Inaddition, This Microcomputer ContainsA Multiplier and Dmac Which Combined With Fast Instruction P

 

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Renesas Technology Corp.

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Rev.0.20 2003.11.10 page 1 of 23
M16C/28 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0026-0020Z
Rev.0.20
2003.11.10
1. Overview
The M16C/28 group of single-chip microcomputers is built using the high-performance silicon gate CMOS
process using a M16C/60 Series CPU core and is packaged in a 64-pin and 80-pin plastic molded QFP.
These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruc-
tion efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. In
addition, this microcomputer contains a multiplier and DMAC which combined with fast instruction process-
ing capability, makes it suitable for control of various OA, communication, and industrial equipment which
requires high-speed arithmetic/logic operations.
1.1 Applications
Audio, cameras, office/communications/portable/industrial equipment, etc
Specifications written in this manual are believed to be accurate, but are
not guaranteed to be entirely free of error. Specifications in this manual
may be changed for functional or performance improvements. Please make
sure your manual is the latest edition.
------Table of Contents------
Rev.0.20 2003.11.10 page 2 of 23
M16C/28 Group
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
Item
Performance
Number of basic instructions
91 instructions
Shortest instruction execution time
50 ns (f(BCLK)= 20MH
Z
, V
CC
= 3.0V to 5.5V) (Normal-ver./T-ver.)
100 ns (f(BCLK)= 10MH
Z
, V
CC
= 2.7V to 5.5V) (Normal-ver.)
50 ns (f(BCLK)= 20MH
Z
, V
CC
= 4.2V to 5.5V -40 to 105
C) (V-ver.)
62.5 ns (f(BCLK)= 16MH
Z
, V
CC
= 4.2V to 5.5V -40 to 125
C) (V-ver.)
Memory
ROM
(See the product list)
capacity
RAM
(See the product list)
I/O port
71 lines
Multifunction timer
TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels
Three-phase Motor Control Timer
TimerS (Input Capture/Output Compare)
: 16bit base timer x 1 channel (Input/Output x 8 channels)
Serial I/O
2 channels (UART0, UART1)
UART, clock synchronous
1 channel (UART2)
UART, clock synchronous, I
2
C bus
1
(option
3
), or IE bus
2
(option
3
)
2 channels (SI/O3, SI/O4)
Clock synchronous
1 channel (Multi-Master I
2
C bus
1
(option
3
))
A-D converter
10 bits x 24 channels
DMAC
2 channels (trigger: 31 sources)
Watchdog timer
15 bits x 1 (with prescaler)
Interrupt
25 internal and 8 external sources, 4 software sources, 7 levels
Clock generation circuit
4 circuits
Main clock
Sub-clock
Ring oscillator(main-clock oscillation stop detect function)
PLL frequency synthesizer
Voltage detection circuit
Present (option
3
)
Power supply voltage
V
CC
=3.0V to 5.5V (f(BCLK)=20MH
Z
)
(Normal-ver.)
V
CC
=2.7V to 5.5V (f(BCLK)=10MH
Z
)
V
CC
=3.0V to 5.5V
(T-ver.)
V
CC
=4.2V to 5.5V
(V-ver.)
Flash memory Program/erase voltage
2.7V to 5.5V (Normal-ver.) 3.0V to 5.5V (T-ver.) 4.2V to 5.5V (V-ver.)
Number of program/erase
100 times ( Block A ,Block B : 10,000 times (option
3
) )
Power consumption
16mA (Vcc=5V, f(BCLK)=20MHz)
25
A (Vcc=3V, f(BCLK)=f(X
CIN
)=32KHz on RAM)
1.8
A (Vcc=3V, f(BCLK)=f(X
CIN
)=32KHz, when wait mode)
0.7
A (Vcc=3V, when stop mode)
Operating ambient temperature
-20 to 85
C / -40 to 85
C (option
3
)
(Normal-ver.)
-40 to 85
C
(T-ver.)
-40 to 105
C / -40 to 125
C
(V-ver.)
Package
80-pin plastic mold QFP
Notes:
1. I
2
C Bus is a registered trademark of PHILIPS.
2. IE Bus is a registered trademark of NEC.
3. If you desire this option, please so specify.
Table 1.2.1. Performance outline of M16C/28 group (80-pin device)
1.2 Performance Outline
Table 1.2.1 lists performance outline of M16C/28 group 80-pin device.
Table 1.2.2 lists performance outline of M16C/28 group 64-pin device.






(These circuits contain a built-in feedback
resistor and external ceramic/quartz oscillator)
Rev.0.20 2003.11.10 page 3 of 23
M16C/28 Group
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
Item
Performance
Number of basic instructions
91 instructions
Shortest instruction execution time
50 ns (f(BCLK)= 20MH
Z
, V
CC
= 3.0V to 5.5V) (Normal-ver./T-ver.)
100 ns (f(BCLK)= 10MH
Z
, V
CC
= 2.7V to 5.5V) (Normal-ver.)
50 ns (f(BCLK)= 20MH
Z
, V
CC
= 4.2V to 5.5V -40 to 105
C) (V-ver.)
62.5 ns (f(BCLK)= 16MH
Z
, V
CC
= 4.2V to 5.5V -40 to 125
C) (V-ver.)
Memory
ROM
(See the product list)
capacity
RAM
(See the product list)
I/O port
55 lines
Multifunction timer
TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels
Three-phase Motor Control Timer
TimerS (Input Capture/Output Compare)
: 16bit base timer x 1 channel (Input/Output x 8 channels )
Serial I/O
2 channels (UART0, UART1)
UART, clock synchronous
1 channel (UART2)
UART, clock synchronous, I
2
C bus
1
(option
3
), or IE bus
2
(option
3
)
1 channel (SI/O3)
Clock synchronous
1 channel (Multi-Master I
2
C bus
1
(option
3
))
A-D converter
10 bits x 13 channels
DMAC
2 channels (trigger: 30 sources)
Watchdog timer
15 bits x 1 (with prescaler)
Interrupt
24 internal and 8 external sources, 4 software sources, 7 levels
Clock generation circuit
4 circuits
Main clock
Sub-clock
Ring oscillator(main-clock oscillation stop detect function)
PLL frequency synthesizer
Voltage detection circuit
Present (option
3
)
Power supply voltage
V
CC
=3.0V to 5.5V (f(BCLK)=20MH
Z
)
(Normal-ver.)
V
CC
=2.7V to 5.5V (f(BCLK)=10MH
Z
)
V
CC
=3.0V to 5.5V
(T-ver.)
V
CC
=4.2V to 5.5V
(V-ver.)
Flash memory Program/erase voltage
2.7V to 5.5V (Normal-ver.) 3.0V to 5.5V (T-ver.) 4.2V to 5.5V (V-ver.)
Number of program/erase
100 times ( Block A ,Block B : 10,000 times (option
3
) )
Power consumption
16mA (Vcc=5V, f(BCLK)=20MHz)
25
A (Vcc=3V, f(BCLK)=f(X
CIN
)=32KHz on RAM)
1.8
A (Vcc=3V, f(BCLK)=f(X
CIN
)=32KHz, when wait mode)
0.7
A (Vcc=3V, when stop mode)
Operating ambient temperature
-20 to 85
C / -40 to 85
C (option
3
)
(Normal-ver.)
-40 to 85
C
(T-ver.)
-40 to 105
C / -40 to 125
C
(V-ver.)
Package
64-pin plastic mold QFP
Notes:
1. I
2
C Bus is a registered trademark of PHILIPS.
2. IE Bus is a registered trademark of NEC.
3. If you desire this option, please so specify.
Table 1.2.2. Performance outline of M16C/28 group (64-pin device)






(These circuits contain a built-in feedback
resistor and external ceramic/quartz oscillator)
Rev.0.20 2003.11.10 page 4 of 23
M16C/28 Group
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
I/O
Ports
Internal Peripheral Functions
Timer
Timer A0 (16 bits)
Timer A1 (16 bits)
Timer A2 (16 bits)
Timer A3 (16 bits)
Timer A4 (16 bits)
Timer B0 (16 bits)
Timer B1 (16 bits)
Timer B2 (16 bits)
Watchdog Timer
A-D converter
(10bits x 24 channels)
U(S)ART/SIO (channel 0)
Serial Ports
System Clock Generator
Xin-Xout
Xcin-Xcout
Ring Oscillator
M16C/60 series 16-bit CPU Core
R0L
R0H
R1L
R1H
R2
R3
A0
A1
FR
R0L
R0H
R1L
R1H
R2
R3
A0
A1
FB
Registers
SB
PC
ISP
USP
Program Counter
Stack Pointers
INTB
Vector Table
FLG
Flag Register
Memory
Multiplier
Flash ROM
RAM
U(S)ART/SIO (channel 1)
U(S)ART/SIO/I
2
C/IEbus
(channel 2)
3-phase PWM
Port P0
8
Port P1
8
Port P2
8
Port P3
8
Port P6
8
Port P7
8
Port P8
8
Port P9
7
Port P10
8
Timer S
Input Capture (8 channels)
Output Compare (8 channels)
Flash ROM
(Data Flash)
Multi-master I
2
C BUS
SIO (channel 3)
SIO (channel 4)
DMAC (2 channels)
Low voltage detect
PLL frequency synthesizer
1.3 Block Diagram
Figure 1.3.1 is a block diagram of the M16C/28 group, 80-pin device.
Figure 1.3.1. M16C/28 Group, 80-pin Block Diagram
Rev.0.20 2003.11.10 page 5 of 23
M16C/28 Group
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
1. Overview
Figure 1.3.2 is a block diagram of the M16C/28 group, 64-pin device.
Figure 1.3.2. M16C/28 Group, 64-pin Block Diagram
I/O
Ports
Internal Peripheral Functions
Timer
Timer A0 (16 bits)
Timer A1 (16 bits)
Timer A2 (16 bits)
Timer A3 (16 bits)
Timer A4 (16 bits)
Timer B0 (16 bits)
Timer B1 (16 bits)
Timer B2 (16 bits)
Watchdog Timer
A-D converter
(10bits x 13 channels)
System Clock Generator
Xin-Xout
Xcin-Xcout
Ring Oscillator
M16C/60 series 16-bit CPU Core
R0L
R0H
R1L
R1H
R2
R3
A0
A1
FR
R0L
R0H
R1L
R1H
R2
R3
A0
A1
FB
Registers
SB
PC
ISP
USP
Program Counter
Stack Pointers
INTB
Vector Table
FLG
Flag Register
Memory
Multiplier
Flash ROM
RAM
3-phase PWM
Port P0
4
Port P1
3
Port P2
8
Port P3
4
Port P6
8
Port P7
8
Port P8
8
Port P9
4
Port P10
8
Timer S
Input Capture (8 channels)
Output Compare (8 channels)
Flash ROM
(Data Flash)
U(S)ART/SIO (channel 0)
Serial Ports
U(S)ART/SIO (channel 1)
U(S)ART/SIO/I
2
C/IEbus
(channel 2)
Multi-master I
2
C BUS
SIO (channel 3)
PLL frequency synthesizer
Low voltage detect
DMAC (2 channels)
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