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Datasheet: I74F777A (Philips Semiconductors)

Triple bidirectional latched bus transceiver 3-State open collector

 

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Philips Semiconductors
Philips
Semiconductors
74F777
Triple bidirectional latched bus
transceiver (3-State + open collector)
Product specification
IC15 Data Handbook
1992 May 19
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74F777
Triple bidirectional latched bus transceiver (3­State +
Open Collector)
2
May 19, 1992
853­1645 06772
FEATURES
·
Latching transceiver
·
High drive Open Collector output current with minimum output
swing
·
Compatible with Test Mode (TM) bus specification
·
Controlled output ramp
·
Multiple package options
·
Industrial temperature range available (­40
°
C to +85
°
C)
DESCRIPTION
The 74F777 is a triple bidirectional latched bus transceiver and is
intended to provide the electrical interface to a high performance
wired­OR bus. This bus has a loaded characteristics impedance
range of 20 to 50 ohms and is terminated on each end with a 30 to
40 ohm resistor.
The 74F777 is a triple bidirectional transceiver with Open Collector
B and 3­State A port output drivers. A latch function is provided for
the A port signals. The B port output driver is designed to sink
100mA from 2 volts to minimize crosstalk and ringing on the bus.
A separate output threshold clamp voltage (V
X
) is provided to
prevent the A port output High level from exceeding future high
density processor supply voltage levels. For 5 volt systems, V
X
is
simply tied to V
CC.
TYPE
TYPICAL
PROPAGATION DELAY
TYPICAL SUPPLY CUR-
RENT( TOTAL)
74F777
7.0ns
45mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
INDUSTRIAL RANGE
PKG DWG #
V
CC
= 5V
±
10%, T
amb
= 0
°
C to +70
°
C
V
CC
= 5V
±
10%,
T
amb
= ­40
°
C to +85
°
C
20­pin plastic DIP (300 mil)
N74F777N
I74F777N
SOT146-1
20­pin PLCC
N74F777A
I74F777A
SOT380-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
A0 ­ A2
PNP latched inputs
3.5/0.117
70
µ
A
/
70
µ
A
B0 ­ B2
Data inputs with threshold circuitry
5.0/0.167
100
µ
A/100
µ
A
OEA0 ­ OEA2
A output enable inputs (active­High)
1.0/0.033
20
µ
A/20
µ
A
OEB0 ­ OEB2
B output enable inputs (active­Low)
1.0/0.033
20
µ
A/20
µ
A
LE0 ­ LE2
Latch enable inputs (active­Low)
1.0/0.033
20
µ
A/20
µ
A
A0 ­ A2
3­State outputs
150/40
3mA/24mA
B0 ­ B2
Open Collector outputs
OC/166.7
OC/100mA
Note to input and output loading and fan out table
One (1.0) FAST unit load is defined as: 20
µ
A in the High state and 0.6mA in the Low state.
OC = Open Collector.
Philips Semiconductors
Product specification
74F777
Triple bidirectional latched bus transceiver (3­State +
Open Collector)
May 19, 1992
3
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
LE0
LE1
OEA0
A0
GND
A1
A2
V
CC
LE2
OEA1
OEA2
V
X
GND
B0
B1
B2
GND
OEB0
OEB1
OEB2
SF00432
PIN CONFIGURATION PLCC
3
2
1
20
19
18
17
16
15
14
8
7
6
5
13
12
11
10
9
4
PLCC
OEA0
A0
OEA1
A1
GND
B0
B1
B2
GND
OEA2
LE2
LE1
LE0
Vcc
Vx
A2
GND
OEB2
OEB1
OEB0
SF00433
LOGIC SYMBOL
1
2
3
4
6
8
17 16 15
12
OEA0
OEA1
OEA2
OEB0
LE0
LE1
LE2
OEB1
11
OEB2
19
V
X
B0 B1
B2
5 7 9
A0
A1
A2
13
V
CC
= Pin 20, V
X
= Pin 19,
GND = Pin 10, 14, 18
SF00434
LOGIC DIAGRAM
LE
A0
B0
OEB0
Data
Q
LE0
OEA0
17
13
1
5
4
LE
A1
B1
OEB1
Data
Q
LE1
OEA1
16
12
2
7
6
LE
A2
B2
OEB2
Data
Q
LE2
OEA2
15
11
3
9
8
V
CC
=
Pin 20, V
X
= Pin 19,
GND = Pin 10, 14, 18
SF00436
IEC/IEEE SYMBOL
EN
ID
C1
EN
13
1
5
4
12
2
7
6
11
3
9
8
17
16
15
SF00435
Philips Semiconductors
Product specification
74F777
Triple bidirectional latched bus transceiver (3­State +
Open Collector)
May 19, 1992
4
FUNCTION TABLE
INPUTS
LATCH
OUTPUTS
OPERATING MODE
An
Bn*
LEn
OEAn
OEBn
STATE
An
Bn
H
X
L
L
L
H
Z
H**
A 3-State, data from A to B
L
X
L
L
L
L
Z
L
X
X
H
L
L
Qn
Z
Qn
A 3-State, latched data to B
­
­
L
H
L
(1)
(1)
(1)
Feedback: A to B, B to A
­
H
H
H
L
H (2)
H
Z(2)
Preconditioned latch enabling
­
L
H
H
L
H (2)
L
Z(2)
data transfer from B to A
­
­
H
H
L
Qn
Qn
Qn
Latch state to A and B
H
X
L
L
H
H
Z
Z
L
X
L
L
H
L
Z
Z
B and A 3­State
X
X
H
L
H
Qn
Z
Z
­
H
L
H
H
H
H
Z
­
L
L
H
H
L
L
Z
B 3-State, data from B to A
­
H
H
H
H
Qn
H
Z
­
L
H
H
H
Qn
Qn
L
Z
Notes to function table
H = High voltage level
L
= Low voltage level
X = Don't care
­
= Input not externally driven
Z = High impedance (off) state
Q
n
= High or Low voltage level one setup time prior to the Low­to­High LE transition.
(1) = Condition will cause a feedback loop path: A to B and B to A.
(2) = The latch must be preconditioned such that B inputs may assume a High or Low level while OEB0 and OEB1 are Low and LE is High.
B
n
*
=Precaution should be taken to insure the B inputs do not float. If they do they are equal to Low state.
H**= Goes to level of pull-up voltage.
Each latch is independent. The latches may be run in any combination of modes.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
CC
Supply voltage
­0.5 to +7.0
V
V
X
Threshold control
­0.5 to +7.0
V
V
IN
Input voltage
OEBn, OEAn, LEn
­0.5 to +7.0
V
A0
­ A2, B0
­ B2
­0.5 to +5.5
V
I
IN
Input current
­30 to +5
mA
V
OUT
Voltage applied to output in High output state
­0.5 to V
CC
V
I
OUT
Current applied to output in
A0
­ A2
48
mA
Low output state
B0
­ B2
200
mA
T
amb
Operating free air
Commercial range
0 to +70
°
C
temperature range
Industrial range
­40 to +85
°
C
T
stg
Storage temperature range
­65 to +150
°
C
Philips Semiconductors
Product specification
74F777
Triple bidirectional latched bus transceiver (3­State +
Open Collector)
May 19, 1992
5
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
MIN
NOM
MAX
V
CC
Supply voltage
4.5
5.0
5.5
V
V
IH
High­level input voltage
Except B0
­ B2
2.0
V
B0
­ B2
1.6
V
V
IL
Low­level input voltage
Except B0
­ B2
0.8
V
B0
­ B2
1.43
V
I
Ik
Input clamp current
Except A0 ­ A2
­18
mA
A0 ­ A2
­40
mA
I
OH
High­level output current
Except A0
­ A2
­3
mA
I
OL
Low­level output current
A0 ­ A2
24
mA
B0
­ B2
100
mA
T
amb
Operating free­air temperature range
Commercial range
0
+70
°
C
Industrial range
­40
+85
°
C
Philips Semiconductors
Product specification
74F777
Triple bidirectional latched bus transceiver (3­State +
Open Collector)
May 19, 1992
6
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
CONDITIONS
1
MIN
TYP
2
MAX
I
OH
High­level output current
B0
­ B2
V
CC
= MAX, V
IL
= MAX, V
IH
= MIN, V
OH
= 2.1V
100
µ
A
I
OFF
Power­off output current
B0
­ B2
V
CC
= 0.0V, V
IL
= MAX, V
IH
= MIN, V
OH
= 2.1V
100
µ
A
V
CC
= MIN,
I
OH
= ­3mA, V
X
=V
CC
2.5
V
CC
V
V
OH
High-level output voltage
A0
­ A2
4
V
IL
= MAX,
V
IH
= MIN
I
OH
= ­4mA, V
X
= 3.13V
and 3.47V
2.5
V
X
V
A0
­ A2
4
V
CC
= MIN,
I
OL
= 20mA, V
X
= V
cc
0.50
V
V
OL
Low-level output voltage
B0
­ B2
V
IL
= MAX,
I
OL
= 100mA
1.15
V
V
IH
= MIN
I
OL
= 4mA
0.40
V
V
IK
Input clamp voltage
A0
­ A2
V
CC
= MIN, I
I
= I
IK
-0.5
V
Except A0
­ A2
V
CC
= MIN, I
I
= I
IK
-1.2
V
I
I
Input current at
maximum input voltage
OEBn, OEAn,
LEn
V
CC
= MAX, V
I
= 7.0V
100
µ
A
A0
­ A2,
B0
­ B2
V
CC
= MAX, V
I
= 5.5V
1
mA
I
IH
High­level input current
OEBn, OEAn,
LEn
V
CC
= MAX, V
I
= 2.7V, Bn ­ An = 0V
20
µ
A
B0
­ B2
V
CC
= MAX, V
I
= 2.1V
100
µ
A
I
IL
Low­level input current
OEBn, OEAn
,
LEn
V
CC
= MAX, V
I
= 0.5V
­20
µ
A
B0
­ B2
V
CC
= MAX, V
I
= 0.3V
­100
µ
A
I
OZH
+ I
IH
Off­state output current,
High level voltage applied
A0
­ A2
V
CC
= MAX, V
O
= 2.7V
70
µ
A
I
OZL
+ I
IL
Off­state output current,
Low level voltage applied
A0
­ A2
V
CC
= MAX, V
I
= 0.5V
­70
µ
A
I
X
High level control current
V
CC
= MAX, V
X
= V
CC
, LE = OEAn
= OEBn
= 2.7V,
A0 ­ A2 = 2.7V, B0 ­ B2 = 2.0V,
­100
100
µ
A
V
CC
= MAX, V
X
= 3.13 & 3.47V, LE = OEAn
=
2.7V, OEBn
= A0 ­ A2 = 2.7V, B0 ­ B2 = 2.0V
­10
10
µ
A
I
OS
Short circuit output
current
3
A0
­ A2
only
V
CC
= MAX, Bn = 1.8V, OEAn = 2.0V,
OEBn
= 2.7V
-60
-150
mA
I
CCH
V
CC
= MAX
40
60
mA
I
CC
Supply current (total)
I
CCL
V
CC
= MAX, V
IL
= 0.5V
55
80
mA
I
CCZ
V
CC
= MAX, V
IL
= 0.5V
45
67
mA
Notes to DC electrical characteristics
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
Unless otherwise specified, V
X
=V
CC
for all test condition.
2. All typical values are at V
CC
= 5V, T
amb
= 25
°
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
4. Due to test equipment limitations, actual test conditions are for V
IH
=1.8v and V
IL
= 1.3V.
Philips Semiconductors
Product specification
74F777
Triple bidirectional latched bus transceiver (3­State +
Open Collector)
May 19, 1992
7
AC ELECTRICAL CHARACTERISTICS
A PORT LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
T
amb
= +25
°
C
V
CC
= +5.0V
C
L
= 30pF, R
L
= 9
T
amb
= 0
°
C to +70
°
C
V
CC
= +5.0V
±
10%
C
L
= 30pF, R
L
= 9
T
amb
= ­40
°
C to
+85
°
C
V
CC
= +5.0V
±
10%
C
L
= 30pF, R
L
= 9
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
t
PLH
t
PHL
Propagation delay
Bn
to An
Waveform 1
8.5
7.5
10.5
9.5
13.0
12.0
8.0
7.5
14.5
12.5
8.0
7.5
14.5
12.5
ns
t
PZH
t
PZL
Output enable time to
High or Low
OEAn
to An
Waveform 3, 4
8.0
9.0
10.0
11.0
13.0
14.0
7.0
8.0
14.5
15.5
7.0
8.0
14.5
15.5
ns
t
PHZ
t
PLZ
Output Disable time from
High or Low
OEAn
to An
Waveform 3, 4
1.5
1.5
3.0
3.0
6.0
6.0
1.0
1.0
6.5
6.0
1.0
1.0
6.5
6.0
ns
B PORT LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
T
amb
= +25
°
C
V
CC
= +5.0V
C
D
= 30pF, R
U
= 9
T
amb
= 0
°
C to +70
°
C
V
CC
= +5.0V
±
10%
C
D
= 30pF, R
U
= 9
T
amb
= ­40
°
C to
+85
°
C
V
CC
= +5.0V
±
10%
C
D
= 30pF, R
U
= 9
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
t
PLH
t
PHL
Propagation delay
An
to Bn
Waveform 1
3.0
5.0
4.5
6.5
7.0
9.0
2.5
4.5
8.0
10.0
2.5
4.5
8.0
10.0
ns
t
PLH
t
PHL
Propagation delay
LEn
to Bn
Waveform 1
3.5
5.5
5.5
7.5
8.0
10.5
3.0
5.0
9.0
11.5
3.0
5.0
9.0
11.5
ns
t
PLH
t
PHL
Enable/disable time
OEBn
to An
Waveform 1
3.0
6.0
5.0
8.0
7.5
10.5
3.0
5.5
8.0
12.0
3.0
5.5
8.0
12.0
ns
t
TLH
t
THL
Transition time, B port
1.3V to 1.7V, 1.7V to 1.3V
Test Circuits and
Waveforms
0.5
0.5
4.0
2.0
4.5
4.5
0.5
0.5
7.0
4.5
0.5
0.5
7.0
4.5
ns
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
T
amb
= +25
°
C
V
CC
= +5.0V
C
D
= 30pF, R
U
= 9
T
amb
= 0
°
C to +70
°
C
V
CC
= +5.0V
±
10%
C
D
= 30pF, R
U
= 9
T
amb
= ­40
°
C to
+85
°
C
V
CC
= +5.0V
±
10%
C
D
= 30pF, R
U
= 9
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
t
su
(H)
t
su
(L)
Setup time
An
to LEn
Waveform 2
4.0
4.5
4.5
4.5
4.5
4.5
ns
t
h
(H)
t
h
(L)
Hold time
An
to LEn
Waveform 2
0.0
0.0
0.0
0.0
0.0
0.0
ns
t
w
(L)
LEn
pulse width, Low
Waveform 2
5.5
6.5
6.5
ns
AC WAVEFORMS
V
M
V
M
V
M
V
M
An, Bn
An, Bn, OEBn
t
PLH
t
PHL
SF00437
Waveform 1. Propagation delay, data to output and
enable/disable time OEBn to Bn
LEn
V
M
V
M
V
M
V
M
V
M
V
M
t
su
(L)
t
su
(H)
t
h
(L)
t
h
(H)
An
V
M
t
w
(L)
SF00438
Waveform 2. Data set-up and hold times and LE pulse width
Philips Semiconductors
Product specification
74F777
Triple bidirectional latched bus transceiver (3­State +
Open Collector)
May 19, 1992
8
V
M
V
M
V
M
t
PHZ
t
PZH
V
OH
-0.3V
0V
OEAn
An
SF00439
Waveform 3. 3-State output enable time to High level and
output disable time from High level
V
M
V
M
V
M
t
PLZ
t
PZL
V
OL
+0.3V
An
OEAn
SF00440
Waveform 4. 3-State output enable time to Low level and output
disable time from Low level
Notes to AC waveforms
For all waveforms, V
M
= 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUITS AND WAVEFORMS
tw
90%
VM
10%
90%
VM
10%
90%
VM
10%
90%
VM
10%
NEGATIVE
PULSE
POSITIVE
PULSE
tw
AMP (V)
low V
low V
tTHL (tf
)
INPUT PULSE REQUIREMENTS
rep. rate
t
w
t
TLH
t
THL
1MHz
500ns 2.5ns
2.5ns
Input pulse definition
VCC
family
A port
D.U.T.
PULSE
GENERATOR
RL
CL
RT
VIN
VOUT
Test circuit for 3­State outputs on A port
DEFINITIONS:
R
L
= Load resistor; see AC electrical characteristics for value.
C
L
= Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
R
U
= Pull up resistor; see AC electrical characteristics for value.
C
D
= Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
tTHL (tf
)
tTLH (tr
)
tTLH (tr
)
AMP (V)
amplitude
3.0V
1.5V
V
M
RL
7.0V
VCC
D.U.T.
PULSE
GENERATOR
CD
RT
VIN
VOUT
Test circuit for outputs on B port
RU
7.0V
1MHz
500ns
B port
2.0V
1.0V
4.0ns
4.0ns
Low V
0.0V
1.0V
SWITCH POSITION
TEST
SWITCH
closed
open
All other
t
PLZ
, t
PZL
SF00431
Philips Semiconductors
Product specification
74F777
Triple bidirectional latched bus transceiver
(3-State + open collector)
1992 May 19
9
DIP20:
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
Philips Semiconductors
Product specification
74F777
Triple bidirectional latched bus transceiver
(3-State + open collector)
1992 May 19
10
PLCC20:
plastic leaded chip carrier; 20 leads
SOT380-1
Philips Semiconductors
Product specification
74F777
Triple bidirectional latched bus transceiver
(3-State + open collector)
1992 May 19
11
NOTES
Philips Semiconductors
Product specification
74F777
Triple bidirectional latched bus transceiver
(3-State + open collector)
yyyy mmm dd
12
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088­3409
Telephone 800-234-7381
©
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code
Date of release: 10-98
Document order number:
9397-750-05178
Philips
Semiconductors
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
[1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1]
Please consult the most recently issued datasheet before initiating or completing a design.
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