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Datasheet: I74F652AD (Philips Semiconductors)

Transceivers/registers

 

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Philips Semiconductors
Philips
Semiconductors
74F651A/74F652A
Transceivers/registers
Product specification
Replaces datasheet 74F651/74F652/74F651A/74F652A of 1990 Oct 23
IC15 Data Handbook
1999 Jun 23
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
74F651A/74F652A
Transceivers/registers
74F651A Octal transceiver/register, inverting (3-State)
74F652A Octal transceiver/register, non-inverting (3-State)
2
1999 Jun 23
853­1126 21852
FEATURES
·
Combines 74F245 and two 74F374 type functions in one chip
·
High impedance base inputs for reduced loading (70
µ
A in high
and low states)
·
Independent registers for A and B buses
·
Multiplexed real-time and stored data
·
Choice of non-inverting and inverting data paths
·
3-State outputs
·
Industrial temperature range available (­40
°
C to +85
°
C) for
74F652A
DESCRIPTION
The 74F651A and 74F652A transceivers/registers consist of bus
transceiver circuits with 3­State outputs, D­type flip­flops, and
control circuitry arranged for multiplexed transmission of data
directly from the input bus or the internal registers. Data on the A or
B bus will be clocked into the registers as the appropriate clock pin
goes high. Output enable (OEAB, OEBA) and select (SAB, SBA)
pins are provided for bus management.
TYPE
TYPICAL f
max
TYPICAL SUPPLY CURRENT( TOTAL)
74F651/74F652
110MHz
140mA
74F651A/74F652A
175MHz
110mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
INDUSTRIAL RANGE
PKG DWG #
DESCRIPTION
V
CC
= 5V
±
10%,
V
CC
= 5V
±
10%,
PKG DWG #
T
amb
= 0
°
C to +70
°
C
T
amb
= ­40
°
C to +85
°
C
24­pin plastic slim DIP (300mil)
N74F651AN, N74F652AN
I74F652AN
SOT222-1
24­pin plastic SOL
N74F651AD, N74F652AD
I74F652AD
SOT137-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
A0 ­ A7, B0 ­ B7
A, B inputs
3.5/0.116
70
µ
A/70
µ
A
CPAB, CPBA
A­to­B, B­to­A clock inputs
1.0/0.033
20
µ
A/20
µ
A
SAB, SBA
A­to­B, B­to­A select inputs
1.0/0.033
20
µ
A/20
µ
A
OEAB, OEBA
A­to­B, B­to­A output enable inputs
1.0/0.033
20
µ
A/20
µ
A
A0 ­ A7, B0 ­ B7
A, B outputs for N74F651, N74F652
750/106.7
15mA/64mA
A0 ­ A7, B0 ­ B7
A, B outputs for N74F651A, N74F652A
750/80
15mA/48mA
A0 ­ A7, B0 ­ B7
A, B outputs for I74F652A
750/60
15mA/36mA
Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20
µ
A in the high state and 0.6mA in the low state.
Philips Semiconductors
Product specification
74F651A/74F652A
Transceivers/registers
1999 Jun 23
3
PIN CONFIGURATION
24
23
22
21
20
19
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
GND
A7
CPAB
CPBA
SBA
OEBA
B0
B3
B4
B5
B6
SAB
OEAB
A0
A1
A2
V
CC
A4
A5
A6
B7
B1
B2
A3
74F651A
SF00401
IEC/IEEE SYMBOL
2
1
G3
G5
G7
C6
20
7
7
5
5
6D
4D
1
1
1
1
EN1 [BA]
EN1 [AB]
4
74F651A
SF00403
21
3
23
22
1
2
5
6
7
8
9
10
11
19
18
17
16
15
14
13
LOGIC SYMBOL
CPAB
SAB
OEAB
CPBA
SBA
OEBA
B0 B1
B2
B3 B4
B5 B6
B7
1
2
3
23
22
21
A0
A1 A2
A3 A4
A5 A6
A7
4
5
6
7
8
9
10
11
20
19
18
17
16
15
14
13
V
CC
= Pin 24
GND = Pin 12
74F651A
SF00402
LOGIC DIAGRAM
A0
OEBA
B0
1D
C1
1D
C1
I of 8 channels
to 7 other channels
74F651A
21
4
20
V
CC
= Pin 24
GND = Pin 12
SF00404
3
23
22
1
2
OEAB
CPBA
SBA
CPAB
SAB
Philips Semiconductors
Product specification
74F651A/74F652A
Transceivers/registers
1999 Jun 23
4
PIN CONFIGURATION
24
23
22
21
20
19
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
GND
A7
CPAB
CPBA
SBA
OEBA
B0
B3
B4
B5
B6
SAB
OEAB
A0
A1
A2
V
CC
A4
A5
A6
B7
B1
B2
A3
74F652A
SF00405
IEC/IEEE SYMBOL
74F652A
SF00407
2
1
G3
G5
G7
C6
20
7
7
6D
4D
1
1
1
1
EN1 [BA]
EN1 [AB]
4
21
3
23
22
1
2
5
6
7
8
9
10
11
19
18
17
16
15
14
13
5
5
LOGIC SYMBOL
CPAB
SAB
OEAB
CPBA
SBA
OEBA
B0 B1
B2 B3
B4 B5
B6 B7
1
2
3
23
22
21
A0
A1 A2
A3 A4
A5 A6
A7
4
5
6
7
8
9
10
11
20
19
18
17
16
15
14
13
V
CC
= Pin 24
GND = Pin 12
74F652A
SF00406
LOGIC DIAGRAM
A0
OEBA
B0
1D
C1
1D
C1
I of 8 channels
to 7 other channels
74F652A
21
3
23
22
1
2
4
20
OEAB
CPBA
SBA
CPAB
SAB
SF00408
Philips Semiconductors
Product specification
74F651A/74F652A
Transceivers/registers
1999 Jun 23
5
The following examples demonstrate the four fundamental
bus-management functions that can be performed with the 74F651A
and 74F652A. The select pins determine whether data is stored or
transferred through the device in real time. The output enable pins
determine the direction of the data flow.
BUS MANAGEMENT FUNCTIONS
REAL TIME BUS TRANSFER
BUS B TO BUS A
REAL TIME BUS TRANSFER
BUS A TO BUS B
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
OEAB OEBA CPAB CPBA SAB SBA
OEAB OEBA CPAB CPBA SAB SBA
OEAB OEBA CPAB CPBA SAB SBA
OEAB OEBA CPAB CPBA SAB SBA
BUS A
BUS A
BUS A
BUS A
BUS B
BUS B
BUS B
BUS B
SF00409
L
L
X
X
X
L
H
H
X
X
L
X
X
H
X
X
X
L
X
X
X
X
L
H
X
X
H
L
H or L H or L
H
H
FUNCTION TABLE
INPUTS
DATA I/O
OPERATING MODE
OEAB
OEBA
CPAB
CPBA
SAB
SBA
An
Bn
74F651A
74F652A
L
H
H or L
H or L
X
X
Input
Input
Isolation
Isolation
L
H
X
X
Input
Input
Store A and B data
Store A and B data
X
H
H or L
X
X
Input
Unspecified*
Store A, hold B
Store A hold B
H
H
L
X
Input
Output
Store A in both registers
Store A in both registers
L
X
H or L
X
X
Unspecified*
Input
Hold A, store B
Hold A, store B
L
L
X
L
Output
Input
Store B in both registers
Store B in both registers
L
L
X
X
X
L
Output
Input
Real time B data to A bus
Real time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
Stored B data to A bus
H
H
X
X
L
X
Input
Output
Real time A data to B bus
Real time A data to B bus
H
H
H or L
X
H
X
Input
Output
Stored A data to B bus
Stored A data to B bus
H
L
H or L
H or L
H
H
Output
Output
Stored A data to B bus
Stored A data to B bus
H
L
H or L
H or L
H
H
Output
Output
Stored B data to A bus
Stored B data to A bus
Notes to function table
1. H = High-voltage level
2. L
= Low-voltage level
3. *
= The data output function may be enabled or disabled by various signals at the OEBA and OEAB inputs. Data input functions are
always enabled, i.e., data at the bus pins will be stored on every low-to-high transition of the clock.
4.
= Low-to-high clock transition
5. X = Don't care
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