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Datasheet: 74HCT9046A (Philips Semiconductors)

Pll With Bandgap Controlled Vco

 

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Philips Semiconductors
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DATA SHEET
Product specification
Supersedes data of March 1994
File under Integrated Circuits, IC06
1999 Jan 11
INTEGRATED CIRCUITS
74HCT9046A
PLL with bandgap controlled VCO
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1999 Jan 11
2
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
FEATURES
Low power consumption
Centre frequency up to
17 MHz (typ.) at V
CC
= 5.5 V
Choice of two phase
comparators
(1)
:
EXCLUSIVE-OR (PC1)
Edge-triggered JK flip-flop (PC2)
No dead zone of PC2
Charge pump output on PC2,
whose current is set by an external
resistor R
b
Centre frequency tolerance
10%
Excellent
voltage-controlled-oscillator (VCO)
linearity
Low frequency drift with supply
voltage and temperature variations
On chip bandgap reference
Glitch free operation of VCO, even
at very low frequencies
Inhibit control for ON/OFF keying
and for low standby power
consumption
Operation power supply voltage
range 4.5 to 5.5 V
Zero voltage offset due to op-amp
buffering
Output capability: standard
I
CC
category: MSI.
APPLICATIONS
FM modulation and demodulation
where a small centre frequency
tolerance is essential
Frequency synthesis and
multiplication where a low jitter is
required (e.g. Video
picture-in-picture)
Frequency discrimination
(1) R
b
connected between pin 15 and
ground: PC2 mode, with PCP
OUT
at
pin 2.
Pin 15 left open or connected to V
CC
:
PC1 mode with PC1
OUT
at pin 2.
Tone decoding
Data synchronization and
conditioning
Voltage-to-frequency conversion
Motor-speed control.
GENERAL DESCRIPTION
The 74HCT9046A is a high-speed
Si-gate CMOS device. It is specified
in compliance with
"JEDEC standard
no. 7A".
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
6 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W)
a) P
D
= C
PD
V
CC
2
f
i
+
(C
L
V
CC
2
f
o
) where:
b) f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC
2
f
o
) = sum of the outputs.
2. Applies to the phase comparator section only (inhibit = HIGH). For power
dissipation of the VCO and demodulator sections see Figs 26 to 28.
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
TYP.
UNIT
f
c
VCO centre frequency
C1 = 40 pF;
R1 = 3 k
;
V
CC
= 5 V
16
MHz
C
I
input capacitance
3.5
pF
C
PD
power dissipation
capacitance per
package
notes 1 and 2
20
pF
EXTENDED
TYPE NUMBER
PACKAGE
PINS
PIN POSITION
MATERIAL
CODE
74HCT9046AN
16
DIL16
plastic
SOT38Z
74HCT9046AD
16
SO16
plastic
SOT109A
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1999 Jan 11
3
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
PINNING
SYMBOL
PIN
DESCRIPTION
GND
1
ground (0 V) (phase comparators)
PC1
OUT
/
PCP
OUT
2
phase comparator 1 output/phase
comparator pulse output
COMP
IN
3
comparator input
VCO
OUT
4
VCO output
INH
5
inhibit input
C1
A
6
capacitor C1 connection A
C1
B
7
capacitor C1 connection B
GND
8
ground (0 V) (VCO)
VCO
IN
9
VCO input
DEM
OUT
10
demodulator output
R1
11
resistor R1 connection
R2
12
resistor R2 connection
PC2
OUT
13
phase comparator 2 output
(current source adjustable with R
b
)
SIG
IN
14
signal input
R
b
15
bias resistor (R
b
) connection
V
CC
16
supply voltage
Fig.1 Pin configuration.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
PC1 /
OUT
PCP
OUT
COMP IN
VCO OUT
C1 A
C1 B
GND
VCO IN
DEM OUT
R2
R1
PC2 OUT
SIG IN
V CC
R
9046A
MBD037 - 1
INH
b
LOGIC/FUNCTIONAL SYMBOLS AND DIAGRAMS
Fig.2 Logic symbol.
MBD038 - 1
PC1 /
OUT
VCO OUT
C1 A
C1 B
VCO IN
DEM OUT
R2
R1
SIG IN
INH
VCO
6
7
11
12
9
5
4
10
2
13
3
14
15
PC2 OUT
COMPIN
R b
PCPOUT
Fig.3 IEC logic symbol.
MBD039 - 1
SIG IN
INH
6
7
11
12
9
5
4
10
2
13
3
14
15
COMP IN
PLL
9046A
PC1 /
OUT
VCO OUT
C1 A
C1 B
VCO IN
DEM OUT
R2
R1
PC2 OUT
R b
PCPOUT
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1999 Jan 11
4
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Fig.4 Functional diagram.
PHASE
COMPARATOR
2
13
PHASE
COMPARATOR
1
2
15
SIG IN
COMP IN
C1A
C1B
DEM OUT
INH
VCO IN
R2
12
11
3
14
4
7
6
5
10
9
C1
9046A
VCO
R s
R1
R4
R3
C2
PC2 OUT
MBD040 - 1
PC1 /
OUT
VCO OUT
R2
R1
R b
PCPOUT
R b
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1999
Jan
11
5
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
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MBD102 - 1
PCP
D
Q
CP
Q
R D
logic
1
D
Q
CP
Q
R D
logic
1
down
up
CHARGE
PUMP
V ref2
PC1 /
OUT
OUT
PCP
OUT
PC2
R b
R b
C2
R4
2
13
R3
15
COMP IN
SIG IN
3
14
PC1
Vref2
Vref1
BAND
GAP
5
INH
9
IN
Vref2
VCO
DEMOUT
VCOOUT
C1B
C1A
7
6
4
C1
Vref1
12
R2
11
R1
10
R
f OUT
f IN
R2
R1
s
VCO
Fig.5 Logic diagram.
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1999 Jan 11
6
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
FUNCTIONAL DESCRIPTION
The 74HCT9046A is a
phase-locked-loop circuit that
comprises a linear VCO and two
different phase comparators (PC1
and PC2) with a common signal input
amplifier and a common comparator
input (see Fig.4). The signal input can
be directly coupled to large voltage
signals (CMOS level), or indirectly
coupled (with a series capacitor) to
small voltage signals. A self-bias
input circuit keeps small voltage
signals within the linear region of the
input amplifiers. With a passive
low-pass filter, the '9046A' forms a
second-order loop PLL.
The principle of this
phase-locked-loop is based on the
familiar HCT4046A. However extra
features are built in, allowing very
high performance phase-locked-loop
applications. This is done, at the
expense of PC3, which is skipped in
this HCT9046A. The PC2 is equipped
with a current source output stage
here. Further a bandgap is applied for
all internal references, allowing a
small centre frequency tolerance. The
details are summed up in the next
section called: "Differences with
respect to the familiar HCT4046A".
If one is familiar with the HCT4046A
already, it will do to read this section
only.
DIFFERENCES WITH RESPECT TO
THE FAMILIAR HCT4046A
A centre frequency tolerance of
maximum
10%.
The on board bandgap sets the
internal references resulting in a
minimal frequency shift at supply
voltage variations and temperature
variations.
The value of the frequency offset is
determined by an internal
reference voltage of 2.5 V instead
of V
CC
-
0.7 V. In this way the offset
frequency will not shift over the
supply voltage range.
A current switch charge pump
output on PC2 allows a virtually
ideal performance of PC2. The gain
of PC2 is independent of the
voltage across the low-pass filter.
Further a passive low-pass filter in
the loop achieves an active
performance now. The influence of
the parasitic capacitance of the
PC2 output plays no role here,
resulting in a true correspondence
of the output correction pulse and
the phase difference even up to
phase differences as small as a few
nanoseconds.
Because of its linear performance
without dead zone, higher
impedance values for the filter,
hence lower C-values, can now be
chosen. Correct operation will not
be influenced by parasitic
capacitances as in the instance
with voltage source output of the
4046A.
No PC3 on pin 15 but instead a
resistor connected to GND, which
sets the load/unload currents of the
charge pump (PC2).
Extra GND pin at pin 1 to allow an
excellent FM demodulator
performance even at 10 MHz and
higher.
Combined function of pin 2. If
pin 15 is connected to V
CC
(no bias
resistor R
b
) pin 2 has its familiar
function viz. output of PC1. If at
pin 15 a resistor (R
b
) is connected
to GND it is assumed that PC2 has
been chosen as phase comparator.
Connection of R
b
is sensed by
internal circuitry and this changes
the function of pin 2 into a lock
detect output (PCP
OUT
) with the
same characteristics as PCP
OUT
of
pin 1 of the well known
74HCT4046A.
The inhibit function differs. For the
HCT4046A a HIGH level at the
inhibit input (INH) disables the VCO
and demodulator, while a LOW
level turns both on. For the
74HCT9046A a HIGH level on the
inhibit input disables the whole
circuit to minimize standby power
consumption.
VCO
The VCO requires one external
capacitor C1 (between C1
A
and C1
B
)
and one external resistor R1
(between R1 and GND) or two
external resistors R1 and R2
(between R1 and GND, and R2 and
GND). Resistor R1 and capacitor C1
determine the frequency range of the
VCO. Resistor R2 enables the VCO
to have a frequency offset if required
(see Fig.5).
The high input impedance of the VCO
simplifies the design of the low-pass
filters by giving the designer a wide
choice of resistor/capacitor ranges. In
order not to load the low-pass filter, a
demodulator output of the VCO input
voltage is provided at pin 10
(DEM
OUT
). The DEM
OUT
voltage
equals that of the VCO input. If
DEM
OUT
is used, a load resistor (R
s
)
should be connected from pin 10 to
GND; if unused, DEM
OUT
should be
left open. The VCO output (VCO
OUT
)
can be connected directly to the
comparator input (COMP
IN
), or
connected via a frequency-divider.
The VCO output signal has a duty
factor of 50% (maximum expected
deviation 1%), if the VCO input is held
at a constant DC level. A LOW level at
the inhibit input (INH) enables the
VCO and demodulator, while a HIGH
level turns both off to minimize
standby power consumption.
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1999 Jan 11
7
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Phase comparators
The signal input (SIG
IN
) can be
directly coupled to the self-biasing
amplifier at pin 14, provided that the
signal swing is between the standard
HC family input logic levels.
Capacitive coupling is required for
signals with smaller swings.
P
HASE COMPARATOR
1 (PC1)
This circuit is an EXCLUSIVE-OR
network. The signal and comparator
input frequencies (f
i
) must have a
50% duty factor to obtain the
maximum locking range. The transfer
characteristic of PC1, assuming
ripple (f
r
= 2f
i
) is suppressed, is:
where:
V
DEMOUT
is the demodulator output
at pin 10.
V
DEMOUT
= V
PC1OUT
(via low-pass).
The phase comparator gain is:
The average output voltage from
PC1, fed to the VCO input via the
low-pass filter and seen at the
demodulator output at pin 10
(V
DEMOUT
), is the resultant of the
phase differences of signals (SIG
IN
)
and the comparator input (COMP
IN
)
as shown in Fig.6. The average of
V
DEMOUT
is equal to
1
/
2
V
CC
when
there is no signal or noise at SIG
IN
and with this input the VCO oscillates
at the centre frequency (f
c
). Typical
waveforms for the PC1 loop locked at
f
c
are shown in Fig.7. This figure also
shows the actual waveforms across
the VCO capacitor at pins 6 and 7
(V
C1A
and V
C1B
) to show the relation
between these ramps and the
VCO
OUT
voltage.
V
DEMOUT
V
CC
-----------
SIGIN
COMPIN
(
)
=
K
p
V
CC
----------- V r
/
(
)
=
The frequency capture range (2f
c
) is
defined as the frequency range of
input signals on which the PLL will
lock if it was initially out-of-lock. The
frequency lock range (2f
L
) is defined
as the frequency range of the input
signals on which the loop will stay
locked if it was initially in lock. The
capture range is smaller or equal to
the lock range.
With PC1, the capture range depends
on the low-pass filter characteristics
and can be made as large as the lock
range. This configuration remains
locked even with very noisy input
signals. Typical behaviour of this type
of phase comparator is that it may
lock to input frequencies close to the
harmonics of the VCO centre
frequency.
P
HASE COMPARATOR
2 (PC2)
This is a positive edge-triggered
phase and frequency detector. When
the PLL is using this comparator, the
loop is controlled by positive signal
transitions and the duty factors of
SIG
IN
and COMP
IN
are not important.
PC2 comprises two D-type flip-flops,
control gating and a 3-state output
stage with sink and source transistors
acting as current sources, henceforth
called charge pump output of PC2.
The circuit functions as an up-down
counter (Fig.5) where SIG
IN
causes
an up-count and COMP
IN
a down
count. The current switch charge
pump output allows a virtually ideal
performance of PC2, due to appliance
of some pulse overlap of the up and
down signals. See Fig.8a.
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1999 Jan 11
8
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Fig.6 Phase comparator 1; average output voltage as a function of input phase difference.
MBD101 - 1
180
o
PCIN
0
o
90
o
1/2V
0
V
VDEMOUT(AV)
CC
CC
V
DEMOUT
V
PC1OUT
V
CC
-----------
SIGIN
COMPIN
(
)
=
=
PCIN
SIGIN
COMPIN
(
)
=
Fig.7 Typical waveforms for PLL using phase comparator 1; loop-locked at f
c
.
MBD100
PC1 OUT
VCO IN
VCC
GND
VCO OUT
COMP IN
SIGN IN
pin 6
pin 7
VC1A
VC1B
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1999 Jan 11
9
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
The pump current I
P
is independent
from the supply voltage and is set by
the internal bandgap reference of
2.5 V.
R
b
is the external bias resistor
between pin 15 and ground.
The current and voltage transfer
function of PC2 are shown in Fig.9.
The phase comparator gain is:
Typical waveforms for the PC2 loop
locked at f
c
are shown in Fig.10.
When the frequencies of SIG
IN
and
COMP
IN
are equal but the phase of
SIG
IN
leads that of COMP
IN
, the up
output driver at PC2
OUT
is held `ON'
for a time corresponding to the phase
difference (
PCIN
). When the phase of
SIG
IN
lags that of COMP
IN
, the down
or sink driver is held `ON'.
When the frequency of SIG
IN
is higher
than that of COMP
IN
, the source
output driver is held `ON' for most of
the input signal cycle time and for the
remainder of the cycle time both
drivers are `OFF' (3-state). If the
SIG
IN
frequency is lower than the
COMP
IN
frequency, then it is the sink
driver that is held `ON' for most of the
cycle. Subsequently the voltage at the
capacitor (C2) of the low-pass filter
connected to PC2
OUT
varies until the
signal and comparator inputs are
equal in both phase and frequency. At
this stable point the voltage on C2
remains constant as the PC2 output is
in 3-state and the VCO input at pin 9
is a high impedance. Also in this
condition the signal at the phase
comparator pulse output (PCP
OUT
)
has a minimum output pulse width
equal to the overlap time, so can be
used for indicating a locked condition.
I
P
17
2.5
R
b
-------- A
( )
=
K
p
I
P
2
------- A r
/
(
)
=
Thus for PC2 no phase difference
exists between SIG
IN
and COMP
IN
over the full frequency range of the
VCO. Moreover, the power
dissipation due to the low-pass filter is
reduced because both output drivers
are OFF for most of the signal input
cycle. It should be noted that the PLL
lock range for this type of phase
comparator is equal to the capture
range and is independent of the
low-pass filter. With no signal present
at SIG
IN
the VCO adjust, via PC2, to
its lowest frequency.
By using current sources as charge
pump output on PC2, the dead zone
or backlash time could be reduced to
zero. Also, the pulse widening due to
the parasitic output capacitance plays
no role here. This enables a linear
transfer function, even in the vicinity
of the zero crossing. The differences
between a voltage switch charge
pump and a current switch charge
pump are shown in Fig.11.
The design of the low-pass filter is
somewhat different when using
current sources. The external resistor
R3 is no longer present when using
PC2 as phase comparator. The
current source is set by R
b
. A simple
capacitor behaves as an ideal
integrator now, because the capacitor
is charged by a constant current. The
transfer function of the voltage switch
charge pump may be used. In fact it is
even more valid, because the transfer
function is no longer restricted for
small changes only. Further the
current is independent from both the
supply voltage and the voltage across
the filter. For one that is familiar with
the low-pass filter design of the
4046A a relation may show how R
b
relates with a fictive series resistance,
called R3'.
This relation can be derived by
assuming first that a voltage
controlled switch PC2 of the 4046A is
connected to the filter capacitance C2
via this fictive R3' (see Fig.8b). Then
during the PC2 output pulse the
charge current equals:
With the initial voltage V
C2(0)
at:
1
/
2
V
CC
= 2.5 V,
As shown before the charge current
of the current switch of the 9046A is:
Hence:
Using this equivalent resistance R3'
for the filter design the voltage can
now be expressed as a transfer
function of PC2; assuming ripple
(f
r
= f
i
) is suppressed, as:
Again this illustrates the supply
voltage independent behaviour of
PC2.
Examples of PC2 combined with a
passive filter are shown in Figs 12
and 13. Figure 12 shows that PC2
with only a C2 filter behaves as a
high-gain filter. For stability the
damped version of Fig.13 with series
resistance R4 is preferred.
Practical design values for R
b
are
between 25 and 250 k
with
R3' = 1.5 to 15 k
for the filter design.
Higher values for R3' require lower
values for the filter capacitance which
is very advantageous at low values
the loop natural frequency
n
.
I
P
V
CC
V
C2 0
( )
R3'
-----------------------------------
=
I
P
2.5
R3'
---------
=
I
P
17
2.5
R
b
--------
=
R3'
R
b
17
-------
( )
=
K
PC2
5
4
------- V r
/
(
)
=
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1999 Jan 11
10
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
MBD099
R3'
I P
up
down
C2
VCC
PC2 OUT
VC2 OUT
Fig.8 The current switch charge pump output of PC2.
b.
a.
MBD046 - 1
PC2 OUT
C2
VCC
I P
I P
down
up
=
pulse overlap of
approximately 15 ns
PCIN
a. At every
, even at zero
both switches are closed simultaneously for a short period (typically 15 ns).
b. Comparable voltage-controlled switch.
0
MSB306 - 1
2
0
1/2V
0
V
VDEMOUT(AV)
CC
CC
PCIN
2
I x R
P
PCIN =
SIGIN
COMPIN
2
0
PCIN
2
I P
I P
Fig.9 Phase comparator 2.
Two kinds of transfer functions may be regarded:
a. The current transfer:
b. The voltage transfer; this transfer can be observed at PC2
OUT
by connecting a resistor (R = 10 k
) between PC2
OUT
and
1
/
2
V
CC
;
pump current
I
P
2
-------
PCIN
V
DEMOUT
V
PC2OUT
5
4
-------
PCIN
=
=
b.
a.
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1999 Jan 11
11
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
MBD047 - 1
SIG IN
COMPIN
VCO OUT
high impedance OFF state,
(zero current)
UP
DOWN
CURRENT AT
PC2 OUT
PC2 /VCO
OUT
IN
PCPOUT
OPC IN
Fig.10 Timing diagram for PC2.
The pulse overlap of the up and down signals (typically 15 ns).
Fig.11 The response of a locked-loop in the vicinity of the zero crossing of the phase error.
b. Response with current switch charge-pump PC2
OUT
as applied in the HCT9046A.
MBD043
25
2.50
2.75
2.25
VCO IN
0
25
phase error (ns)
(1)
(1)
(2)
25
2.50
2.75
2.25
VCO IN
0
25
phase error (ns)
a. Response with traditional voltage-switch charge-pump PC2
OUT
(4046A).
(1) Due to parasitic capacitance on PC2
OUT
.
(2) Backlash time (dead zone).
b.
a.
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1999 Jan 11
12
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
LOOP FILTER COMPONENT SELECTION
MBD045 - 1
j
(
)
F
1/
OUTPUT
INPUT
C2
I P
I P
17
R b
1/
1
A
A
1
A
Fig.12 Simple loop filter for PC2 without damping.
a.
b. Amplitude characteristic:
c. Pole zero diagram.
1
R
b
17
-------
C2
R3'
C2
=
=
F
j
( )
1
1 A
/
j
1
+
-----------------------------
1
j
1
-----------
=
a.
b.
c.
MBD044 - 1
j
(
)
F
m
1 /
2
O
1/
2
1/
1
OUTPUT
INPUT
R4
C2
I P
I P
17
R b
A
1/
1
A
A
Fig.13 Simple loop filter for PC2 with damping.
a.
b. Amplitude characteristic:
c. Pole zero diagram.
A = DC gain limit, due to leakage.
1
R
b
17
-------
C2
R3'
C2
=
=
2
R4
C2
=
F
j
( )
1
j
2
+
1 A
/
j
1
+
-----------------------------
=
a.
b.
c.
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1999 Jan 11
13
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
RECOMMENDED OPERATING CONDITIONS FOR 74HCT
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
Note
1. Temperature range:
-
40 to +125
C.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
CC
DC supply voltage
4.5
5.0
5.5
V
V
I
DC input voltage
0
-
V
CC
V
V
O
DC output voltage
0
-
V
CC
V
T
amb
operating ambient temperature
see DC and AC Characteristics
-
40
-
+85
C
-
40
-
+125
C
t
r
, t
f
input rise and fall times (pin 5)
V
CC
= 4.5 V
-
6
500
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
CC
DC supply voltage
-
0.5
+7
V
I
IK
DC input diode current
for V
I
< -
0.5 V
or V
I
>
V
CC
+ 0.5 V
-
20
mA
I
OK
DC output diode current
for V
O
< -
0.5 V
or V
O
>
V
CC
+ 0.5 V
-
20
mA
I
O
DC output source or sink current
for
-
0.5 V
<
V
O
<
V
CC
+ 0.5 V
-
25
mA
I
CC
; I
GND
DC V
CC
or GND current
-
50
mA
T
stg
storage temperature
-
65
+150
C
P
tot
total power dissipation per package
note 1
plastic DIL
above +70
C: derate linearly
with 12 mW/K
-
750
mW
plastic mini-pack (SO)
above +70
C: derate linearly
with 8 mW/K
-
500
mW
background image
1999 Jan 11
14
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
DC CHARACTERISTICS FOR 74HCT
Voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
+25
-
40 to +85
-
40 to +125
V
CC
(V)
V
I
(V)
OTHER
MIN.
TYP.
MAX.
MIN.
MAX.
MIN.
MAX.
Phase comparator section
V
IH
DC coupled
HIGH level input
voltage SIG
IN
,
COMP
IN
3.15
2.4
-
3.15
-
3.15
-
V
4.5
-
V
IL
DC coupled LOW
level input
voltage SIG
IN
,
COMP
IN
-
2.1
1.35
-
1.35
-
1.35
V
4.5
-
V
OH
HIGH level
output voltage
PCP
OUT
, PCn
OUT
4.4
4.5
-
4.4
-
4.4
-
V
4.5
V
IH
or
V
IL
I
O
=
-
20
A
3.98
4.32
-
3.84
-
3.7
-
V
4.5
V
IH
or
V
IL
I
O
=
-
4.0 mA
V
OL
LOW level
output voltage
PCP
OUT
, PCn
OUT
-
0
0.1
-
0.1
-
0.1
V
4.5
V
IH
or
V
IL
I
O
=
-
20
A
-
0.15
0.26
-
0.33
-
0.4
V
4.5
V
IH
or
V
IL
I
O
=
-
4.0 mA
I
I
input leakage
current SIG
IN
,
COMP
IN
-
-
30
-
38
-
45
A
5.5
V
CC
or
GND
I
OZ
3-state
OFF-state
current PC2
OUT
-
-
0.5
-
5.0
-
10.0
A
5.5
V
IH
or
V
IL
V
O
= V
CC
or
GND
R
I
input resistance
SIG
IN
, COMP
IN
-
250
-
-
-
-
-
k
4.5
V
I
at self-bias
operating point;
V
I
= 0.5 V;
see Figs 14 to 16
R
b
bias resistance
25
-
250
-
-
-
-
k
4.5
-
I
P
charge pump
current
0.53
1.06
2.12
-
-
-
-
mA
4.5
-
R
b
= 40 k
background image
1999 Jan 11
15
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
VCO section
V
IH
DC coupled
HIGH level input
voltage INH
2.0
1.6
-
2.0
-
2.0
-
V
4.5
to 5.5
-
V
IL
DC coupled LOW
level input
voltage INH
-
1.2
0.8
-
0.8
-
0.8
V
4.5
to 5.5
-
V
OH
HIGH level
output voltage
VCO
OUT
4.4
4.5
-
4.4
-
4.4
-
V
4.5
V
IH
or
V
IL
I
O
=
-
20
A
3.98
4.32
-
3.84
-
3.7
-
V
4.5
V
IH
or
V
IL
I
O
=
-
4.0 mA
V
OL
LOW level
output voltage
VCO
OUT
-
0
0.1
-
0.1
-
0.1
V
4.5
V
IH
or
V
IL
I
O
= 20
A
-
0.15
0.26
-
0.33
-
0.4
V
4.5
V
IH
or
V
IL
I
O
= 4.0 mA
V
OL
LOW level
output voltage
C1
A
, C1
B
-
-
0.40
-
0.47
-
0.54
V
4.5
V
IH
or
V
IL
I
O
= 4.0 mA
I
I
input leakage
current INH and
VCO
IN
-
-
0.1
-
1.0
-
1.0
A
5.5
V
CC
or
GND
R1
resistance
3
-
300
-
-
-
-
k
4.5
-
R2
resistance
3
-
300
-
-
-
-
k
4.5
-
C1
capacitance
40
-
no
limit
-
-
-
-
pF
4.5
-
V
VCOIN
operating
voltage range at
VCO
IN
1.1
-
3.4
-
-
-
-
V
4.5
-
over the
range
specified
for R1
1.1
-
3.9
-
-
-
-
V
5.0
-
1.1
-
4.4
-
-
-
-
V
5.5
-
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
+25
-
40 to +85
-
40 to +125
V
CC
(V)
V
I
(V)
OTHER
MIN.
TYP.
MAX.
MIN.
MAX.
MIN.
MAX.
background image
1999 Jan 11
16
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Note
1. The value of additional quiescent supply current (
I
CC
) for a unit load of 1 is given above. To determine
I
CC
per
input, multiply this value by the unit load coefficient shown in Table 1.
Table 1 Unit load coefficient table.
Demodulator section
R
s
resistance
50
-
300
-
-
-
-
k
4.5
-
at R
s
>
300 k
the
leakage
current can
influence
V
DEMOUT
V
OFF
offset voltage
VCO
IN
to
V
DEMOUT
-
20
-
-
-
-
-
mV
4.5
-
V
I
= V
VCOIN
=
1
/
2
V
CC
;
values
taken over
R
s
range,
see Fig.17
R
D
dynamic output
resistance at
DEM
OUT
-
25
-
-
-
-
-
4.5
-
V
DEMOUT
=
1
/
2
V
CC
Quiescent supply current
I
CC
quiescent supply
current
(disabled)
-
-
8.0
-
80.0
-
160.0
A
5.5
-
pin 5 at V
CC
I
CC
additional
quiescent supply
current per input
pin for unit load
coefficient is 1;
note 1;
V
I
= V
CC
-
2.1 V
-
100
360
-
450
-
490
A
4.5
-
other inputs
at V
CC
or
GND
INPUT
UNIT LOAD COEFFICIENT
INH
1.00
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITIONS
+25
-
40 to +85
-
40 to +125
V
CC
(V)
V
I
(V)
OTHER
MIN.
TYP.
MAX.
MIN.
MAX.
MIN.
MAX.
background image
1999 Jan 11
17
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Fig.14 Typical input resistance curve at SIG
IN
,
COMP
IN
.
MBD108
self-bias operating point
V I
V I
I I
Fig.15 Input resistance at SIG
IN
; COMP
IN
with
V
I
= 0.5 V at self-bias point.
800
600
200
0
400
MGA956 - 1
V (V)
I
1/2V
0.25
CC
1/2V CC
1/2V
0.25
CC
R I
(k
)
5.5 V
4.5 V
V =
CC
Fig.16 Input current at SIG
IN
; COMP
IN
with
V
I
= 0.5 V at self-bias point.
5
5
0
MGA957
V (V)
I
1/2 V
0.25
CC
1/2 VCC
1/2 V
0.25
CC
II
(
A)
4.5 V
5.5 V
V =
CC
5.5 V
4.5 V
Fig.17 Offset voltage at demodulator output as a
function of VCO
IN
and R
s
.
40
40
0
MGA958
V (V)
1/2 V
2
CC
1/2 VCC
1/2 V
2
CC
20
20
60
VOFF
(mV)
VCOIN
5.5 V
4.5 V
V =
CC
___ R
s
= 50 k
.
- - - R
s
= 300 k
.
background image
1999 Jan 11
18
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF.
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITION
+25
-
40 to +85
-
40 to +125
V
CC
(V)
WAVEFORMS
MIN.
TYP.
MAX.
MIN.
MAX.
MIN.
MAX.
Phase comparator section
t
PHL
/t
PLH
propagation delay
SIG
IN
, COMP
IN
to
PC1
OUT
-
23
40
-
50
-
60
ns
4.5
Fig.18
t
PHL
/t
PLH
propagation delay
SIG
IN
, COMP
IN
to
PCP
OUT
-
35
68
-
85
-
102
ns
4.5
Fig.18
t
PZH
/t
PZL
3
-
state output
enable time SIG
IN
,
COMP
IN
to
PC2
OUT
-
30
56
-
70
-
84
ns
4.5
Fig.19
t
PHZ
/t
PLZ
3
-
state output
enable time SIG
IN
,
COMP
IN
to
PC2
OUT
-
36
65
-
81
-
98
ns
4.5
Fig.19
t
THL
/t
TLH
output transition
time
-
7
15
-
19
-
22
ns
4.5
Fig.18
V
i(p-p)
AC coupled input
sensitivity
(peak-to-peak
value) at SIGN
IN
or
COMP
IN
-
15
-
-
-
-
-
mV
4.5
f
i
= 1 MHz
background image
1999 Jan 11
19
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
VCO section
f/T
frequency stability
with temperature
change
-
-
-
0.06
-
-
-
%/K
4.5
V
VCOIN
=
1
/
2
V
CC
;
recommended
range:
R1 = 10 k
;
R2 = 10 k
;
C1 = 1 nF;
Figs 20 to 22
f
c
centre frequency
tolerance
-
10
-
+10
-
-
-
-
%
5.0
V
VCOIN
= 3.9 V;
R1 = 10 k
;
R2 = 10 k
;
C1 = 1 nF
f
c
VCO centre
frequency
(duty factor = 50%)
11.0
15.0
-
-
-
-
-
MHz
4.5
V
VCOIN
=
1
/
2
V
CC
;
R1 = 4.3 k
;
R2 =
;
C1 = 40 pF;
Figs 23 and 31
f
VCO
VCO frequency
linearity
-
0.4
-
-
-
-
-
%
4.5
R1 = 100 k
;
R2 =
;
C1 = 100 pF;
Figs 24 and 25
VCO
duty factor at
VCO
OUT
-
50
-
-
-
-
-
%
4.5
SYMBOL
PARAMETER
T
amb
(
C)
UNIT
TEST CONDITION
+25
-
40 to +85
-
40 to +125
V
CC
(V)
WAVEFORMS
MIN.
TYP.
MAX.
MIN.
MAX.
MIN.
MAX.
background image
1999 Jan 11
20
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Fig.18 Waveforms showing input (SIG
IN
and COMP
IN
) to output (PCP
OUT
and PC1
OUT
) propagation delays and
the output transition times.
MBD106
t PHL
t THL
t PLH
t TLH
SIG , COMP
IN
IN
INPUTS
PCP , PC1 ,
OUT
OUT
OUTPUTS
VM
(1)
VM
(1)
(1) V
M
=
1
/
2
V
CC
; V
I
= GND to V
CC
.
Fig.19 Waveforms showing the 3-state enable and disable times for PC2
OUT
.
MGA941
t PLZ
t PZH
t PHZ
10%
90%
t PZL
SIG IN
INPUT
COMPIN
INPUT
PC2 OUT
OUTPUT
M
V
(1)
M
V
(1)
M
V
(1)
(1) V
M
=
1
/
2
V
CC
; V
I
= GND to V
CC
.
background image
1999 Jan 11
21
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
50
0
50
150
20
10
10
20
0
MBD115
100
f
(%)
5.5 V
4.5 V
V =
CC
T ( C)
amb
o
Fig.20 Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter.
MBD116
T ( C)
amb
0
f
(%)
o
150
100
50
0
50
15
10
5
5
10
15
5.5 V
4.5 V
V =
CC
a. R1 = 3 k
; R2 =
; C1 = 100 pF.
b. R1 = 10 k
; R2 =
;
C1 = 100 pF.
b.
a.
50
0
50
150
10
5
5
10
0
MBD124
100
f
(%)
5.5 V
4.5 V
V =
CC
T ( C)
amb
o
Fig.21 Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter.
MBD117
T ( C)
amb
0
f
(%)
o
150
100
50
0
50
20
15
10
5
10
15
5.5 V
4.5 V
V =
CC
5
a. R1 = 300 k
; R2 =
; C1 = 100 pF.
b. R1 =
; R2 = 3 k
; C1 = 100 pF.
b.
a.
background image
1999 Jan 11
22
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
MBD118
T ( C)
amb
0
f
(%)
o
150
100
50
0
50
12
8
4
4
8
5.5 V
4.5 V
V =
CC
Fig.22 Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter.
MBD119
T ( C)
amb
0
f
(%)
o
150
100
50
0
50
10
5
5
10
5.5 V
4.5 V
V =
CC
a. R1 =
; R2 = 10 k
; C1 = 100 pF.
b. R1 =
; R2 = 300 k
; C1 = 100 pF.
b.
a.
background image
1999 Jan 11
23
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Fig.23 Graphs showing VCO frequency as a function of the VCO input voltage (V
VCOIN
).
a. R1 = 4.3 k
; C1 = 39 pF.
b. R1 = 4.3 k
; C1 = 100 nF.
c. R1 = 300 k
; C1 = 39 pF.
d. R1 = 300 k
; C1 = 100 nF.
a.
b.
c.
d.
handbook, halfpage
0
2
4
6
800
600
200
0
400
MBD120 - 1
V (V)
VCOIN
f VCO
(kHz)
V = 5.5 V
CC
4.5 V
handbook, halfpage
0
2
4
6
400
300
100
0
200
MBD111 - 1
V (V)
VCOIN
f VCO
(Hz)
frequency
frequency
4.5 V
5.5 V
V =
CC
0
2
4
6
30
10
0
20
MBD112
V (V)
VCOIN
f VCO
(MHz)
5.5 V
4.5 V
V =
CC
0
2
4
6
30
10
0
20
MBD113
V (V)
VCOIN
f VCO
(kHz)
5.5 V
4.5 V
V =
CC
background image
1999 Jan 11
24
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Fig.24 Definition of VCO frequency linearity:
V = 0.5 V over the V
CC
range.
MGA937 - 1
f
max
f1
min
1/2VCC
f'c
f c
f2
VVCOIN
V
V
f
c
f
1
f
2
+
2
---------------
=
linearity
f
c
f
c
f
c
----------------
100%
=
Fig.25 Frequency linearity as a function of R1, C1
and V
CC
.
4
4
0
1
MBD114
10
10
2
10
3
8
f VCO
(%)
R1 (k
)
C1 = 1
F
4.5 V
5.5 V
C1 =
39 pF
4.5 V
5.5 V
R2 =
and
V = 0.5 V.
Fig.26 Power dissipation as a function of
component values.
300
0
100
MBD121
10
1
1
200
10
2
R1 (k
)
4.5 V
C1 = 1
F
5.5 V
C1 = 39 pF
4.5 V
C1 = 39 pF
5.5 V
C1 = 1
F
CC
V =
PD
(W)
R2 =
.
Fig.27 Power dissipation as a function of
component values.
R1 =
.
300
0
100
MBD110
10
1
1
200
10
2
R2 (k
)
P
5.5 V
C1 = 39 pF
CC
5.5 V
4.5 V
C1 = 1
F
4.5 V
C1 = 39 pF
V =
D
(W)
background image
1999 Jan 11
25
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Fig.28 Typical power dissipation.
10
3
MBD109
10
2
10
10
4
P DEM
(W)
R (k
)
s
V =
CC
5.5 V
4.5 V
10
5
10
3
APPLICATION INFORMATION
This information is a guide for the approximation of values
of external components to be used with the 74HCT9046A
in a phase-locked-loop system.
Values of the selected components should be within the
rages shown in Table 2.
Table 2 Survey of components.
COMPONENT
VALUE
R1
between 3 k
and 300 k
R2
between 3 k
and 300 k
R1 + R2
parallel value >2.7 k
C1
>40 pF
Table 3 Design considerations for VCO section.
SUBJECT
PHASE
COMPARATOR
DESIGN CONSIDERATION
VCO frequency without
extra offset
PC1, PC2
VCO frequency characteristic
With R2 =
and R1 within the range 3 k
<
R1
<
300 k
, the
characteristics of the VCO operation will be as shown in Fig.29a.
(Due to R1, C1 time constant a small offset remains when R2 =
).
PC1
Selection of R1 and C1
Given f
c
, determine the values of R1 and C1 using Fig.31.
PC2
Given f
max
and f
c
determine the values of R1 and C1 using Fig.31; use
Fig.33 to obtain 2f
L
and then use this to calculate f
min
.
VCO frequency
with extra offset
PC1, PC2
VCO frequency characteristic
With R1 and R2 within the ranges 3 k
<
R1
<
300 k
<
R2
<
300 k
,
the characteristics of the VCO operation is as shown in Fig.29b.
PC1, PC2
Selection of R1, R2 and C1
Given f
c
and f
L
determine the value of product R1C1 by using Fig.33.
Calculate f
off
from the equation f
off
= f
c
-
1.6f
L
.
Obtain the values of C1 and R2 by using Fig.32.
Calculate the value of R1 from the value of C1 and the product R1C1.
PLL conditions with no
signal at the SIG
IN
input
PC1
VCO adjusts to f
c
with
PCIN
= 90
and V
VCOIN
=
1
/
2
V
CC
.
PC2
VCO adjusts to f
offset
with
PCIN
=
-
360
and V
VCOIN
= minimum.
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1999 Jan 11
26
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
0.6f L
f off
f VCO
fmax
fc
f min
1.1 V
1/2VCC
VCC 1.1 V
VCC
VCO IN
2f L
due to
R1,C1
due to
R2,C1
MGA939 - 1
MGA938 - 1
f VCO
fmax
fc
f min
1.1 V
1/2VCC
VCC 1.1 V
VCC
VCO IN
2f L
due to
R1,C1
Fig.29 Frequency characteristic of VCO.
a. Operating without offset; f
c
= centre frequency; 2f
L
= frequency lock range.
b. Operating with offset; f
c
= centre frequency; 2f
L
= frequency lock range.
b.
a.
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1999 Jan 11
27
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Filter design considerations for PC1 and PC2 of the HCT9046A
Figure 30 shows some examples of passive and active filters to be used with the phase comparators of the HCT9046A.
Transfer functions of phase comparators and filters are given in Table 4.
Table 4 Transfer functions of phase comparators and filters.
PHASE
COMPARATOR
Fig.30
FILTER TYPE
TRANSFER FUNCTION
EXPLANATION
PC1
a.
passive filter
without
damping
b.
passive filter
with damping
1
= R3
C2;
2
= R4
C2;
3
= R4
C3;
A = 10
5
= DC gain amplitude
c.
active filter
with damping
PC2
d.
passive filter
with damping
A = 10
5
= limit DC gain
1
= R3'
C2;
2
= R4
C2;
3
= R4
C3;
R3' = R
b
/17;
R
b
= 25 to 250 k
e.
active filter
with damping
A = 10
5
= DC gain amplitude
F
j
( )
1
1
j
1
+
---------------------
=
K
PC1
V
CC
----------- V r
/
=
F
j
( )
1
j
2
+
1
j
1
2
+
(
)
+
----------------------------------------
=
F
j
( )
1
j
2
+
1 A
/
j
1
+
-----------------------------
=
1
j
2
+
j
1
---------------------
F
j
( )
1
j
2
+
1 A
/
j
1
+
-----------------------------
=
1
j
2
+
j
1
---------------------
K
PC2
5
4
------- V r
/
=
F
j
( )
1
j
2
+
1 A
/
j
1
+
-----------------------------
=
1
j
2
+
j
1
---------------------
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1999 Jan 11
28
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
MBD107 - 1
X
1/
R3
C2
F(j
)
R3
C2
C3
R4
C3
A
R4
C2
R3
R3'
C2
R4
AR3'
A
C3
R4
C2
O
X
2
1
1
2
O
X
2
1/
2
1/
3
1/
O
X
2
1/ A
1/
1
O
X
2
1/ A
1/
1
A
1/
2
1/
3
1/
1
A
A
1/
2
1/
3
1
1/A
A
1/
2
1/
3
CIRCUIT
AMPLITUDE
CHARACTERISTIC
POLE ZERO
DIAGRAM
1/
1
1
1
2
1/
1/
1
A
PC2
PC1
1
1/A
R3'
1/
F(j
)
Fig.30 Passive and active filters for HCT9046A.
a.
b.
c.
d.
e.
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1999 Jan 11
29
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
General design consideration.
SUBJECT
PHASE
COMPARATOR
DESIGN CONSIDERATION
PLL locks on harmonics at
centre frequency
PC1
yes
PC2
no
Noise rejection at signal
input
PC1
high
PC2
low
AC ripple content when PLL
is locked
PC1
f
r
= 2f
i
; large ripple content at
PCIN
= 90
PC2
f
r
= f
i
; small ripple content at
PCIN
= 0
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1999 Jan 11
30
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Fig.31 Typical value of VCO centre frequency (f
c
) as a function of C1.
10
7
10
5
10
4
10
3
10
1
10
5
10
3
10
10
2
10
4
10
6
10
6
C1 (pF)
10
7
10
8
(Hz)
fc
10
2
MBD103 - 1
V =
CC
5.5 V
4.5 V
R1 = 3 k
R1 = 10 k
R1 = 150 k
R1 = 300 k
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
R2 =
; V
VCOIN
=
1
/
2
V
CC
; INH = GND; T
amb
= 25
C.
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1999 Jan 11
31
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Fig.32 Typical value of frequency offset as a function of C1.
10
7
10
5
10
4
10
3
10
1
10
5
10
3
10
10
2
10
4
10
6
10
6
C1 (pF)
10
7
10
8
(Hz)
foff
10
2
MBD104
R2 = 150 k
R2 = 300 k
R2 = 3 k
R2 = 10 k
V =
CC
4.5 V - 5.5 V
4.5 V - 5.5 V
4.5 V - 5.5 V
4.5 V - 5.5 V
R1 =
; V
VCOIN
=
1
/
2
V
CC
; INH = GND; T
amb
= 25
C.
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1999 Jan 11
32
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Fig.33 Typical frequency lock range 2f
L
as a function of the product R1 and C1.
V
VCOIN
= 1.1 to (V
CC
-
1.1) V.
K
v
2f
L
V
VCOIN
range
-------------------------------------2
r s
/
V
/
(
)
=
10
7
10
5
10
3
10
10
2
10
4
10
6
R1C1 (s)
10
7
10
8
(Hz)
2fL
MBD105 - 1
V =
CC
10
6
10
5
10
4
10
3
10
2
10
1
1
5.5 V
4.5 V
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1999 Jan 11
33
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
PLL design example
The frequency synthesizer used in
the design example shown in Fig.34
has the following parameters:
Output frequency: 2 MHz to 3 MHz.
Frequency steps: 100 kHz.
Settling time: 1 ms.
Overshoot: <20%.
The open loop gain is:
H (s)
G (s) = K
p
K
f
K
o
K
n
and the closed loop:
where:
K
p
= phase comparator gain
K
f
= low-pass filter transfer gain
K
o
= K
v
/s VCO gain
K
n
=
1
/
n
divider ratio.
The programmable counter ratio K
n
can be found as follows:
The VCO is set by the values of R1,
R2 and C1; R2 = 10 k
(adjustable).
The values can be determined using
the information in Table 3.
With f
c
= 2.5 MHz and f
L
= 500 kHz
this gives the following values
(V
CC
= 5.0 V):
R1 = 30 k
.
R2 = 30 k
.
C1 = 100 pF.
The VCO gain is:
u
i
-------
K
p
K
f
K
o
K
n
1
K
p
K
f
K
o
K
n
+
------------------------------------------------------
=
N
min
f
OUT
f
step
------------
2 MHz
100 kHz
----------------------
20
=
=
=
N
max
f
OUT
f
step
------------
3 MHz
100 kHz
----------------------
30
=
=
=
K
v
2f
L
2
V
CC
1.1
(
)
1.1
----------------------------------------------
1 MHz
2.8
-----------------
2
2.24
10
6
r s
/
V
/
=
=
The gain of the phase comparator
PC2 is:
Using PC2 with the passive filter as
shown in Fig.34 results in a high gain
loop with the same performance as a
loop with an active filter. Hence loop
filter equations as for a high gain loop
should be used. The current source
output of PC2 can be simulated then
with a fictive filter resistance:
The transfer functions of the filter is
given by:
Where:
1
= R3'
C2.
2
= R4
C2.
The characteristic equation is:
This results in:
or:
This can be written as:
with the natural frequency
n
defined
as:
and the
damping value given as:
In Fig.35 the output frequency
response to a step of input frequency
is shown.
The overshoot and settling time
percentages are now used to
determine
n
. From Fig.35 it can be
K
p
5
4
------------
0.4V r
/
=
=
R3'
R
b
17
-------
=
K
f
1
s
2
+
s
2
------------------
=
1
K
p
K
f
K
o
K
n
+
1
K
p
1
s
2
+
s
1
------------------
K
v
s
------ K
n
0
=
+
s
2
sK
p
K
v
K
n
2
1
-----
K
p
K
v
K
n
1
0
=
/
+
+
s
2
2
n
s
n
( )
2
+
+
0
=
n
K
p
K
v
K
n
1
--------------------------------
=
0.5
2
n
=
seen that the damping ratio
= 0.707
will produce an overshoot of less than
20% and settle to within 5% at
n
t = 5.
The required settling time is 1 ms.
This results in:
Rewriting the equation for natural
frequency results in:
The maximum overshoot occurs at
N
max
= 30; hence K
n
=
1
/
30
:
When C2 = 470 nF, it follows:
Hence the current source bias
resistance R
b
= 17
2550 = 43 k
.
With
= 0.707 (0.5
2
n
) it
follows:
For extra ripple suppression a
capacitor C3 can be connected in
parallel with R4, with an extra
3
= R4
C3.
For stability reasons
3
should be
<
0.1
2
, hence C3
<
0.1C2, or
C3 = 39 nF.
n
5
t
---
5
0.001
---------------
5
10
3
r s
/
=
=
=
1
K
p
K
v
K
n
n
( )
2
--------------------------------
=
1
0.4
2.24
10
6
5000
2
30
------------------------------------------
0.0012
=
=
R3'
1
C2
--------
0.0012
470
10
9
----------------------------
2550
=
=
=
2
0.707
0.5
5000
----------------------------
0.00028
=
=
R4
2
C2
--------
0.00028
470
10
9
----------------------------
600
=
=
=
background image
1999 Jan 11
34
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
MBD098
R4
C2
R2
R1
VCO
R3'
PHASE
COMPARATOR
PC2
DIVIDE BY 10
"190"
OSCILLATOR
"HCU04"
13
100 kHz
14
3
4
f OUT
PROGRAMMABLE
DIVIDER
"4059"
9
11
12 6
7
5
1 MHz
Kp
Kn
K f
Ko
C1
C3
(1)
R
15
b
u
Fig.34 Frequency synthesizer.
R1 = 30 k
.
R2 = 30 k
.
C1 = 100 pF.
R3
'
= 2550
.
R
b
= 43 k
.
R4 = 600
.
C2 = 470 nF.
C3 = 39 nF.
(1)
R3'
fictive resistance
=
R3'
R
b
17
-------
=
0
1
2
4
1.6
1.0
0.6
0
0.8
MGA959
3
1.4
1.2
0.4
0.2
5
6
7
8
n t
(t)
e
e
/
n
(t)
e
e
/
n
-
0.6
0
0.4
1.0
0.2
-
0.4
-
0.2
0.6
0.8
= 5.0
0.5
0.707
1.0
= 0.3
= 2.0
Fig.35 Type 2, second order frequency step response.
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1999 Jan 11
35
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
MGA952
3.1
3.0
2.9
2.1
2.0
1.9
0
0.5
1.0
1.5
2.0
2.5
time (ms)
proportional
to output
frequency
(MHz)
N = 30
N stepped from 29 to 30
step input
N stepped from 21 to 20
Fig.36 Frequency compared to the time response.
Since the output frequency is proportional to the VCO
control voltage, the PLL frequency response can be
observed with an oscilloscope by monitoring pin 9 of the
VCO. The average frequency response, as calculated by
the Laplace method, is found experimentally by smoothing
this voltage at pin 9 with a simple RC filter, whose time
constant is long compared with the phase detector
sampling rate but short compared with the PLL response
time.
Further information
For an extensive description and application example
please refer to
"Application note" ordering number
9398 649 90011. Also available a
"Computer design
program for PLLs" ordering number 9398 961 10061.
background image
1999 Jan 11
36
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
PACKAGE OUTLINES
UNIT
A
max.
1
2
b
1
c
E
e
M
H
L
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT38-1
92-10-02
95-01-19
A
min.
A
max.
b
max.
w
M
E
e
1
1.40
1.14
0.055
0.045
0.53
0.38
0.32
0.23
21.8
21.4
0.86
0.84
6.48
6.20
0.26
0.24
3.9
3.4
0.15
0.13
0.254
2.54
7.62
0.30
8.25
7.80
0.32
0.31
9.5
8.3
0.37
0.33
2.2
0.087
4.7
0.51
3.7
0.15
0.021
0.015
0.013
0.009
0.01
0.10
0.020
0.19
050G09
MO-001AE
M
H
c
(e )
1
M
E
A
L
seating plane
A
1
w
M
b
1
e
D
A
2
Z
16
1
9
8
b
E
pin 1 index
0
5
10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
(1)
(1)
D
(1)
Z
DIP16: plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
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1999 Jan 11
37
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
X
w
M
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v
M
A
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT
A
max.
A
1
A
2
A
3
b
p
c
D
(1)
E
(1)
(1)
e
H
E
L
L
p
Q
Z
y
w
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
0.7
0.6
0.7
0.3
8
0
o
o
0.25
0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
1.0
0.4
SOT109-1
95-01-23
97-05-22
076E07S
MS-012AC
0.069
0.010
0.004
0.057
0.049
0.01
0.019
0.014
0.0100
0.0075
0.39
0.38
0.16
0.15
0.050
1.05
0.041
0.244
0.228
0.028
0.020
0.028
0.012
0.01
0.25
0.01
0.004
0.039
0.016
0
2.5
5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
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1999 Jan 11
38
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
SOLDERING
Introduction
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
"Data Handbook IC26; Integrated Circuit Packages"
(document order number 9398 652 90011).
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mount components are mixed on
one printed-circuit board. However, wave soldering is not
always suitable for surface mount ICs, or for printed-circuit
boards with high population densities. In these situations
reflow soldering is often used.
Through-hole mount packages
S
OLDERING BY DIPPING OR BY SOLDER WAVE
The maximum permissible temperature of the solder is
260
C; solder at this temperature must not be in contact
with the joints for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
stg(max)
). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
M
ANUAL SOLDERING
Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300
C it may remain in contact for up to
10 seconds. If the bit temperature is between
300 and 400
C, contact may be up to 5 seconds.
Surface mount packages
R
EFLOW SOLDERING
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical reflow peak temperatures range from
215 to 250
C. The top-surface temperature of the
packages should preferable be kept below 230
C.
W
AVE SOLDERING
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
For packages with leads on two sides and a pitch (e):
larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
For packages with leads on four sides, the footprint must
be placed at a 45
angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250
C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
M
ANUAL SOLDERING
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300
C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320
C.
background image
1999 Jan 11
39
Philips Semiconductors
Product specification
PLL with bandgap controlled VCO
74HCT9046A
Suitability of IC packages for wave, reflow and dipping soldering methods
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".
2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
4. If wave soldering is considered, then the package must be placed at a 45
angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
MOUNTING
PACKAGE
SOLDERING METHOD
WAVE
REFLOW
(1)
DIPPING
Through-hole mount DBS, DIP, HDIP, SDIP, SIL
suitable
(2)
-
suitable
Surface mount
BGA, SQFP
not suitable
suitable
-
HLQFP, HSQFP, HSOP, HTSSOP, SMS
not suitable
(3)
suitable
-
PLCC
(4)
, SO, SOJ
suitable
suitable
-
LQFP, QFP, TQFP
not recommended
(4)(5)
suitable
-
SSOP, TSSOP, VSO
not recommended
(6)
suitable
-
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
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Internet: http://www.semiconductors.philips.com
Philips Semiconductors a worldwide company
Philips Electronics N.V. 1999
SCA61
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
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Portugal: see Spain
Romania: see Italy
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Slovakia: see Austria
Slovenia: see Italy
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Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
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Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
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Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
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Colombia: see South America
Czech Republic: see Austria
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Finland: Sinikalliontie 3, FIN-02630 ESPOO,
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Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
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Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
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Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Printed in The Netherlands
245002/00/03/pp40
Date of release: 1999 Jan 11
Document order number:
9397 750 05007
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