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Datasheet: OX12PCI840 (Oxford Micro Devices, Inc.)

Integrated Parallel Port and Pci Interface.

 

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Oxford Semiconductor Ltd.
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK
Tel: +44 (0)1235 824900
Fax: +44(0)1235 821141
Oxford Semiconductor 1999
OX12PCI840 1.2 Dec 2001
Part No. OX12PCI840-PQC-A
F
EATURE
IEEE1284 SPP/EPP/ECP parallel port
Single function target PCI controller, fully PCI 2.2 and
PCI Power Management 1.0 compliant
2 multi-purpose IO pins which can be configured as
interrupt input pins
Can be reconfigured using optional non-volatile
configuration memory (EEPROM)
5.0V operation
100 pin PQFP package
D
ESCRIPTION
The OX12PCI840 is a single chip solution for PCI-based
parallel expansion add-in cards. It is a single function PCI
device.
For legacy applications the PCI resources are arranged so
that the parallel port can be located at standard I/O
addresses.
The efficient 32-bit, 33MHz target-only PCI interface is
compliant with version 2.2 of the PCI Bus Specification and
version 1.0 of PCI Power Management Specification. For
full flexibility, all the default register values can be
overwritten using an optional Microwire
TM
serial EEPROM.
The OX12PCI840 provides an IEEE1284 EPP/ECP parallel
port which fully supports the existing Centronics interface.
OX12PCI840
Integrated Parallel Port
and PCI interface
Data Sheet Revision 1.2
Page 2
OX12PCI840
OXFORD SEMICONDUCTOR LTD.
C
ONTENTS
1 PIN INFORMATION .....................................................................................................................4
2 PIN DESCRIPTIONS ....................................................................................................................5
3 CONFIGURATION & OPERATION ...............................................................................................8
4 PCI TARGET CONTROLLER .......................................................................................................9
4.1
OPERATION.......................................................................................................................................................................... 9
4.2
CONFIGURATION SPACE................................................................................................................................................... 9
4.2.1
PCI CONFIGURATION SPACE REGISTER MAP ......................................................................................................... 10
4.3
ACCESSING LOGICAL FUNCTIONS................................................................................................................................ 11
4.3.1
PCI ACCESS TO PARALLEL PORT .............................................................................................................................. 11
4.4
ACCESSING LOCAL CONFIGURATION REGISTERS .................................................................................................... 12
4.4.1
LOCAL CONFIGURATION AND CONTROL REGISTER `LCC' (OFFSET 0X00) ......................................................... 12
4.4.2
MULTI-PURPOSE I/O CONFIGURATION REGISTER `MIC' (OFFSET 0X04)............................................................. 13
4.4.3
LOCAL BUS TIMING PAR AMETER REGISTER 1 `LT1' (OFFSET 0X08): ................................................................... 13
4.4.4
LOCAL BUS TIMING PAR AMETER/BAR SIZING REGISTER 2 `LT2' (OFFSET 0X0C):............................................. 14
4.4.5
GLOBAL INTERRUPT STATUS AND CONTROL REGISTER `GIS' (OFFSET 0X10)................................................. 15
4.5
PCI INTERRUPTS ............................................................................................................................................................... 16
4.6
POWER MANAGEMENT.................................................................................................................................................... 17
4.6.1
POWER MANAGEMENT USING MIO............................................................................................................................ 17
5 BI-DIRECTIONAL PARALLEL PORT..........................................................................................18
5.1
OPERATION AND MODE SELECTION............................................................................................................................. 18
5.1.1
SPP MODE ...................................................................................................................................................................... 18
5.1.2
PS2 MODE ...................................................................................................................................................................... 18
5.1.3
EPP MODE ...................................................................................................................................................................... 18
5.1.4
ECP MODE...................................................................................................................................................................... 18
5.2
PARALLEL PORT INTERRUPT ......................................................................................................................................... 18
5.3
REGISTER DESCRIPTION................................................................................................................................................. 19
5.3.1
PARALLEL PORT DATA REGISTER `PDR'................................................................................................................... 19
5.3.2
ECP FIFO ADDRESS / RLE ........................................................................................................................................... 19
5.3.3
DEVICE STATUS REGISTER `DSR'.............................................................................................................................. 19
5.3.4
DEVICE CONTROL REGISTER `DCR' .......................................................................................................................... 20
5.3.5
EPP ADDRESS REGISTER `EPPA' ............................................................................................................................... 20
5.3.6
EPP DATA REGISTERS `EPPD1-4' ............................................................................................................................... 20
5.3.7
ECP DATA FIFO............................................................................................................................................................. 20
5.3.8
TEST FIFO...................................................................................................................................................................... 20
5.3.9
CONFIGURATION A REGISTER ................................................................................................................................... 20
5.3.10
CONFIGURATION B REGISTER ................................................................................................................................... 21
5.3.11
EXTENDED CONTROL REGISTER `ECR' .................................................................................................................... 21
6 SERIAL EEPROM...................................................................................................................... 22
6.1
SPECIFICATION ................................................................................................................................................................. 22
6.2
EEPROM DATA ORGANISATION ..................................................................................................................................... 22
6.2.1
ZONE0: HEADER............................................................................................................................................................ 22
6.2.2
ZONE1: LOCAL CONFIGURATION REGISTERS ......................................................................................................... 23
6.2.3
ZONE2: IDENTIFICATION REGISTERS........................................................................................................................ 23
6.2.4
ZONE3: PCI CONFIGURATION REGISTERS ............................................................................................................... 23
6.2.5
ZONE4: FUNCTION ACCESS........................................................................................................................................ 25
7 OPERATING CONDITIONS ........................................................................................................26
Data Sheet Revision 1.2
Page 3
OX12PCI840
OXFORD SEMICONDUCTOR LTD.
8 DC ELECTRICAL CHARACTERISTICS ...................................................................................... 26
8.1
NON-PCI I/O BUFFERS ...................................................................................................................................................... 26
8.2
PCI I/O BUFFERS ............................................................................................................................................................... 27
9 AC ELECTRICAL CHARACTERISTICS ...................................................................................... 28
9.1
PCI BUS............................................................................................................................................................................... 28
10
TIMING WAVEFORMS............................................................................................................29
11
PACKAGE DETAILS .............................................................................................................. 30
12
NOTES..................................................................................................................................31
13
CONTACT DETAILS...............................................................................................................32
Data Sheet Revision 1.2
Page 4
OX12PCI840
OXFORD SEMICONDUCTOR LTD.
1 P
IN
I
NFORMATION
100 pin QFP
EE_DI
EE_DO
EE_CS
TEST
STB
AFD#
INIT#
SLIN#
GND ac
ACK#
NC
PD_EN
ERR#
VDD dc
GND dc
SLCT
BUSY
PE
PD0
GND ac
PD1
PD2
PD3
PD4
VDD ac
GND ac
PD5
PD6
PD7
MIO0
80
75
70
65
60
55
51
EE_SK
81
50
AD0
MIO1
AD1
Z_INTA
GND ac
Z_RESET
AD2
GND dc
85
AD3
PCI_CLK
45
VDD dc
VDD dc
GND dc
Z_PME
AD4
AD31
AD5
AD30
90
GND ac
AD29
40
VDD ac
GND ac
AD6
AD28
AD7
AD27
Z_CBE0
AD26
95
AD8
GND ac
35
GND ac
VDD ac
AD9
AD25
AD10
AD24
AD11
Z_CBE3
100
31
AD12
1
5
10
15
20
25
30
IDSEL
AD23
GND ac
AD22
AD21
AD20
GND ac
VDD ac
AD19
AD18
AD17
AD16
Z_CBE2
Z_FRAME
GND dc
VDD dc
Z_IRDY
Z_TRDY
Z_DEVSEL
GND ac
Z_STOP
Z_PERR
Z_SERR
PAR
Z_CBE1
AD15
AD14
AD13
GND ac
VDD ac
Data Sheet Revision 1.2
Page 5
OX12PCI840
OXFORD SEMICONDUCTOR LTD.
2 P
IN
D
ESCRIPTIONS
Pin Numbers
Dir
1
Name
Description
PCI interface
89,90,91,93,94,95,98,99,2,4,5,6,9,
10,11,12,26,27,28,31,32,33,34,36,
38,39,42,43,46,47,49,50
P_I/O AD[31:0]
Multiplexed PCI Address/Data bus
100,13,25,37
P_I
C/BE[3:0]#
PCI Command/Byte enable
86
P_I
CLK
PCI system clock
14
P_I
FRAME#
Cycle Frame
19
P_O
DEVSEL#
Device Select
17
P_I
IRDY#
Initiator ready
18
P_O
TRDY#
Target ready
21
P_O
STOP#
Target Stop request
24
P_I/O PAR
Parity
23
P_O
SERR#
System error
22
P_I/O PERR#
Parity error
1
P_I
IDSEL
Initialisation device select
84
P_I
RST#
PCI system reset
83
P_OD INTA#
PCI interrupt
88
P_OD PME#
Power management event
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