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Datasheet: 100331F (National Semiconductor)

Low Power Triple D Flip-Flop

 

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National Semiconductor
100331
Low Power Triple D Flip-Flop
General Description
The 100331 contains three D-type, edge-triggered master/
slave flip-flops with true and complement outputs, a Com-
mon Clock (CP
C
), and Master Set (MS) and Master Reset
(MR) inputs. Each flip-flop has individual Clock (CP
n
), Direct
Set (SD
n
) and Direct Clear (CD
n
) inputs. Data enters a mas-
ter when both CP
n
and CP
C
are LOW and transfers to a
slave when CP
n
or CP
C
(or both) go HIGH. The Master Set,
Master Reset and individual CD
n
and SD
n
inputs override
the Clock inputs. All inputs have 50 k
pull-down resistors.
Features
n
35% power reduction of the 100131
n
2000V ESD protection
n
Pin/function compatible with 100131
n
Voltage compensated operating range = -4.2V to -5.7V
n
Available to industrial grade temperature range
n
Available to Standard Microcircuit Drawing (SMD)
5962-9153601
Logic Symbol
Pin Names
Description
CP
0
CP
2
Individual Clock Inputs
CP
C
Common Clock Input
D
0
D
2
Data Inputs
CD
0
CD
2
Individual Direct Clear Inputs
SD
n
Individual Direct Set Inputs
MR
Master Reset Input
MS
Master Set Input
Q
0
-Q
2
Data Outputs
Q
0
Q
2
Complementary Data Outputs
Connection Diagrams
DS100300-1
24-Pin DIP
DS100300-2
24-Pin Quad Cerpak
DS100300-3
August 1998
100331
Low
Power
T
riple
D
Flip-Flop
1998 National Semiconductor Corporation
DS100300
www.national.com
Logic Diagram
Truth Tables
Synchronous Operation
(Each Flip-Flop)
Inputs
Outputs
D
n
CP
n
CP
C
MS
MR
Q
n
(t + 1)
SD
n
CD
n
L
N
L
L
L
L
H
N
L
L
L
H
L
L
N
L
L
L
H
L
N
L
L
H
X
L
L
L
L
Qn(t)
X
H
X
L
L
Qn(t)
X
X
H
L
L
Qn(t)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
U = Undefined
t = Time before CP Positive Transition
t + 1 = Time after CP Positive Transition
N
= LOW to HIGH Transition
Asynchronous Operation
(Each Flip-Flop)
Inputs
Outputs
D
n
CP
n
CP
C
MS
MR
Q
n
(t + 1)
SD
n
CD
n
X
X
X
H
L
H
X
X
X
L
H
L
X
X
X
H
H
U
DS100300-5
www.national.com
2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Above which the useful life may be impaired
Storage Temperature (T
STG
)
-65C to +150C
Maximum Junction Temperature (T
J
)
Ceramic
+175C
Pin Potential to
Ground Pin (V
EE
)
-7.0V to +0.5V
Input Voltage (DC)
V
EE
to +0.5V
Output Current
(DC Output HIGH)
-50 mA
ESD (Note 2)
2000V
Recommended Operating
Conditions
Case Temperature (T
C
)
Military
-55C to +125C
Supply Voltage (V
EE
)
-5.7V to -4.2V
Note 1: Absolute maximum ratings are those values beyond which the de-
vice may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version
DC Electrical Characteristics
V
EE
= -4.2V to -5.7V, V
CC
= V
CCA
= GND, T
C
= -55C to +125C
Symbol
Parameter
Min
Max
Units
T
C
Conditions
Notes
V
OH
Output HIGH Voltage
-1025
-870
mV
0C to
V
IN
= V
IH
(Max)
or V
IL
(Min)
Loading with
50
to -2.0V
(Notes 3,
4, 5)
+125C
-1085
-870
mV
-55C
V
OL
Output LOW Voltage
-1830
-1620
mV
0C to
+125C
-1830
-1555
mV
-55C
V
OHC
Output HIGH Voltage
-1035
mV
0C to
V
IN
= V
IH
(Min)
or V
IL
(Max)
Loading with
50
to -2.0V
(Notes 3,
4, 5)
+125C
-1085
mV
-55C
V
OLC
Output LOW Voltage
-1610
mV
0C to
+125C
-1555
mV
-55C
V
IH
Input HIGH Voltage
-1165
-870
mV
-55C to
Guaranteed HIGH Signal
(Notes 3,
4, 5, 6)
+125C
for all Inputs
V
IL
Input LOW Voltage
-1830
-1475
mV
-55C to
Guaranteed LOW Signal
(Notes 3,
4, 5, 6)
+125C
for all Inputs
I
IL
Input LOW Current
0.50
A
-55C to
V
EE
= -4.2V
(Notes 3,
4, 5)
+125C
V
IN
= V
IL
(Min)
I
IH
Input HIGH Current
240
A
0C to
V
EE
= -5.7V
V
IN
= V
IH
(Max)
(Notes 3,
4, 5)
+125C
340
A
-55C
I
EE
Power Supply Current
-130
-50
mA
-55C to
Inputs Open
(Notes 3,
4, 5)
+125C
Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides "cold start" specs which can be considered a worst case
condition at cold temperatures.
Note 4: Screen tested 100% on each device at -55C, +25C, and +125C, Subgroups, 1, 2, 3, 7 and 8.
Note 5: Sampled tested (Method 5005, Table I) on each manufactured lot at -55C, +25C, and +125C, Subgroups A1, 2, 3, 7 and 8.
Note 6: Guaranteed by applying specified input condition and testing V
OH
/V
OL
.
www.national.com
3
AC Electrical Characteristics
V
EE
= -4.2V to -5.7V, V
CC
= V
CCA
= GND
Symbol
Parameter
T
C
= -55C
T
C
= +25C
T
C
= +125C
Units
Conditions
Notes
Min
Max
Min
Max
Min
Max
f
max
Toggle Frequency
400
400
400
MHz
Figures 2, 3
(Note
10)
t
PLH
Propagation Delay
0.50
2.20
0.60
2.00
0.50
2.40
ns
t
PHL
CP
C
to Output
Figures 1, 3
t
PLH
Propagation Delay
0.50
2.20
0.60
2.00
0.50
2.40
ns
t
PHL
CP
n
to Output
t
PLH
Propagation Delay
0.50
2.20
0.60
2.00
0.50
2.40
CP
n
, CP
C
= L
Figures
1, 4
(Notes
7, 8,
9)
t
PHL
CD
n
, SD
n
to Output
ns
t
PLH
0.50
2.40
0.60
2.10
0.50
2.50
CP
n
, CP
C
= H
t
PHL
t
PLH
Propagation Delay
0.70
2.70
0.80
2.60
0.80
2.90
CP
n
, CP
C
= L
t
PHL
MS, MR to Output
ns
t
PLH
0.70
2.90
0.80
2.80
0.80
3.10
CP
n
, CP
C
= H
t
PHL
t
TLH
Transition Time
0.20
1.40
0.20
1.40
0.20
1.40
ns
Figures 1, 3, 4
t
THL
20% to 80%, 80% to 20%
t
s
Setup Time
Figure 5
(Note
10)
D
n
1.00
0.80
0.90
CD
n
, SD
n
(Release Time)
1.50
1.30
1.60
ns
Figure 4
MS, MR (Release Time)
2.50
2.30
2.50
t
h
Hold Time D
n
1.50
1.30
1.60
ns
Figure 5
t
pw
(H)
Pulse Width HIGH
CP
n
, CP
C
, CD
n
,
2.00
2.00
2.00
ns
Figures 3, 4
SD
n
, MR, MS
Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides "cold start" specs which can be considered a worst case
condition at cold temperatures.
Note 8: Screen tested 100% on each device at +25C. Temperature only, Subgroup A9.
Note 9: Sample tested (Method 5005, Table I) on each Mfg. lot at +25C, Subgroup A9, and at +125C, and -55C Temp., Subgroups A10 and A11.
Note 10: Not tested at +25C, +125C and -55C Temperature (design characterization data).
www.national.com
4
Test Circuits
DS100300-6
FIGURE 1. AC Test Circuit
DS100300-7
Notes:
V
CC
, V
CCA
= +2V, V
EE
= -2.5V
L1 and L2 = Equal length 50
impedance lines
R
T
= 50
terminator internal to scope
Decoupling 0.1 F from GND to V
CC
and V
EE
All unused outputs are loaded with 50
to GND
C
L
= Fixture and stray capacitance
3 pF
FIGURE 2. Toggle Frequency Test Circuit
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5
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