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Datasheet: M16379EJ1V0DS00 (NEC)

 

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32M-BIT CMOS SYNCHRONOUS FAST STATIC RAM
2M-WORD BY 18-BIT / 1M-WORD BY 36-BIT
HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
©
2002
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µ
µ
µ
µ
PD44323182, 44323362
Document No. M16379EJ2V0DS00 (2nd edition)
Date Published September 2002 NS CP(K)
Printed in Japan
The mark
# shows major revised points.
Description
The
µPD44323182 is a 2,097,152 words by 18 bits, and the µPD44323362 is a 1,048,576 words by 36 bits
synchronous static RAM fabricated with advanced CMOS technology using Full-CMOS six-transistor memory cell.
The
µPD44323182 and µPD44323362 are suitable for applications which require high-speed, low voltage, high-
density memory and wide bit configuration, such as cache and buffer memory.
The
µPD44323182 and µPD44323362 are packaged in a 119-pin PLASTIC BGA (Ball Grid Array).
Features
· Fully synchronous operation
· HSTL Input / Output levels
· Fast clock access time: 2.0 ns / 250 MHz, 2.5ns / 200 MHz
· Asynchronous output enable control: /G
· Byte write control: /SBa (DQa1 to DQa9), /SBb (DQb1 to DQb9), /SBc (DQc1 to DQc9), /SBd (DQd1 to DQd9)
· Common I/O using three-state outputs
· Internally self-timed write cycle
· Late write with 1 dead cycle between Read-Write
· User-configurable outputs: Controlled impedance outputs or push-pull outputs
· Boundary scan (JTAG) IEEE 1149.1 compatible
· 2.5 ± 0.125 V (Chip) / 1.4 to 1.9 V (I/O) supply
· 119 bump BGA package, 1.27 mm pitch, 14 mm × 22 mm
· Sleep mode: ZZ (Enables sleep mode, active high)
Ordering Information
Part number
Access time
Clock frequency
Package
µPD44323182F1-C40-FJ1
2.0 ns
250 MHz
119-pin PLASTIC BGA
µPD44323182F1-C50-FJ1
2.5 ns
200 MHz
µPD44323362F1-C40-FJ1
2.0 ns
250 MHz
µPD44323362F1-C50-FJ1
2.5 ns
200 MHz
2
Preliminary Data Sheet M16379EJ2V0DS
µ
µ
µ
µPD44323182, 44323362
Pin Configurations
/xxx indicates active low signal.
119-pin PLASTIC BGA (2M Words by 18 Bits Pin Assignment)
[
µ
µ
µ
µPD44323182F1]
1
2
3
4
4
5
6
7
1 2 3 4 5 6 7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
Top View
Bottom View
1
2
3
4
5
6
7
7
6
5
4
3
2
1
V
DD
Q
SA12
SA9
NC
SA6
SA2
V
DD
Q
A
V
DD
Q
SA2
SA6
NC
SA9
SA12
V
DD
Q
NC
SA19
SA17
SA20
SA16
SA18
NC
B
NC
SA18
SA16
SA20
SA17
SA19
NC
NC
SA13
SA10
V
DD
SA7
SA3
NC
C
NC
SA3
SA7
V
DD
SA10
SA13
NC
DQb1
NC
V
SS
ZQ
V
SS
DQa9
NC
D
NC
DQa9
V
SS
ZQ
V
SS
NC
DQb1
NC
DQb2
V
SS
/SS
V
SS
NC
DQa8
E
DQa8
NC
V
SS
/SS
V
SS
DQb2
NC
V
DD
Q
NC
V
SS
/G
V
SS
DQa7
V
DD
Q
F
V
DD
Q
DQa7
V
SS
/G
V
SS
NC
V
DD
Q
NC
DQb3
/SBb
NC
NC
NC
DQa6
G
DQa6
NC
NC
NC
/SBb
DQb3
NC
DQb4
NC
V
SS
NC
V
SS
DQa5
NC
H
NC
DQa5
V
SS
NC
V
SS
NC
DQb4
V
DD
Q
V
DD
V
REF
V
DD
V
REF
V
DD
V
DD
Q
J
V
DD
Q
V
DD
V
REF
V
DD
V
REF
V
DD
V
DD
Q
NC
DQb5
V
SS
K
V
SS
NC
DQa4
K
DQa4
NC
V
SS
K
V
SS
DQb5
NC
DQb6
NC
NC
/K
/SBa
DQa3
NC
L
NC
DQa3
/SBa
/K
NC
NC
DQb6
V
DD
Q
DQb7
V
SS
/SW
V
SS
NC
V
DD
Q
M
V
DD
Q
NC
V
SS
/SW
V
SS
DQb7
V
DD
Q
DQb8
NC
V
SS
SA0
V
SS
DQa2
NC
N
NC
DQa2
V
SS
SA0
V
SS
NC
DQb8
NC
DQb9
V
SS
SA1
V
SS
NC
DQa1
P
DQa1
NC
V
SS
SA1
V
SS
DQb9
NC
NC
SA14
M1
V
DD
M2
SA4
NC
R
NC
SA4
M2
V
DD
M1
SA14
NC
NC
SA15
SA11
NC
SA8
SA5
ZZ
T
ZZ
SA5
SA8
NC
SA11
SA15
NC
V
DD
Q
TMS
TDI
TCK
TDO
NC
V
DD
Q
U
V
DD
Q
NC
TDO
TCK
TDI
TMS
V
DD
Q
3
Preliminary Data Sheet M16379EJ2V0DS
µ
µ
µ
µPD44323182, 44323362
Pin Name and Functions [
µ
µ
µ
µPD44323182F1]
Pin name
Description
Function
V
DD
Core Power Supply
Supplies power for RAM core
V
SS
Ground
V
DD
Q
Output Power Supply
Supplies power for output buffers
V
REF
Input Reference
K, /K
Main Clock
SA0 to SA20
Synchronous Address Input
DQa1 to DQb9
Synchronous Data Input / Output
/SS
Synchronous Chip Select
Logically selects SRAM
/SW
Synchronous Byte Write Enable
Write command
/SBa
Synchronous Byte "a" Write Enable
Write DQa1 to DQa9
/SBb
Synchronous Byte "b" Write Enable
Write DQb1 to DQb9
/G
Asynchronous Output Enable
Asynchronous input
ZZ
Asynchronous Sleep Mode
Enables sleep mode, active high
ZQ
Output Impedance Control
M1, M2
Mode Select
Selects operation mode
Note
NC
No Connection
TMS
Test Mode Select (JTAG)
TDI
Test Data Input (JTAG)
TCK
Test Clock Input (JTAG)
TDO
Test Data Output (JTAG)
Note This device only supports Single Differential Clock, R/R Mode.
(R/R stands for Registered Input / Registered Output.)
4
Preliminary Data Sheet M16379EJ2V0DS
µ
µ
µ
µPD44323182, 44323362
119-pin plastic BGA (1M Words by 36 Bits Pin Assignment)
[
µ
µ
µ
µPD44323362F1]
1
2
3
4
4
5
6
7
1 2 3 4 5 6 7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
Top View
Bottom View
1
2
3
4
5
6
7
7
6
5
4
3
2
1
V
DD
Q
SA12
SA9
NC
SA5
SA2
V
DD
Q
A
V
DD
Q
SA2
SA5
NC
SA9
SA12
V
DD
Q
NC
SA18
SA16
SA19
SA15
SA17
NC
B
NC
SA17
SA15
SA19
SA16
SA18
NC
NC
SA13
SA10
V
DD
SA6
SA3
NC
C
NC
SA3
SA6
V
DD
SA10
SA13
NC
DQc8
DQc9
V
SS
ZQ
V
SS
DQb9
DQb8
D
DQb8
DQb9
V
SS
ZQ
V
SS
DQc9
DQc8
DQc6
DQc7
V
SS
/SS
V
SS
DQb7
DQb6
E
DQb6
DQb7
V
SS
/SS
V
SS
DQc7
DQc6
V
DD
Q
DQc5
V
SS
/G
V
SS
DQb5
V
DD
Q
F
V
DD
Q
DQb5
V
SS
/G
V
SS
DQc5
V
DD
Q
DQc3
DQc4
/SBc
NC
/SBb
DQb4
DQb3
G
DQb3
DQb4
/SBb
NC
/SBc
DQc4
DQc3
DQc1
DQc2
V
SS
NC
V
SS
DQb2
DQb1
H
DQb1
DQb2
V
SS
NC
V
SS
DQc2
DQc1
V
DD
Q
V
DD
V
REF
V
DD
V
REF
V
DD
V
DD
Q
J
V
DD
Q
V
DD
V
REF
V
DD
V
REF
V
DD
V
DD
Q
DQd1
DQd2
V
SS
K
V
SS
DQa2
DQa1
K
DQa1
DQa2
V
SS
K
V
SS
DQd2
DQd1
DQd3
DQd4
/SBd
/K
/SBa
DQa4
DQa3
L
DQa3
DQa4
/SBa
/K
/SBd
DQd4
DQd3
V
DD
Q
DQd5
V
SS
/SW
V
SS
DQa5
V
DD
Q
M
V
DD
Q
DQa5
V
SS
/SW
V
SS
DQd5
V
DD
Q
DQd6
DQd7
V
SS
SA0
V
SS
DQa7
DQa6
N
DQa6
DQa7
V
SS
SA0
V
SS
DQd7
DQd6
DQd8
DQd9
V
SS
SA1
V
SS
DQa9
DQa8
P
DQa8
DQa9
V
SS
SA1
V
SS
DQd9
DQd8
NC
SA14
M1
V
DD
M2
SA4
NC
R
NC
SA4
M2
V
DD
M1
SA14
NC
NC
NC
SA11
SA8
SA7
NC
ZZ
T
ZZ
NC
SA7
SA8
SA11
NC
NC
V
DD
Q
TMS
TDI
TCK
TDO
NC
V
DD
Q
U
V
DD
Q
NC
TDO
TCK
TDI
TMS
V
DD
Q
5
Preliminary Data Sheet M16379EJ2V0DS
µ
µ
µ
µPD44323182, 44323362
Pin Name and Functions [
µ
µ
µ
µPD44323362F1]
Pin name
Description
Function
V
DD
Core Power Supply
Supplies power for RAM core
V
SS
Ground
V
DD
Q
Output Power Supply
Supplies power for output buffers
V
REF
Input Reference
K, /K
Main Clock
SA0 to SA19
Synchronous Address Input
DQa1 to DQd9
Synchronous Data Input / Output
/SS
Synchronous Chip Select
Logically selects SRAM
/SW
Synchronous Byte Write Enable
Write command
/SBa
Synchronous Byte "a" Write Enable
Write DQa1 to DQa9
/SBb
Synchronous Byte "b" Write Enable
Write DQb1 to DQb9
/SBc
Synchronous Byte "c" Write Enable
Write DQc1 to DQc9
/SBd
Synchronous Byte "d" Write Enable
Write DQd1 to DQd9
/G
Asynchronous Output Enable
Asynchronous input
ZZ
Asynchronous Sleep Mode
Enables sleep mode, active high
ZQ
Output Impedance Control
M1, M2
Mode Select
Selects operation mode
Note
NC
No Connection
TMS
Test Mode Select (JTAG)
TDI
Test Data Input (JTAG)
TCK
Test Clock Input (JTAG)
TDO
Test Data Output (JTAG)
Note This device only supports Single Differential Clock, R/R Mode.
(R/R stands for Registered Input / Registered Output.)
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