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Datasheet: M16065EJ3V0DS00 (NEC)

 

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MOS INTEGRATED CIRCUIT



PD23C64040JL, 23C64080JL
64M-BIT MASK-PROGRAMMABLE ROM
8M-WORD BY 8-BIT (BYTE MODE) / 4M-WORD BY 16-BIT (WORD MODE)
PAGE ACCESS MODE
DATA SHEET
Document No. M16065EJ3V0DS00 (3rd edition)
Date Published February 2003 NS CP (K)
Printed in Japan
The mark shows major revised points.
2002
Description
The
PD23C64040JL, 23C64080JL are a 67,108,864 bits mask-programmable ROM. The word organization is
selectable (BYTE mode : 8,388,608 words by 8 bits, WORD mode : 4,194,304 words by 16 bits).
The active levels of OE (Output Enable Input) can be selected with mask-option.
The
PD23C64040JL, 23C64080JL are packed in 48-pin PLASTIC TSOP (I) and 44-pin PLASTIC SOP.
Features
Word organization
8,388,608 words by 8 bits (BYTE mode)
4,194,304 words by 16 bits (WORD mode)
Page access mode
BYTE mode : 8 byte random page access (
PD23C64040JL)
: 16 byte random page access (
PD23C64080JL)
WORD mode : 4 word random page access (
PD23C64040JL)
: 8 word random page access (
PD23C64080JL)
Operating supply voltage : V
CC
= 2.7 to 3.6 V
Operating
Package
Access time /
Power supply current (Active mode)
Standby current
supply voltage
Page access time
mA (MAX.)
(CMOS level input)
V
CC
ns (MAX.)
PD23C64040JL
PD23C64080JL
A (MAX.)
3.0 V
0.3 V
TSOP (I)
100 / 25
40
60
30
SOP
120 / 25
35
50
3.3 V
0.3 V
TSOP (I)
90 / 25
55
75
SOP
100 / 25
50
65
Remark The access time and power supply current vary depending on the package type.
Data Sheet M16065EJ3V0DS
2
PD23C64040JL, 23C64080JL
Ordering Information
Part number
Package
PD23C64040JLGY-xxx-MJH
PD23C64040JLGY-xxx-MKH
PD23C64040JLGX-xxx
PD23C64080JLGY-xxx-MJH
PD23C64080JLGY-xxx-MKH
PD23C64080JLGX-xxx
48-pin PLASTIC TSOP (I) (12
18) (Normal bent)
48-pin PLASTIC TSOP (I) (12
18) (Reverse bent)
44-pin PLASTIC SOP (15.24 mm (600))
48-pin PLASTIC TSOP (I) (12
18) (Normal bent)
48-pin PLASTIC TSOP (I) (12
18) (Reverse bent)
44-pin PLASTIC SOP (15.24 mm (600))
(xxx : ROM code suffix No.)
Data Sheet M16065EJ3V0DS
3
PD23C64040JL, 23C64080JL
Pin Configurations
/xxx indicates active low signal.
48-pin PLASTIC TSOP (I) (12



18) (Normal bent)
[



PD23C64040JLGY-xxx-MJH ]
[



PD23C64080JLGY-xxx-MJH ]
Marking Side
WORD, /BYTE
A16
A15
A14
A13
A12
A11
A10
A9
A8
A19
A21
A20
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
/CE
GND
GND
O15, A
-1
O7
O14
O6
O13
O5
O12
O4
V
CC
V
CC
NC
O11
O3
O10
O2
O9
O1
O8
O0
/OE or OE or DC
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A0 to A21
: Address inputs
O0 to O7, O8 to O14 : Data outputs
O15, A
-1
: Data output 15 (WORD mode),
LSB Address input (BYTE mode)
WORD, /BYTE
: Mode select input
/CE
: Chip Enable input
/OE or OE
: Output Enable input
V
CC
: Supply voltage
GND
: Ground
NC
Note
: No Connection
DC
: Don't Care
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M16065EJ3V0DS
4
PD23C64040JL, 23C64080JL
48-pin PLASTIC TSOP (I) (12



18) (Reverse bent)
[



PD23C64040JLGY-xxx-MKH ]
[



PD23C64080JLGY-xxx-MKH ]
Marking Side
WORD, /BYTE
A16
A15
A14
A13
A12
A11
A10
A9
A8
A19
A21
A20
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
/CE
GND
GND
O15, A
-1
O7
O14
O6
O13
O5
O12
O4
V
CC
V
CC
NC
O11
O3
O10
O2
O9
O1
O8
O0
/OE or OE or DC
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A0 to A21
: Address inputs
O0 to O7, O8 to O14 : Data outputs
O15, A
-1
: Data output 15 (WORD mode),
LSB Address input (BYTE mode)
WORD, /BYTE
: Mode select input
/CE
: Chip Enable input
/OE or OE
: Output Enable input
V
CC
: Supply voltage
GND
: Ground
NC
Note
: No Connection
DC
: Don't Care
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M16065EJ3V0DS
5
PD23C64040JL, 23C64080JL
44-pin PLASTIC SOP (15.24 mm (600))
[



PD23C64040JLGX-xxx ]
[



PD23C64080JLGX-xxx ]
Marking
Side
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A21
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
/CE
GND
/OE or OE or DC
O0
O8
O1
O9
O2
O10
O3
O11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A20
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
WORD, /BYTE
GND
O15, A
-1
O7
O14
O6
O13
O5
O12
O4
V
CC
A0 to A21
: Address inputs
O0 to O7, O8 to O14 : Data outputs
O15, A
-1
: Data output 15 (WORD mode),
LSB Address input (BYTE mode)
WORD, /BYTE
: Mode select input
/CE
: Chip Enable input
/OE or OE
: Output Enable input
V
CC
: Supply voltage
GND
: Ground
DC
: Don't Care
Remark Refer to Package Drawings for the 1-pin index mark.
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