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Datasheet: M16062EJ2V0DS00 (NEC)

 

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2002
MOS INTEGRATED CIRCUIT



PD29F064115-X
64M-BIT CMOS LOW-VOLTAGE DUAL OPERATION FLASH MEMORY
4M-WORD BY 16-BIT (WORD MODE)
PAGE MODE
DATA SHEET
Document No. M16062EJ2V0DS00 (2nd edition)
Date Published September 2002 NS CP (K)
Printed in Japan
The mark
#
#
#
# shows major revised points.
Description
The
PD29F064115-X is a flash memory organized of 67,108,864 bits and 142 sectors. Sectors of this memory can
be erased at a low voltage (1.65 to 1.95 V, 1.8 to 2.1 V ) supplied from a power source, or the contents of the entire
chip can be erased. Memory organization is 4,194,304 words
16 bits, so that the memory can be programmed in
word units.
PD29F064115-X can be read high speed with page mode.
The
PD29F064115-X can be read while its contents are being erased or programmed. The memory cell is divided
into four banks. While sectors in any bank are being erased or programmed, data can be read from the other three
banks thanks to the simultaneous execution architecture. The banks are 8M bits, 24M bits, 24M bits and 8M bits.
Input /output voltage is supplied to 2.7 to 3.3 V.
Because the
PD29F064115-X enables the boot sector to be erased, it is ideal for storing a boot program. In
addition, program code that controls the flash memory can be also stored, and the program code can be programmed
or erased without the need to load it into RAM. 16 small sectors for storing parameters are provided, each of which
can be erased in 4K words units.
Once a program or erase command sequence has been executed, an automatic program or automatic erase
function internally executes program or erase and verification automatically. The programming time is about 0.5
seconds per sector. The erase time is less than 1 second per sector.
Because the
PD29F064115-X can be electrically erased or programmed by writing an instruction, data can be
reprogrammed on-board after the flash memory has been installed in a system, making it suitable for a wide range of
applications.
This flash memory is packed in 48-pin PLASTIC TSOP (I), 63-pin TAPE FBGA and 85-pin TAPE FBGA.
Features
Four bank organization enabling simultaneous execution of program / erase and read
High-speed read with page mode
Bank organization : 4 banks (8M bits + 24M bits + 24M bits + 8M bits)
Memory organization : 4,194,304 words 16 bits
Sector organization : 142 sectors (4K words 16 sectors, 32K words 126 sectors)
The boot sector is located at the highest address (sector) and the lowest address (sector)
3-state output
Automatic program
Program suspend / resume
Unlock bypass program
Automatic erase
Chip erase
Sector erase (sectors can be combined freely)
Erase suspend / resume
Program / Erase completion detection
Detection through data polling and toggle bits
Detection through RY (/BY) pin
Data Sheet M16062EJ2V0DS
2



PD29F064115-X
Sector group protection
Any sector group can be protected
Any protected sector group can be temporary unprotected
Any sector group can be unprotected
Sectors can be used for boot application
Hardware reset and standby using /RESET pin
Automatic sleep mode
Boot block sector protect by /WP (ACC) pin
Extra One Time Protect Sector provided
PD29F064115
Access time
Operating supply voltage V
Power supply current (MAX.)
ns (MAX.)
Chip
I/O
At active mA
At standby
A
V
CC
V
CC
Q
Read
Program / Erase
-DB80X, -DB85X
80, 85
1.95
0.15
3.0
0.3
20
35
25
-EB80X
Note
, -EB85X, -EB90X
80
Note
, 85, 90
1.8
0.15
15
25
Note Under Development
Program / erase time
Program : 11.0
s / word (TYP.)
Sector erase :
Program / erase cycle : 100,000 cycle
0.15 s (TYP.) (4K words sector), 0.5 s (TYP.) (32K words sector)
Program / erase cycle : 300,000 cycle
0.5 s (TYP.) (4K words sector), 0.7 s (TYP.) (32K words sector)
Program / erase cycle : 300,000 cycle (MIN.)
Ordering Information
Part number
Access time Operating supply voltage V
Operating
Package
ns (MAX.)
Chip
I/O
temperature
V
CC
V
CC
Q
C
PD29F064115GZ-DB80X-MJH
80
1.95
0.15
3.0
0.3
-25 to +85 48-pin PLASTIC TSOP (I) (12 20)
PD29F064115GZ-DB85X-MJH
85
(Normal bent)
PD29F064115F9-DB80X-CD6
80
63-pin TAPE FBGA (11
8)
PD29F064115F9-DB85X-CD6
85
PD29F064115F9-DB80X-CD5
80
85-pin TAPE FBGA (11
8)
PD29F064115F9-DB85X-CD5
85
PD29F064115GZ-EB85X-MJH
85
1.8
0.15
48-pin PLASTIC TSOP (I) (12
20)
PD29F064115GZ-EB90X-MJH
90
(Normal bent)
PD29F064115F9-EB85X-CD6
85
63-pin TAPE FBGA (11
8)
PD29F064115F9-EB90X-CD6
90
PD29F064115F9-EB85X-CD5
85
85-pin TAPE FBGA (11
8)
PD29F064115F9-EB90X-CD5
90
Data Sheet M16062EJ2V0DS
3



PD29F064115-X
Pin Configurations
/xxx indicates active low signal.
48-pin PLASTIC TSOP (I) (12



20) (Normal bent)
[



PD29F064115GZ-DB80X-MJH ]
[



PD29F064115GZ-DB85X-MJH ]
[



PD29F064115GZ-EB85X-MJH ]
[



PD29F064115GZ-EB90X-MJH ]
Marking Side
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
/WE
/RESET
A21
/WP (ACC)
RY (/BY)
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
V
CC
Q
GND
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
V
CC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
/OE
GND
/CE
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A0 to A21
: Address inputs
I/O0 to I/O15 : Data Inputs / Outputs
/CE
: Chip Enable
/WE : Write
Enable
/OE : Output
Enable
/RESET : Hardware
reset
input
RY (/BY)
: Ready (Busy) output
/WP (ACC)
: Write Protect (Accelerated) input
V
CC
: Supply
Voltage
V
CC
Q
: Input / Output Supply Voltage
GND : Ground
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M16062EJ2V0DS
4



PD29F064115-X
63-pin TAPE FBGA (11



8)
[



PD29F064115F9-DB80X-CD6 ]
[



PD29F064115F9-DB85X-CD6 ]
[



PD29F064115F9-EB85X-CD6 ]
[



PD29F064115F9-EB90X-CD6 ]
Top View
Bottom View
H
G
F
E
D
C
B
A
H G F E D C B A
Top View
A0
I/O8
I/O6
A3
/CE
I/O15
I/O12
/OE
A4
A6
A13
A9
A2
GND
I/O13
A14
A5
A16
I/O9
I/O11
/WE
V
CC
I/O3
A18
/WP(ACC)
A12
I/O7
I/O14
A10
A8
GND
V
CC
Q
I/O0
A1
A11
I/O4
I/O1
/RESET
A21
A15
A7
RY(/BY)
A17
I/O10
A
B
C
D
E
F
G
H
M
K
L
J
M
K L
J
M
K
L
J
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
I/O5
I/O2
A20
A19
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A0 to A21
: Address inputs
I/O0 to I/O15 : Data Inputs / Outputs
/CE
: Chip Enable
/WE : Write
Enable
/OE : Output
Enable
/RESET : Hardware
reset
input
RY (/BY)
: Ready (Busy) output
/WP (ACC)
: Write Protect (Accelerated) input
V
CC
: Supply
Voltage
V
CC
Q
: Input / Output Supply Voltage
GND : Ground
NC
Note
: No Connection
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the index mark.
Data Sheet M16062EJ2V0DS
5



PD29F064115-X
85-pin TAPE FBGA (11



8)
[



PD29F064115F9-DB80X-CD5 ]
[



PD29F064115F9-DB85X-CD5 ]
[



PD29F064115F9-EB85X-CD5 ]
[



PD29F064115F9-EB90X-CD5 ]
Top View
H
G
F
E
D
C
Top View
Bottom View
B
A
A
B
C
D
E
F
G
H
A
B
C
D
E
F
V
SS
I/O9
I/O5
A7
/OE
I/O7
I/O4
I/O0
A6
A18
A11
A8
A5
I/O8
I/O12
A13
A17
SA
/CEf
I/O10
V
CC
f
/WE
V
CC
s
A16
I/O11
8
7
6
5
4
3
G
H
RY(/BY)
/RESET
A12
I/O6
I/O13
A9
A15
A19
I/O14
/CE1s
I/O15, A-1
I/O1
A1
A2
A4
A10
CIOs
I/O2
A0
A3
2
1
CE2s
A20
A14
/LB
CIOf
/WP(ACC)
/UB
I/O3
NC
NC
V
SS
Top View
Bottom View
H
G
F
E
D
C
B
A
H G F E D C B A
Top View
GND
I/O9
I/O5
A7
/OE
I/O7
I/O4
I/O0
A6
A18
A11
A8
A5
I/O8
I/O12
A13
A17
NC
/CE
I/O10
V
CC
/WE
NC
A16
I/O11
RY(/BY)
/RESET
A12
I/O6
I/O13
A9
A15
A19
I/O14
NC
I/O15
I/O1
A1
A2
A4
A10
V
CC
Q
I/O2
A0
A3
NC
A20
A14
NC
NC
/WP(ACC)
NC
I/O3
A21
NC
GND
A
B
C
D
E
F
G
H
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
M
K
L
J
M
K L
J
M
K
L
J
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
A0 to A21
: Address inputs
I/O0 to I/O15 : Data Inputs / Outputs
/CE
: Chip Enable
/WE : Write
Enable
/OE : Output
Enable
/RESET : Hardware
reset
input
RY (/BY)
: Ready (Busy) output
/WP (ACC)
: Write Protect (Accelerated) input
V
CC
: Supply
Voltage
V
CC
Q
: Input / Output Supply Voltage
GND : Ground
NC
Note
: No Connection
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the index mark.
INPUT / OUTPUT PIN FUNCTION
Refer to PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY Information (M15451E).
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