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Datasheet: M15822EJ4V0DS00 (NEC)

 

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MOS INTEGRATED CIRCUIT



PD44164084, 44164184, 44164364
18M-BIT DDRII SRAM
4-WORD BURST OPERATION
Document No. M15822EJ4V0DS00 (4th edition)
Date Published June 2003 NS CP(K)
Printed in Japan
PRELIMINARY DATA SHEET
2001
Description
The
PD44164084 is a 2,097,152-word by 8-bit, the PD44164184 is a 1,048,576-word by 18-bit and the PD44164364
is a 524,288-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using
full CMOS six-transistor memory cell.
The
PD44164084, PD44164184 and PD44164364 integrates unique synchronous peripheral circuitry and a burst
counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and /K.
These products are suitable for application which require synchronous operation, high speed, low voltage, high
density and wide bit configuration.
These products are packaged in 165-pin PLASTIC FBGA.
Features
1.8 0.1 V power supply and HSTL I/O
DLL circuitry for wide output data valid window and future frequency scaling
Pipelined double data rate operation
Common data input/output bus
Four-tick burst for reduced address frequency
Two input clocks (K and /K) for precise DDR timing at clock rising edges only
Two output clocks (C and /C) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
Internally self-timed write control
Clock-stop capability with
s restart
User programmable impedance output
Fast clock cycle time : 4.0 ns (250 MHz), 5.0 ns (200 MHz), 6.0 ns (167 MHz)
Simple control logic for easy depth expansion
JTAG boundary scan
2
Preliminary Data Sheet M15822EJ4V0DS



PD44164084, 44164184, 44164364
Ordering Information
Part number
Cycle
Clock
Organization Core Supply
I/O
Package
Time
Frequency
(word x bit)
Voltage
Interface
ns
MHz
V
PD44164084F5-E40-EQ1
4.0
250
2 M x 8-bit
1.8 0.1
HSTL
165-pin PLASTIC
PD44164084F5-E50-EQ1
5.0
200
FBGA (13 x 15)
PD44164084F5-E60-EQ1
6.0
167
PD44164184F5-E40-EQ1
4.0
250
1 M x 18-bit
PD44164184F5-E50-EQ1
5.0
200
PD44164184F5-E60-EQ1
6.0
167
PD44164364F5-E40-EQ1
4.0
250
512 K x 36-bit
PD44164364F5-E50-EQ1
5.0
200
PD44164364F5-E60-EQ1
6.0
167
3
Preliminary Data Sheet M15822EJ4V0DS



PD44164084, 44164184, 44164364
Pin Configurations
/
indicates active low signal.
165-pin PLASTIC FBGA (13 x 15)
(Top View)
[



PD44164084F5-EQ1]
1
2
3
4
5
6
7
8
9
10
11
A
/CQ
V
SS
A
R, /W
/NW1
/K
NC
/LD
A
V
SS
CQ
B
NC
NC
NC
A
NC
K
/NW0
A
NC
NC
DQ3
C
NC
NC
NC
V
SS
A
NC
A
V
SS
NC
NC
NC
D
NC
NC
NC
V
SS
V
SS
V
SS
V
SS
V
SS
NC
NC
NC
E
NC
NC
DQ4
V
DD
Q
V
SS
V
SS
V
SS
V
DD
Q
NC
NC
DQ2
F
NC
NC
NC
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
NC
NC
NC
G
NC
NC
DQ5
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
NC
NC
NC
H
/DLL
V
REF
V
DD
Q
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
V
DD
Q
V
REF
ZQ
J
NC
NC
NC
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
NC
DQ1
NC
K
NC
NC
NC
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
NC
NC
NC
L
NC
DQ6
NC
V
DD
Q
V
SS
V
SS
V
SS
V
DD
Q
NC
NC
DQ0
M
NC
NC
NC
V
SS
V
SS
V
SS
V
SS
V
SS
NC
NC
NC
N
NC
NC
NC
V
SS
A
A
A
V
SS
NC
NC
NC
P
NC
NC
DQ7
A
A
C
A
A
NC
NC
NC
R
TDO
TCK
A
A
A
/C
A
A
A
TMS
TDI
A
: Address inputs
TMS
: IEEE 1149.1 Test input
DQ0 to DQ7
: Data inputs / outputs
TDI
: IEEE 1149.1 Test input
/LD
: Synchronous load
TCK
: IEEE 1149.1 Clock input
R, /W
: Read Write input
TDO
: IEEE 1149.1 Test output
/NW0, /NW1
: Nibble Write data select
V
REF
: HSTL input reference input
K, /K
: Input clock
V
DD
: Power Supply
C, /C
: Output clock
V
DD
Q
: Power Supply
CQ, /CQ
: Echo clock
V
SS
: Ground
ZQ
: Output impedance matching
NC
: No connection
/DLL
: DLL disable
Remark Refer to Package Drawing for the index mark.
4
Preliminary Data Sheet M15822EJ4V0DS



PD44164084, 44164184, 44164364
165-pin PLASTIC FBGA (13 x 15)
(Top View)
[



PD44164184F5-EQ1]
1
2
3
4
5
6
7
8
9
10
11
A
/CQ
V
SS
A
R, /W
/BW1
/K
NC
/LD
A
V
SS
CQ
B
NC
DQ9
NC
A
NC
K
/BW0
A
NC
NC
DQ8
C
NC
NC
NC
V
SS
A
A0
A1
V
SS
NC
DQ7
NC
D
NC
NC
DQ10
V
SS
V
SS
V
SS
V
SS
V
SS
NC
NC
NC
E
NC
NC
DQ11
V
DD
Q
V
SS
V
SS
V
SS
V
DD
Q
NC
NC
DQ6
F
NC
DQ12
NC
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
NC
NC
DQ5
G
NC
NC
DQ13
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
NC
NC
NC
H
/DLL
V
REF
V
DD
Q
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
V
DD
Q
V
REF
ZQ
J
NC
NC
NC
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
NC
DQ4
NC
K
NC
NC
DQ14
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
NC
NC
DQ3
L
NC
DQ15
NC
V
DD
Q
V
SS
V
SS
V
SS
V
DD
Q
NC
NC
DQ2
M
NC
NC
NC
V
SS
V
SS
V
SS
V
SS
V
SS
NC
DQ1
NC
N
NC
NC
DQ16
V
SS
A
A
A
V
SS
NC
NC
NC
P
NC
NC
DQ17
A
A
C
A
A
NC
NC
DQ0
R
TDO
TCK
A
A
A
/C
A
A
A
TMS
TDI
A0, A1, A
: Address inputs
TMS
: IEEE 1149.1 Test input
DQ0 to DQ17
: Data inputs / outputs
TDI
: IEEE 1149.1 Test input
/LD
: Synchronous load
TCK
: IEEE 1149.1 Clock input
R, /W
: Read Write input
TDO
: IEEE 1149.1 Test output
/BW0, /BW1
: Byte Write data select
V
REF
: HSTL input reference input
K, /K
: Input clock
V
DD
: Power Supply
C, /C
: Output clock
V
DD
Q
: Power Supply
CQ, /CQ
: Echo clock
V
SS
: Ground
ZQ
: Output impedance matching
NC
: No connection
/DLL
: DLL disable
Remark Refer to Package Drawing for the index mark.
5
Preliminary Data Sheet M15822EJ4V0DS



PD44164084, 44164184, 44164364
165-pin PLASTIC FBGA (13 x 15)
(Top View)
[



PD44164364F5-EQ1]
1
2
3
4
5
6
7
8
9
10
11
A
/CQ
V
SS
NC
R, /W
/BW2
/K
/BW1
/LD
A
V
SS
CQ
B
NC
DQ27
DQ18
A
/BW3
K
/BW0
A
NC
NC
DQ8
C
NC
NC
DQ28
V
SS
A
A0
A1
V
SS
NC
DQ17
DQ7
D
NC
DQ29
DQ19
V
SS
V
SS
V
SS
V
SS
V
SS
NC
NC
DQ16
E
NC
NC
DQ20
V
DD
Q
V
SS
V
SS
V
SS
V
DD
Q
NC
DQ15
DQ6
F
NC
DQ30
DQ21
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
NC
NC
DQ5
G
NC
DQ31
DQ22
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
NC
NC
DQ14
H
/DLL
V
REF
V
DD
Q
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
V
DD
Q
V
REF
ZQ
J
NC
NC
DQ32
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
NC
DQ13
DQ4
K
NC
NC
DQ23
V
DD
Q
V
DD
V
SS
V
DD
V
DD
Q
NC
DQ12
DQ3
L
NC
DQ33
DQ24
V
DD
Q
V
SS
V
SS
V
SS
V
DD
Q
NC
NC
DQ2
M
NC
NC
DQ34
V
SS
V
SS
V
SS
V
SS
V
SS
NC
DQ11
DQ1
N
NC
DQ35
DQ25
V
SS
A
A
A
V
SS
NC
NC
DQ10
P
NC
NC
DQ26
A
A
C
A
A
NC
DQ9
DQ0
R
TDO
TCK
A
A
A
/C
A
A
A
TMS
TDI
A0, A1, A
: Address inputs
TMS
: IEEE 1149.1 Test input
DQ0 to DQ35
: Data inputs / outputs
TDI
: IEEE 1149.1 Test input
/LD
: Synchronous load
TCK
: IEEE 1149.1 Clock input
R, /W
: Read Write input
TDO
: IEEE 1149.1 Test output
/BW0 to /BW3
: Byte Write data select
V
REF
: HSTL input reference input
K, /K
: Input clock
V
DD
: Power Supply
C, /C
: Output clock
V
DD
Q
: Power Supply
CQ, /CQ
: Echo clock
V
SS
: Ground
ZQ
: Output impedance matching
NC
: No connection
/DLL
: DLL disable
Remark Refer to Package Drawing for the index mark.
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