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Datasheet: M15709EJ2V0DS00 (NEC)

 

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MOS INTEGRATED CIRCUIT



PD23C16340, 23C16380
16M-BIT MASK-PROGRAMMABLE ROM
2M-WORD BY 8-BIT (BYTE MODE) / 1M-WORD BY 16-BIT (WORD MODE)
PAGE ACCESS MODE
Document No. M15709EJ2V0DS00 (2nd edition)
Date Published February 2003 NS CP(K)
Printed in Japan
DATA SHEET
The mark shows major revised points.
2001
Description
The
PD23C16340 and PD23C16380 are 16,777,216 bits mask-programmable ROM. The word organization is
selectable (BYTE mode : 2,097,152 words by 8 bits, WORD mode : 1,048,576 words by 16 bits).
The active levels of OE (Output Enable Input) can be selected with mask-option.
The
PD23C16340 and PD23C16380 are packed in 48-pin PLASTIC TSOP(I) and 48-pin TAPE FBGA.
Features
Pin compatible with NOR Flash Memory
Word organization
2,097,152 words by 8 bits (BYTE mode)
1,048,576 words by 16 bits (WORD mode)
Page access mode
BYTE mode : 8 byte random page access (
PD23C16340)
16 byte random page access (
PD23C16380)
WORD mode : 4 word random page access (
PD23C16340)
8 word random page access (
PD23C16380)
Operating supply voltage : V
CC
= 2.7 V to 3.6 V
Operating supply
Access time /
Power supply current (Active mode)
Standby current
voltage
Page access time
mA (MAX.)
(CMOS level input)
V
CC
ns (MAX.)
PD23C16340
PD23C16380
A (MAX.)
3.0 V
0.3 V
90 / 25
40
55
30
3.3 V
0.3 V
85 / 25
2



PD23C16340, 23C16380
Data Sheet M15709EJ2V0DS
Ordering Information
Part Number
Package
PD23C16340GZ-xxx-MJH
48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent)
PD23C16340F9-xxx-BC3
48-pin TAPE FBGA (8 x 6)
PD23C16380GZ-xxx-MJH
48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent)
PD23C16380F9-xxx-BC3
48-pin TAPE FBGA (8 x 6)
(xxx : ROM code suffix No.)
3



PD23C16340, 23C16380
Data Sheet M15709EJ2V0DS
Pin Configurations
/xxx indicates active low signal.
48-pin PLASTIC TSOP(I) (12 x 20) (Normal bent)
[



PD23C16340GZ-xxx-MJH ]
[



PD23C16380GZ-xxx-MJH ]
Marking Side
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
NC
NC
NC
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
WORD, /BYTE
GND
O15, A
-1
O7
O14
O6
O13
O5
O12
O4
V
CC
O11
O3
O10
O2
O9
O1
O8
O0
/OE or OE or DC
GND
/CE
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A0 to A19
: Address inputs
O0 to O7, O8 to O14 : Data outputs
O15, A1
: Data output 15 (WORD mode),
LSB Address input (BYTE mode)
WORD, /BYTE
: Mode select
/CE
: Chip Enable
/OE or OE
: Output Enable
V
CC
: Supply voltage
GND
: Ground
NC
Note
: No Connection
DC
: Don't Care
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the 1-pin index mark.
4



PD23C16340, 23C16380
Data Sheet M15709EJ2V0DS
48-pin TAPE FBGA (8 x 6)
[



PD23C16340F9-xxx-BC3 ]
[



PD23C16380F9-xxx-BC3 ]
6
5
4
3
2
1
A
B
C
D
E
F
G
H
H
G
F
E
D
C
B
A
Top View
Bottom View
A
B
C
D
E
F
G
H
H
G
F
E
D
C
B
A
6
A13
A12
A14
A15
A16
WORD,
O15,
GND
6
GND
O15,
WORD,
A16
A15
A14
A12
A13
/BYTE
A1
A1
/BYTE
5
A9
A8
A10
A11
O7
O14
O13
O6
5
O6
O13
O14
O7
A11
A10
A8
A9
4
NC
NC
NC
A19
O5
O12
V
CC
O4
4
O4
V
CC
O12
O5
A19
NC
NC
NC
3
NC
NC
A18
NC
O2
O10
O11
O3
3
O3
O11
O10
O2
NC
A18
NC
NC
2
A7
A17
A6
A5
O0
O8
O9
O1
2
O1
O9
O8
O0
A5
A6
A17
A7
1
A3
A4
A2
A1
A0
/CE
/OE or
GND
1
GND
/OE or
/CE
A0
A1
A2
A4
A3
OE
OE
A0 to A19
: Address inputs
O0 to O7, O8 to O14 : Data outputs
O15, A1
: Data output 15 (WORD mode),
LSB Address input (BYTE mode)
WORD, /BYTE
: Mode select
/CE
: Chip Enable
/OE or OE
: Output Enable
V
CC
: Supply voltage
GND
: Ground
NC
Note
: No Connection
DC
: Don't Care
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the index mark.
5



PD23C16340, 23C16380
Data Sheet M15709EJ2V0DS
Input / Output Pin Functions
Pin name
Input / Output
Function
WORD, /BYTE
Input
The pin for switching WORD mode and BYTE mode.
High level : WORD mode (1M-word by 16-bit)
Low level : BYTE mode (2M-word by 8-bit)
A0 to A19
(Address inputs)
Input
Address input pins.
A0 to A19 are used differently in the WORD mode and the BYTE mode.
WORD mode (1M-word by 16-bit)
A0 to A19 are used as 20 bits address signals.
BYTE mode (2M-word by 8-bit)
A0 to A19 are used as the upper 20 bits of total 21 bits of address signal.
(The least significant bit (A
-1) is combined to O15.)
O0 to O7, O8 to O14
(Data outputs)
Output
Data output pins.
O0 to O7, O8 to O14 are used differently in the WORD mode and the BYTE mode.
WORD mode (1M-word by 16-bit)
The lower 15 bits of 16 bits data outputs to O0 to O14.
(The most significant bit (O15) combined to A
-1.)
BYTE mode (2M-word by 8-bit)
8 bits data outputs to O0 to O7 and also O8 to O14 are high impedance.
O15, A
-1
(Data output 15,
LSB Address input)
Output, Input O15, A
-1 are used differently in the WORD mode and the BYTE mode.
WORD mode (1M-word by 16-bit)
The most significant output data bus (O15).
BYTE mode (2M-word by 8-bit)
The least significant address bus (A
-1).
/CE
(Chip Enable)
Input
Chip activating signal.
When the OE is active, output states are following.
High level : High-Z
Low level : Data out
/OE or OE or DC
(Output Enable, Don't care)
Input
Output enable signal. The active level of OE is mask option. The active level of OE
can be selected from high active, low active and Don't care at order.
V
CC
-
Supply voltage
GND
-
Ground
NC
-
Not internally connected. (The signal can be connected.)
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