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Datasheet: M15561EJ3V0DS00 (NEC)

 

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MOS INTEGRATED CIRCUIT
PD4481161, 4481181, 4481321, 4481361
8M-BIT ZEROSB
TM
SRAM
FLOW THROUGH OPERATION
Document No. M15561EJ3V0DS00 (3rd edition)
Date Published December 2002 NS CP(K)
Printed in Japan
DATA SHEET
The mark shows major revised points.
2001
Description
The
PD4481161 is a 524,288-word by 16-bit, the PD4481181 is a 524,288-word by 18-bit, the PD4481321 is a
262,144-word by 32-bit and the
PD4481361 is a 262,144-word by 36-bit ZEROSB static RAM fabricated with
advanced CMOS technology using full CMOS six-transistor memory cell.
The
PD4481161, PD4481181, PD4481321 and PD4481361 are optimized to eliminate dead cycles for read to
write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit
burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the
single clock input (CLK).
The
PD4481161, PD4481181, PD4481321 and PD4481361 are suitable for applications which require
synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State
("Sleep"). In the "Sleep" state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes
normal operation.
The
PD4481161, PD4481181, PD4481321 and PD4481361 are packaged in 100-pin PLASTIC LQFP with a
1.4 mm package thickness for high density and low capacitive loading.
Features
Low voltage core supply : V
DD
= 3.3 0.165 V (-A65, -A75, -A85, -A65Y, -A75Y, -A85Y)
V
DD
= 2.5 0.125 V (-C75, -C85, -C75Y, -C85Y)
Synchronous operation
Operating temperature : T
A
= 0 to 70
C (-A65, -A75, -A85, -C75, -C85)
T
A
=
-40 to +85 C (-A65Y, -A75Y, -A85Y, -C75Y, -C85Y)
100 percent bus utilization
Internally self-timed write control
Burst read / write : Interleaved burst and linear burst sequence
Fully registered inputs and outputs for flow through operation
All registers triggered off positive clock edge
3.3V or 2.5V LVTTL Compatible : All inputs and outputs
Fast clock access time : 6.5 ns (133 MHz), 7.5 ns (117 MHz), 8.5 ns (100 MHz)
Asynchronous output enable : /G
Burst sequence selectable : MODE
Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
Separate byte write enable : /BW1 to /BW4 (
PD4481321 and PD4481361)
/BW1 and /BW2 (
PD4481161 and PD4481181)
Three chip enables for easy depth expansion
Common I/O using three state outputs
2
Data Sheet M15561EJ3V0DS
PD4481161, 4481181, 4481321, 4481361
Ordering Information
(1/2)
Part number
Access
Clock
Core Supply
I/O Interface
Operating
Package
Time
Frequency
Voltage
Temperature
ns
MHz
V
C
PD4481161GF-A65
6.5
133
3.3 0.165
3.3 V LVTTL
Note
0 to 70
100-pin PLASTIC
PD4481161GF-A75
7.5
117
3.3 V or 2.5 V LVTTL
LQFP (14 x 20)
PD4481161GF-A85
8.5
100
PD4481181GF-A65
6.5
133
3.3 V LVTTL
Note
PD4481181GF-A75
7.5
117
3.3 V or 2.5 V LVTTL
PD4481181GF-A85
8.5
100
PD4481321GF-A65
6.5
133
3.3 V LVTTL
Note
PD4481321GF-A75
7.5
117
3.3 V or 2.5 V LVTTL
PD4481321GF-A85
8.5
100
PD4481361GF-A65
6.5
133
3.3 V LVTTL
Note
PD4481361GF-A75
7.5
117
3.3 V or 2.5 V LVTTL
PD4481361GF-A85
8.5
100
PD4481161GF-C75
7.5
117
2.5 0.125
2.5 V LVTTL
PD4481161GF-C85
8.5
100
PD4481181GF-C75
7.5
117
PD4481181GF-C85
8.5
100
PD4481321GF-C75
7.5
117
PD4481321GF-C85
8.5
100
PD4481361GF-C75
7.5
117
PD4481361GF-C85
8.5
100
Note Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A75 (117 MHz).
3
Data Sheet M15561EJ3V0DS
PD4481161, 4481181, 4481321, 4481361
(2/2)
Part number
Access
Clock
Core Supply
I/O Interface
Operating
Package
Time
Frequency
Voltage
Temperature
ns
MHz
V
C
PD4481161GF-A65Y
6.5
133
3.3 0.165
3.3 V LVTTL
Note
-40 to +85
100-pin PLASTIC
PD4481161GF-A75Y
7.5
117
3.3 V or 2.5 V LVTTL
LQFP (14 x 20)
PD4481161GF-A85Y
8.5
100
PD4481181GF-A65Y
6.5
133
3.3 V LVTTL
Note
PD4481181GF-A75Y
7.5
117
3.3 V or 2.5 V LVTTL
PD4481181GF-A85Y
8.5
100
PD4481321GF-A65Y
6.5
133
3.3 V LVTTL
Note
PD4481321GF-A75Y
7.5
117
3.3 V or 2.5 V LVTTL
PD4481321GF-A85Y
8.5
100
PD4481361GF-A65Y
6.5
133
3.3 V LVTTL
Note
PD4481361GF-A75Y
7.5
117
3.3 V or 2.5 V LVTTL
PD4481361GF-A85Y
8.5
100
PD4481161GF-C75Y
7.5
117
2.5 0.125
2.5 V LVTTL
PD4481161GF-C85Y
8.5
100
PD4481181GF-C75Y
7.5
117
PD4481181GF-C85Y
8.5
100
PD4481321GF-C75Y
7.5
117
PD4481321GF-C85Y
8.5
100
PD4481361GF-C75Y
7.5
117
PD4481361GF-C85Y
8.5
100
Note Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A75Y (117 MHz).
4
Data Sheet M15561EJ3V0DS
PD4481161, 4481181, 4481321, 4481361
Pin Configurations
/
indicates active low signal.

100-pin PLASTIC LQFP (14



20)

[



PD4481161GF, PD4481181GF]
Marking Side
NC
NC
NC
V
DD
Q
V
SS
Q
NC
NC
I/O9
I/O10
V
SS
Q
V
DD
Q
I/O11
I/O12
V
SS
V
DD
V
DD
V
SS
I/O13
I/O14
V
DD
Q
V
SS
Q
I/O15
I/O16
I/OP2, NC
NC
V
SS
Q
V
DD
Q
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A18
NC
NC
V
DD
Q
V
SS
Q
NC
I/OP1, NC
I/O8
I/O7
V
SS
Q
V
DD
Q
I/O6
I/O5
V
SS
V
SS
V
DD
ZZ
I/O4
I/O3
V
DD
Q
V
SS
Q
I/O2
I/O1
NC
NC
V
SS
Q
V
DD
Q
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6
A7
/CE
CE2
NC
NC
/BW2
/BW1
/CE2
V
DD
V
SS
CLK
/WE
/CKE
/G
ADV
NC
A17
A8
A9
MODE
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A10
A11
A12
A13
A14
A15
A16
Remark Refer to Package Drawing for the 1-pin index mark.
5
Data Sheet M15561EJ3V0DS
PD4481161, 4481181, 4481321, 4481361

Pin Identifications

[



PD4481161GF, PD4481181GF]
Symbol
Pin No.
Description
A0 to A18
37, 36, 35, 34, 33, 32, 100, 99, 82, 81,
Synchronous Address Input
44, 45, 46, 47, 48, 49, 50, 83, 80
I/O1 to I/O16
58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13,
Synchronous Data In,
18, 19, 22, 23
Synchronous / Asynchronous Data Out
I/OP1, NC
Note
74
Synchronous Data In (Parity),
I/OP2, NC
Note
24
Synchronous / Asynchronous Data Out (Parity)
ADV
85
Synchronous Address Load / Advance Input
/CE, CE2, /CE2
98, 97, 92
Synchronous Chip Enable Input
/WE
88
Synchronous Write Enable Input
/BW1, /BW2
93, 94
Synchronous Byte Write Enable Input
/G
86
Asynchronous Output Enable Input
CLK
89
Clock Input
/CKE
87
Synchronous Clock Enable Input
MODE
31
Asynchronous Burst Sequence Select Input
Have to tied to V
DD
or V
SS
during normal operation
ZZ
64
Asynchronous Power Down State Input
V
DD
15, 16, 41, 65, 91
Power Supply
V
SS
14, 17, 40, 66, 67, 90
Ground
V
DD
Q
4, 11, 20, 27, 54, 61, 70, 77
Output Buffer Power Supply
V
SS
Q
5, 10, 21, 26, 55, 60, 71, 76
Output Buffer Ground
NC
1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 43,
No Connection
51, 52, 53, 56, 57, 75, 78, 79, 84, 95, 96
Note NC (No Connection) is used in the
PD4481161GF.
I/OP1 and I/OP2 are used in the
PD4481181GF.
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