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Datasheet: M15502EJ1V0DS00 (NEC)

 

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2001
MOS INTEGRATED CIRCUIT
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y
4M-BIT CMOS SYNCHRONOUS FAST SRAM
FLOW THROUGH OPERATION
Document No. M15502EJ1V0DS00 (1st edition)
Date Published May 2001 NS CP(K)
Printed in Japan
PRELIMINARY DATA SHEET
Description
The
PD4442161-Y is a 262,144-word by 16-bit, the
PD4442181-Y is a 262,144-word by 18-bit, the
PD4442321-Y
is a 131,072-word by 32-bit and the
PD4442361-Y is a 131,072-word by 36-bit synchronous static RAM fabricated
with advanced CMOS technology using Full-CMOS six-transistor memory cell.
The
PD4442161-Y,
PD4442181-Y,
PD4442321-Y and
PD4442361-Y integrate unique synchronous peripheral
circuitry, 2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive
edge of the single clock input (CLK).
The
PD4442161-Y,
PD4442181-Y,
PD4442321-Y and
PD4442361-Y are suitable for applications which require
synchronous operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer
memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State ("Sleep").
In the "Sleep" state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal
operation.
The
PD4442161-Y,
PD4442181-Y,
PD4442321-Y and
PD4442361-Y are packaged in 100-pin PLASTIC LQFP
with a 1.4 mm package thickness for high density and low capacitive loading.
Features
3.3 V (A version) or 2.5 V (C version) Core Supply
Synchronous operation
Extended operating temperature (T
A
= 40 to +85
C)
Internally self-timed write control
Burst read / write : Interleaved burst and linear burst sequence
Fully registered inputs for flow through operation
All registers triggered off positive clock edge
3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs
Fast clock access time : 6.5 ns (133 MHz), 7.5 ns (117 MHz), 8.5 ns (100 MHz)
Asynchronous output enable : /G
Burst sequence selectable : MODE
Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
Separate byte write enable : /BW1 - /BW4 (
PD4442321-Y,
PD4442361-Y), /BW1 - /BW2 (
PD4442161-Y,
PD4442181-Y), /BWE
Global write enable : /GW
Three chip enables for easy depth expansion
Common I/O using three state outputs
2
Preliminary Data Sheet M15502EJ1V0DS
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y
Ordering Information
Part number
Access
Clock
Core Supply
I/O
Package
Remark
Time
Frequency
Voltage
Interface
ns
MHz
V
PD4442161GF-A65Y
6.5
133
3.3 0.165
3.3 V or 2.5 V
100-pin PLASTIC
A version
PD4442161GF-A75Y
7.5
117
LVTTL
LQFP (14
20)
PD4442161GF-A85Y
8.5
100
PD4442181GF-A65Y
6.5
133
PD4442181GF-A75Y
7.5
117
PD4442181GF-A85Y
8.5
100
PD4442321GF-A65Y
6.5
133
PD4442321GF-A75Y
7.5
117
PD4442321GF-A85Y
8.5
100
PD4442361GF-A65Y
6.5
133
PD4442361GF-A75Y
7.5
117
PD4442361GF-A85Y
8.5
100
PD4442161GF-C75Y
Note
7.5
117
2.5 0.125
2.5 V LVTTL
C version
PD4442161GF-C85Y
Note
8.5
100
PD4442181GF-C75Y
Note
7.5
117
PD4442181GF-C85Y
Note
8.5
100
PD4442321GF-C75Y
Note
7.5
117
PD4442321GF-C85Y
Note
8.5
100
PD4442361GF-C75Y
Note
7.5
117
PD4442361GF-C85Y
Note
8.5
100
Note Under development
3
Preliminary Data Sheet M15502EJ1V0DS
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y
Pin Configurations (Marking Side)
/
indicates active low signal.
100-pin PLASTIC LQFP (14



20)
[



PD4442161GF-Y,



PD4442181GF-Y ]
NC
NC
NC
V
DD
Q
V
SS
Q
NC
NC
I/O9
I/O10
V
SS
Q
V
DD
Q
I/O11
I/O12
NC
V
DD
NC
V
SS
I/O13
I/O14
V
DD
Q
V
SS
Q
I/O15
I/O16
I/OP2, NC
NC
V
SS
Q
V
DD
Q
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A17
NC
NC
V
DD
Q
V
SS
Q
NC
I/OP1, NC
I/O8
I/O7
V
SS
Q
V
DD
Q
I/O6
I/O5
V
SS
NC
V
DD
ZZ
I/O4
I/O3
V
DD
Q
V
SS
Q
I/O2
I/O1
NC
NC
V
SS
Q
V
DD
Q
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6
A7
/CE
CE2
NC
NC
/BW2
/BW1
/CE2
V
DD
V
SS
CLK
/GW
/BWE
/G
/AC
/AP
/ADV
A8
A9
MODE
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A10
A11
A12
A13
A14
A15
A16
Remark Refer to Package Drawing for 1-pin index mark.
4
Preliminary Data Sheet M15502EJ1V0DS
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y
Pin Identifications
[



PD4442161GF-Y,



PD4442181GF-Y ]
Symbol
Pin No.
Description
A0 - A17
37, 36, 35, 34, 33, 32, 100, 99, 82, 81,
Synchronous Address Input
44, 45, 46, 47, 48, 49, 50, 80
I/O1 - I/O16
58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12,
Synchronous Data In,
13, 18, 19, 22, 23
Synchronous / Asynchronous Data Out
I/OP1, NC
Note
74
Synchronous Data In (Parity),
I/OP2, NC
Note
24
Synchronous / Asynchronous Data Out (Parity)
/ADV
83
Synchronous Burst Address Advance Input
/AP
84
Synchronous Address Status Processor Input
/AC
85
Synchronous Address Status Controller Input
/CE, CE2, /CE2
98, 97, 92
Synchronous Chip Enable Input
/BW1, /BW2, /BWE
93, 94, 87
Synchronous Byte Write Enable Input
/GW
88
Synchronous Global Write Input
/G
86
Asynchronous Output Enable Input
CLK
89
Clock Input
MODE
31
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
ZZ
64
Asynchronous Power Down State Input
V
DD
15, 41, 65, 91
Power Supply
V
SS
17, 40, 67, 90
Ground
V
DD
Q
4, 11, 20, 27, 54, 61, 70, 77
Output Buffer Power Supply
V
SS
Q
5, 10, 21, 26, 55, 60, 71, 76
Output Buffer Ground
NC
1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38,
No Connection
39, 42, 43, 51, 52, 53, 56, 57, 66, 75,
78, 79, 95, 96
Note NC (No Connection) is used in the
PD4442161GF-Y.
I/OP1 - I/OP2 are used in the
PD4442181GF-Y.
5
Preliminary Data Sheet M15502EJ1V0DS
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y
100-pin PLASTIC LQFP (14



20)
[



PD4442321GF-Y,



PD4442361GF-Y ]
I/OP3, NC
I/O17
I/O18
V
DD
Q
V
SS
Q
I/O19
I/O20
I/O21
I/O22
V
SS
Q
V
DD
Q
I/O23
I/O24
NC
V
DD
NC
V
SS
I/O25
I/O26
V
DD
Q
V
SS
Q
I/O27
I/O28
I/O29
I/O30
V
SS
Q
V
DD
Q
I/O31
I/O32
I/OP4, NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/OP2, NC
I/O16
I/O15
V
DD
Q
V
SS
Q
I/O14
I/O13
I/O12
I/O11
V
SS
Q
V
DD
Q
I/O10
I/O9
V
SS
NC
V
DD
ZZ
I/O8
I/O7
V
DD
Q
V
SS
Q
I/O6
I/O5
I/O4
I/O3
V
SS
Q
V
DD
Q
I/O2
I/O1
I/OP1, NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6
A7
/CE
CE2
/BW4
/BW3
/BW2
/BW1
/CE2
V
DD
V
SS
CLK
/GW
/BWE
/G
/AC
/AP
/ADV
A8
A9
MODE
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A10
A11
A12
A13
A14
A15
A16
Remark Refer to Package Drawing for 1-pin index mark.
6
Preliminary Data Sheet M15502EJ1V0DS
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y
[



PD4442321GF-Y,



PD4442361GF-Y ]
Symbol
Pin No.
Description
A0 - A16
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input
45, 46, 47, 48, 49, 50
I/O1 - I/O32
52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72,
Synchronous Data In,
73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13,
Synchronous / Asynchronous Data Out
18, 19, 22, 23, 24, 25, 28, 29
I/OP1, NC
Note
51
Synchronous Data In (Parity),
I/OP2, NC
Note
80
Synchronous / Asynchronous Data Out (Parity)
I/OP3, NC
Note
1
I/OP4, NC
Note
30
/ADV
83
Synchronous Burst Address Advance Input
/AP
84
Synchronous Address Status Processor Input
/AC
85
Synchronous Address Status Controller Input
/CE, CE2, /CE2
98, 97, 92
Synchronous Chip Enable Input
/BW1 - /BW4, /BWE
93, 94, 95, 96, 87
Synchronous Byte Write Enable Input
/GW
88
Synchronous Global Write Input
/G
86
Asynchronous Output Enable Input
CLK
89
Clock Input
MODE
31
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
ZZ
64
Asynchronous Power Down State Input
V
DD
15, 41, 65, 91
Power Supply
V
SS
17, 40, 67, 90
Ground
V
DD
Q
4, 11, 20, 27, 54, 61, 70, 77
Output Buffer Power Supply
V
SS
Q
5, 10, 21, 26, 55, 60, 71, 76
Output Buffer Ground
NC
14, 16, 38, 39, 42, 43, 66
No Connection
Note NC (No Connection) is used in the
PD4442321GF-Y.
I/OP1 - I/OP4 are used in the
PD4442361GF-Y.
7
Preliminary Data Sheet M15502EJ1V0DS
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y
Block Diagrams
[



PD4442161-Y,






PD4442181-Y ]
Address
register
Binary
counter
and logic
CLR
Q0
Q1
Byte 1
Write register
Byte 1
Write driver
8/9
Byte 2
Write register
Byte 2
Write driver
8/9
Enable
register
Row and column
Input
register
Output
buffer
18
18
16
18
A0, A1
A1'
A0'
2
16/18
A0 - A17
MODE
/ADV
CLK
/AC
/AP
/BW1
/BW2
/BWE
/GW
/CE
CE2
/CE2
/G
I/O1 - I/O16
I/OP1 - I/OP2
ZZ
Power down control
16/18
16/18
Memory Cell Array
512 rows
512
16 columns
(4,194,304 bits)
512
18 columns
(4,718,592 bits)
decoders
Burst Sequence
[



PD4442161-Y,






PD4442181-Y ]
Interleaved Burst Sequence Table (MODE = Open or V
DD
)
External Address
A17 - A2, A1, A0
1st Burst Address
A17 - A2, A1, /A0
2nd Burst Address
A17 - A2, /A1, A0
3rd Burst Address
A17 - A2, /A1, /A0
Linear Burst Sequence Table (MODE = V
SS
)
External Address
A17 - A2, 0, 0
A17 - A2, 0, 1
A17 - A2, 1, 0
A17 - A2, 1, 1
1st Burst Address
A17 - A2, 0, 1
A17 - A2, 1, 0
A17 - A2, 1, 1
A17 - A2, 0, 0
2nd Burst Address
A17 - A2, 1, 0
A17 - A2, 1, 1
A17 - A2, 0, 0
A17 - A2, 0, 1
3rd Burst Address
A17 - A2, 1, 1
A17 - A2, 0, 0
A17 - A2, 0, 1
A17 - A2, 1, 0
8
Preliminary Data Sheet M15502EJ1V0DS
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y
[



PD4442321-Y,






PD4442361-Y ]
Address
register
Binary
counter
and logic
CLR
Q0
Q1
Byte 1
Write register
Byte 1
Write driver
8/9
Byte 2
Write register
Byte 2
Write driver
8/9
Byte 3
Write register
Byte 3
Write driver
8/9
Byte 4
Write register
Byte 4
Write driver
8/9
Enable
register
Row and column
Input
register
Output
buffer
32/36
17
17
15
17
A0, A1
A1'
A0'
32/36
4
32/36
A0 - A16
MODE
/ADV
CLK
/AC
/AP
/BW1
/BW2
/BW3
/BW4
/BWE
/GW
/CE
CE2
/CE2
/G
I/O1 - I/O32
I/OP1 - I/OP4
ZZ
Power down control
Memory Cell Array
512 rows
256
32 columns
(4,194,304 bits)
256
36 columns
(4,718,592 bits)
decoders
[



PD4442321-Y,






PD4442361-Y ]
Interleaved Burst Sequence Table (MODE = Open or V
DD
)
External Address
A16 - A2, A1, A0
1st Burst Address
A16 - A2, A1, /A0
2nd Burst Address
A16 - A2, /A1, A0
3rd Burst Address
A16 - A2, /A1, /A0
Linear Burst Sequence Table (MODE = V
SS
)
External Address
A16 - A2, 0, 0
A16 - A2, 0, 1
A16 - A2, 1, 0
A16 - A2, 1, 1
1st Burst Address
A16 - A2, 0, 1
A16 - A2, 1, 0
A16 - A2, 1, 1
A16 - A2, 0, 0
2nd Burst Address
A16 - A2, 1, 0
A16 - A2, 1, 1
A16 - A2, 0, 0
A16 - A2, 0, 1
3rd Burst Address
A16 - A2, 1, 1
A16 - A2, 0, 0
A16 - A2, 0, 1
A16 - A2, 1, 0
9
Preliminary Data Sheet M15502EJ1V0DS
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y
Asynchronous Truth Table
Operation
/G
I/O
Read Cycle
L
Dout
Read Cycle
H
Hi-Z
Write Cycle
Hi-Z, Din
Deselected
Hi-Z
Remark
: don't care
Synchronous Truth Table
Operation
/CE
CE2
/CE2
/AP
/AC
/ADV
/WRITE
CLK
Address
Deselected
Note
H
L
L
H
None
Deselected
Note
L
L
L
L
H
None
Deselected
Note
L
H
L
L
H
None
Deselected
Note
L
L
H
L
L
H
None
Deselected
Note
L
H
H
L
L
H
None
Read Cycle / Begin Burst
L
H
L
L
L
H
External
Read Cycle / Begin Burst
L
H
L
H
L
H
L
H
External
Read Cycle / Continue Burst
H
H
L
H
L
H
Next
Read Cycle / Continue Burst
H
H
L
H
L
H
Next
Read Cycle / Suspend Burst
H
H
H
H
L
H
Current
Read Cycle / Suspend Burst
H
H
H
H
L
H
Current
Write Cycle / Begin Burst
L
H
L
H
L
L
L
H
External
Write Cycle / Continue Burst
H
H
L
L
L
H
Next
Write Cycle / Continue Burst
H
H
L
L
L
H
Next
Write Cycle / Suspend Burst
H
H
H
L
L
H
Current
Write Cycle / Suspend Burst
H
H
H
L
L
H
Current
Note Deselect status is held until new "Begin Burst" entry.
Remarks 1.
: don't care
2. /WRITE = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) and /BWE are LOW
or /GW is LOW.
/WRITE = H means the following two cases.
(1) /BWE and /GW are HIGH.
(2) /BW1, /BW2, /BW3, /BW4 and /GW are HIGH, and /BWE is LOW.
10
Preliminary Data Sheet M15502EJ1V0DS
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y
Partial Truth Table for Write Enables
[



PD4442161-Y,






PD4442181-Y ]
Operation
/GW
/BWE
/BW1
/BW2
Read Cycle
H
H
Read Cycle
H
L
H
H
Write Cycle / Byte 1 Only
H
L
L
H
Write Cycle / All Bytes
H
L
L
L
Write Cycle / All Bytes
L
Remark
: don't care
[



PD4442321-Y,
PD4442361-Y ]
Operation
/GW
/BWE
/BW1
/BW2
/BW3
/BW4
Read Cycle
H
H
Read Cycle
H
L
H
H
H
H
Write Cycle / Byte 1 Only
H
L
L
H
H
H
Write Cycle / All Bytes
H
L
L
L
L
L
Write Cycle / All Bytes
L
Remark
: don't care
ZZ (Sleep) Truth Table
ZZ
Chip Status
0.2 V
Active
Open
Active
V
DD
-
0.2 V
Sleep
11
Preliminary Data Sheet M15502EJ1V0DS
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Note
Supply voltage (A version)
V
DD
0.5
+4.0
V
Supply voltage (C version)
V
DD
0.5
+3.0
V
Output supply voltage
V
DD
Q
0.5
V
DD
V
Input voltage
V
IN
0.5
V
DD
+ 0.5
V
1, 2
Input / Output voltage
V
I/O
0.5
V
DD
Q
+ 0.5
V
1, 2
Operating ambient temperature
T
A
40
+85
C
Storage temperature
T
stg
55
+125
C
Notes 1. 2.0 V (MIN.) (Pulse width : 2 ns)
2. V
DD
Q + 2.3 V (MAX.) (Pulse width : 2 ns)
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

Recommended DC Operating Conditions (T
A
= 40 to +85



C)
(A version)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Supply voltage
V
DD
3.135
3.3
3.465
V
2.5 V LVTTL interface
Output supply voltage
V
DD
Q
2.375
2.5
2.9
V
High level input voltage
V
IH
1.7
V
DD
Q
+ 0.3
V
Low level input voltage
V
IL
0.3
Note
+0.7
V
3.3 V LVTTL interface
Output supply voltage
V
DD
Q
3.135
3.3
3.465
V
High level input voltage
V
IH
2.0
V
DD
Q
+ 0.3
V
Low level input voltage
V
IL
0.3
Note
+0.8
V
Note 0.8 V (MIN.) (Pulse width : 2 ns)
(C version)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Supply voltage
V
DD
2.375
2.5
2.625
V
Output supply voltage
V
DD
Q
2.375
2.5
2.625
V
High level input voltage
V
IH
1.7
V
DD
Q
+ 0.3
V
Low level input voltage
V
IL
0.3
Note
+0.7
V
Note 0.8 V (MIN.) (Pulse width : 2 ns)
12
Preliminary Data Sheet M15502EJ1V0DS
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Note
Input leakage current
I
LI
V
IN
(except ZZ, MODE) = 0 V to V
DD
2
+2
A
I/O leakage current
I
LO
V
I/O
= 0 V to V
DD
Q, Outputs are disabled.
2
+2
A
Operating supply current
I
DD
Device selected, Cycle = MAX.
-A65Y
330
mA
V
IN
V
IL
or V
IN
V
IH
,
-A75Y, -C75Y
300
I
I/O
= 0 mA
-A85Y, -C85Y
280
I
DD1
Suspend cycle, Cycle = MAX.
150
/AC, /AP, /ADV, /GW, /BWEs
V
IH
,
V
IN
V
IL
or V
IN
V
IH
, I
I/O
= 0 mA
Standby supply current
I
SB
Device deselected, Cycle = 0 MHz,
30
mA
V
IN
V
IL
or V
IN
V
IH
, All inputs are static.
I
SB1
Device deselected, Cycle = 0 MHz,
12
V
IN
0.2 V or V
IN
V
DD
0.2 V,
V
I/O
0.2 V, All inputs are static.
I
SB2
Device deselected, Cycle = MAX.
150
V
IN
V
IL
or V
IN
V
IH
Power down supply current
I
SBZZ
ZZ
V
DD
0.2 V, V
I/O
V
DD
Q + 0.2 V
12
mA
2.5 V LVTTL interface
High level output voltage
V
OH
I
OH
= 2.0 mA
1.7
V
I
OH
= 1.0 mA
2.1
Low level output voltage
V
OL
I
OL
= +2.0 mA
0.7
V
I
OL
= +1.0 mA
0.4
3.3 V LVTTL interface
High level output voltage
V
OH
I
OH
= 4.0 mA
2.4
V
Low level output voltage
V
OL
I
OL
= +8.0 mA
0.4
V
Remark These DC characteristics are in common regardless product classification.

Capacitance (T
A
= 25



C, f = 1MHz)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input capacitance
C
IN
V
IN
= 0 V
4.5
pF
Input / Output capacitance
C
I/O
V
I/O
= 0 V
7.0
pF
Clock input capacitance
C
clk
V
clk
= 0 V
6.0
pF
Remark These parameters are not 100
%
tested.
13
Preliminary Data Sheet M15502EJ1V0DS
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
2.5 V LVTTL Interface
Input waveform (Rise / Fall time
2.4 ns)
Test points
V
SS
2.4 V
V
DD
Q/2
V
DD
Q/2
Output waveform
Test points
V
DD
Q/2
V
DD
Q/2
3.3 V LVTTL Interface
Input waveform (Rise / Fall time
3.0 ns)
Test points
V
SS
3.0 V
1.5 V
1.5 V
Output waveform
Test points
1.5 V
1.5 V
Output load condition
C
L
: 30 pF
5 pF (TKHQX1, TKHQX2, TGLQX, TGHQZ, TKHQZ)
Figure1 External load at test
V
T
= +1.2 V/+1.5 V
I/O (Output)
50
Z
O
= 50
C
L
Remark C
L
includes capacitances of the probe and jig, and stray capacitances.
14
Preliminary Data Sheet M15502EJ1V0DS
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y

Read and Write Cycle
Parameter
Symbol
-A65Y
-A75Y, -C75Y
-A85Y, -C85Y
Unit
Note
(133 MHz)
(117 MHz)
(100MHz)
Standard
Alias
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Cycle time
TKHKH
TCYC
7.5
8.6
10.0
ns
Clock access time
TKHQV
TCD
6.5
7.5
8.5
ns
Output enable access time
TGLQV
TOE
3.5
3.5
3.5
ns
Clock high to output active
TKHQX1
TDC1
2.5
2.5
2.5
ns
Clock high to output change
TKHQX2
TDC2
2.5
2.5
2.5
ns
Output enable to output active
TGLQX
TOLZ
0
0
0
ns
Output disable to output high-Z
TGHQZ
TOHZ
0
3.5
0
3.5
0
3.5
ns
Clock high to output high-Z
TKHQZ
TCZ
2.5
4.0
2.5
4.0
2.5
4.0
ns
Clock high pulse width
TKHKL
TCH
2.5
2.5
2.5
ns
Clock low pulse width
TKLKH
TCL
2.5
2.5
2.5
ns
Setup times Address
TAVKH
TAS
1.5
1.5
2.0
ns
Address status
TADSVKH
TSS
Data in
TDVKH
TDS
Write enable
TWVKH
TWS
Address advance TADVVKH
Chip enable
TEVKH
Hold times
Address
TKHAX
TAH
0.5
0.5
0.5
ns
Address status
TKHADSX
TSH
Data in
TKHDX
TDH
Write enable
TKHWX
TWH
Address advance TKHADVX
Chip enable
TKHEX
Power down entry time
TZZE
TZZE
7.5
8.6
10.0
ns
Power down recovery time
TZZR
TZZR
7.5
8.6
10.0
ns
15
Preliminary

Data Sheet
M15502E
J1V0DS
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-
Y
TKHKH
TKLKH
TKHAX
TWVKH
TKHWX
TKHEX
TGLQV
TGLQX
TKHQX2
TKHQZ
Q1(A1)
Q1(A2)
Q2(A2)
Q3(A2)
Q4(A2)
Q1(A3)
Hi-Z
A1
A2
A3
CLK
/AP
/AC
Address
/ADV
/CEs
Note
/G
Data In
/BWE
/BWs
TGHQZ
TKHQV
TKHKL
TKHADSX
TADSVKH
TAVKH
TEVKH
TADSVKH
TKHADSX
TADVVKH
TKHADVX
TWVKH
TKHWX
/GW
Data Out
READ CYCLE
Remark Qn(A2) refers to output from address A2. Q1-Q4 refer to outputs according to burst sequence.
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
Note
Q1(A2)
16
Preliminary

Data Sheet
M15502E
J1V0DS
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-
Y
TKHKH
TAVKH
TKHAX
TEVKH
TKHEX
D1(A1)
D1(A2)
D2(A2)
D2(A2)
D3(A2)
D4(A2)
D1(A3)
D2(A3)
D3(A3)
Hi-Z
TKHKL
TKLKH
A1
A2
A3
TDVKH
TKHDX
TKHADSX
TWVKH
TKHWX
CLK
/AP
/AC
Address
/ADV
/CEs
Note2
/G
Data In
/BWE
Note1
/BWs
/GW
Note1
Data Out
TADVVKH
TWVKH
TKHADVX
TKHWX
TADSVKH TKHADSX
TADSVKH
WRITE CYCLE
Notes
2.
All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1-/BW4 LOW.
1.
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
TGHQZ
17
Preliminary

Data Sheet
M15502E
J1V0DS
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-
Y
TKHKH
TKLKH
TKHKL
TAVKH
TEVKH
TKHEX
TKHQV
TGLQX
Q1(A1)
Q1(A3)
Q2(A3)
Q3(A3)
A3
A2
A1
TGHQZ
TKHQX1
TDVKH
TKHDX
Hi-Z
D1(A2)
TADSVKH TKHADSX
TKHAX
TADSVKH TKHADSX
CLK
/AP
/AC
Address
/ADV
/CEs
Note2
/G
Data In
/BWE
Note1
/BWs
/GW
Note1
Data Out
TWVKH
TKHWX
TWVKH
TKHWX
Q4(A3)
TADVVKH
TKHADVX
Notes
2.
All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1-/BW4 LOW.
1.
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
READ / WRITE CYCLE
18
Preliminary

Data Sheet
M15502E
J1V0DS
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-
Y
TKHKH
ZZ
TKLKH
A1
A2
TZZE
TZZR
Power Down (I
SBZZ
) State
Q2(A2)
TKHKL
CLK
/AP
/AC
Address
/ADV
/CEs
/G
/BWE
/BWs
/GW
Data Out
POWER DOWN (ZZ) CYCLE
Q1(A2)
Q1(A1)
Hi-Z
19
Preliminary

Data Sheet
M15502E
J1V0DS
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-
Y
TKHKH
Data Out
TKHKL
TKLKH
A1
A2
Power Down State (I
SB1
)
Note
Q1(A1)
Q1(A2)
Data In
CLK
/AP
/AC
Address
/ADV
/CE
/G
/BWE
/BWs
/GW
Q2(A2)
Hi-Z
STOP CLOCK CYCLE
Note V
IN
0.2 V or V
IN
V
DD
-
0.2 V, V
I/O
0.2 V
20
Preliminary Data Sheet M15502EJ1V0DS
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y
Package Drawing
100-PIN PLASTIC LQFP (14x20)
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
A
B
D
G
22.0
0.2
20.0
0.2
0.65 (T.P.)
0.575
J
16.0
0.2
K
C
14.0
0.2
I
0.13
1.0
0.2
L
0.5
0.2
F
0.825
N
P
Q
0.10
1.4
0.125
0.075
S100GF-65-8ET-1
S
1.7 MAX.
H
0.32
+
0.08
-
0.07
M
0.17
+
0.06
-
0.05
R
3
+
7
-
3
M
80
81
51
50
30
31
100
1
S
S
N
J
detail of lead end
C
D
A
B
R
K
M
L
P
I
S
Q
G
F
H
21
Preliminary Data Sheet M15502EJ1V0DS
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of the
PD4442161
-Y
, 4442181
-Y
, 4442321
-Y
and
4442361
-Y
.
Types of Surface Mount Devices
PD4442161
GF-Y
: 100-pin PLASTIC LQFP (14
20)
PD4442181
GF-Y
: 100-pin PLASTIC LQFP (14
20)
PD4442321
GF-Y :
100-pin PLASTIC LQFP (14
20)
PD4442361
GF-Y
: 100-pin PLASTIC LQFP (14
20)
22
Preliminary Data Sheet M15502EJ1V0DS
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y
[ MEMO ]
23
Preliminary Data Sheet M15502EJ1V0DS
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y
M8E 00. 4
The information in this document is current as of May, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
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Customers must check the quality grade of each semiconductor product before using it in a particular
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(Note)
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