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Datasheet: M15393EJ1V0DS00 (NEC)

 

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2001
MOS INTEGRATED CIRCUIT



PD4382323, 4382363
8M-BIT CMOS SYNCHRONOUS FAST SRAM
PIPELINED OPERATION
DOUBLE CYCLE DESELECT
Document No. M15393EJ1V0DS00 (1st edition)
Date Published February 2001 NS CP(K)
Printed in Japan
DATA SHEET
Description
The
PD4382323 is a 262,144-word by 32-bit and the
PD4382363 is a 262,144-word by 36-bit synchronous static RAM
fabricated with advanced CMOS technology using N-channel four-transistor memory cell.
The
PD4382323 and
PD4382363 integrates unique synchronous peripheral circuitry, 2-bit burst counter and output
buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input (CLK).
The
PD4382323 and
PD4382363 are suitable for applications which require synchronous operation, high speed, low
voltage, high density and wide bit configuration, such as cache and buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State ("Sleep"). In
the "Sleep" state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.
The
PD4382323 and
PD4382363 are packaged in 100-pin plastic LQFP with a 1.4 mm package thickness for high
density and low capacitive loading.
Features
3.3 V power supply
Synchronous operation
Internally self-timed write control
Burst read / write : Interleaved burst and linear burst sequence
Fully registered inputs and outputs for pipelined operation
Double-Cycle deselect timing
All registers triggered off positive clock edge
3.3 V LVTTL Compatible : All inputs and outputs
Fast clock access time : 3.8 ns (150 MHz), 4.0 ns (133 MHz)
Asynchronous output enable : /G
Burst sequence selectable : MODE
Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
Separate byte write enable : /BW1 - /BW4, /BWE
Global write enable : /GW
Three chip enables for easy depth expansion
Common I/O using three state outputs
2
Data Sheet M15393EJ1V0DS



PD4382323, 4382363
Ordering Information
Part number
Access
Clock
Core Supply
I/O
Package
Time
Frequency
Voltage
Interface
ns
MHz
V
V
PD4382323GF-A67
3.8
150
3.3 0.165
3.3
100-PIN PLASTIC LQFP (14 x 20)
PD4382323GF-A75
4.0
133
LVTTL
PD4382363GF-A67
3.8
150
PD4382363GF-A75
4.0
133
3
Data Sheet M15393EJ1V0DS



PD4382323, 4382363
Pin Configuration (Marking Side)
/
indicates active low signal.
100-PIN PLASTIC LQFP (14 x 20)
[



PD4382323GF,



PD4382363GF]
I/OP3, NC
I/O17
I/O18
V
DD
Q
V
SS
Q
I/O19
I/O20
I/O21
I/O22
V
SS
Q
V
DD
Q
I/O23
I/O24
NC
V
DD
NC
V
SS
I/O25
I/O26
V
DD
Q
V
SS
Q
I/O27
I/O28
I/O29
I/O30
V
SS
Q
V
DD
Q
I/O31
I/O32
I/OP4, NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/OP2, NC
I/O16
I/O15
V
DD
Q
V
SS
Q
I/O14
I/O13
I/O12
I/O11
V
SS
Q
V
DD
Q
I/O10
I/O9
V
SS
NC
V
DD
ZZ
I/O8
I/O7
V
DD
Q
V
SS
Q
I/O6
I/O5
I/O4
I/O3
V
SS
Q
V
DD
Q
I/O2
I/O1
I/OP1, NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6
A7
/CE
CE2
/BW4
/BW3
/BW2
/BW1
/CE2
V
DD
V
SS
CLK
/GW
/BWE
/G
/AC
/AP
/ADV
A8
A9
MODE
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
A17
A10
A11
A12
A13
A14
A15
A16
Remark Refer to Package Drawing for 1-pin index mark.
4
Data Sheet M15393EJ1V0DS



PD4382323, 4382363
Pin Identification
Symbol
Pin No.
Description
A0 - A17
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49, 50, 43
Synchronous Address Input
I/O1 - I/O32
52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74,
75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23,
24, 25, 28, 29
Synchronous Data In,
Synchronous / Asynchronous Data Out
I/OP1, NC
Note
51
Synchronous Data In (Parity),
I/OP2, NC
Note
80
Synchronous / Asynchronous Data Out (Parity)
I/OP3, NC
Note
1
I/OP4, NC
Note
30
/ADV
83
Synchronous Burst Address Advance Input
/AP
84
Synchronous Address Status Processor Input
/AC
85
Synchronous Address Status Controller Input
/CE, CE2, /CE2
98, 97, 92
Synchronous Chip Enable Input
/BWE1 - /BWE4, /BWE
93, 94, 95, 96, 87
Synchronous Byte Write Enable Input
/GW
88
Synchronous Global Write Input
/G
86
Asynchronous Output Enable Input
CLK
89
Clock Input
MODE
31
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
ZZ
64
Asynchronous Power Down State Input
V
DD
15, 41, 65, 91
Power Supply
V
SS
17, 40, 67, 90
Ground
V
DD
Q
4, 11, 20, 27, 54, 61, 70, 77
Output Buffer Power Supply
V
SS
Q
5, 10, 21, 26, 55, 60, 71, 76
Output Buffer Ground
NC
14, 16, 38, 39, 42, 66
No Connection
Note NC (No Connection) is used in the
PD4382323GF. I/OP1 - I/OP4 is used in the
PD4382363GF.
5
Data Sheet M15393EJ1V0DS



PD4382323, 4382363
Block Diagram
Address
Registers
Binary
Counter
and Logic
CLR
Q0
Q1
Byte 1
Write Register
Byte 1
Write Driver
8/9
Byte 2
Write Register
Byte 2
Write Driver
8/9
Byte 3
Write Register
Byte 3
Write Driver
8/9
Byte 4
Write Register
Byte 4
Write Driver
8/9
Enable
Register
Row and Column
Memory Matrix
1,024 rows
256
32 columns
(8,388,608 bits)
256
36 columns
(9,437,184 bits)
Output
Registers
Output
Buffers
Input
Registers
32/36
16
18
A0, A1
A1'
A0'
32/36
4
32/36
A0 - A17
MODE
/ADV
CLK
/AC
/AP
/BW1
/BW2
/BW3
/BW4
/BWE
/GW
/CE
CE2
/CE2
/G
I/O1 - I/O32
I/OP1 - I/OP4
ZZ
Power Down Control
Decoders
18
Burst Sequence
Interleaved Burst Sequence Table (MODE = Open or V
DD
)
External Address
A17 - A2, A1, A0
1st Burst Address
A17 - A2, A1, /A0
2nd Burst Address
A17 - A2, /A1, A0
3rd Burst Address
A17 - A2, /A1, /A0
Linear Burst Sequence Table (MODE = V
SS
)
External Address
A17 - A2, 0, 0
A17 - A2, 0, 1
A17 - A2, 1, 0
A17 - A2, 1, 1
1st Burst Address
A17 - A2, 0, 1
A17 - A2, 1, 0
A17 - A2, 1, 1
A17 - A2, 0, 0
2nd Burst Address
A17 - A2, 1, 0
A17 - A2, 1, 1
A17 - A2, 0, 0
A17 - A2, 0, 1
3rd Burst Address
A17 - A2, 1, 1
A17 - A2, 0, 0
A17 - A2, 0, 1
A17 - A2, 1, 0
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