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Datasheet: M14931EJ5V0DS00 (NEC)

 

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2000
MOS INTEGRATED CIRCUIT
MC-222254A-X
MCP (MULTI-CHIP PACKAGE) FLASH MEMORY AND SRAM
32M-BIT FLASH MEMORY AND 4M-BIT SRAM
DATA SHEET
Document No. M14931EJ5V0DS00 (5th edition)
Date Published July 2001 NS CP (K)
Printed in Japan
The mark
5
5
5
5
shows major revised points.
Description
The MC-222254A-X is a stacked type MCP (Multi-Chip Package) of 33,554,432 bits (BYTE mode : 4,194,304 words
by 8 bits, WORD mode : 2,097,152 words by 16 bits) flash memory and 4,194,304 bits (BYTE mode : 524,288 words
by 8 bits, WORD mode : 262,144 words by 16 bits) static RAM.
The MC-222254A-X is packaged in a 77-pin TAPE FBGA.
Features
General Features
Fast access time : t
ACC
= 85 ns (MAX.) (Flash Memory), t
AA
= 70 ns (MAX.) (SRAM)
Supply voltage : V
CC
f / V
CC
s = 2.7 to 3.6 V
Wide operating temperature : T
A
=
-
25 to +85
C
Flash Memory Features
Two bank organization enabling simultaneous execution of erase / program and read
Bank organization : 2 banks (16M bits + 16M bits)
Memory organization : 4,194,304 words
8 bits (BYTE mode)
2,097,152 words
16 bits (WORD mode)
Sector organization : 71 sectors (8K bytes / 4K words
8 sectors, 64K bytes / 32K words
63 sectors)
Boot sector allocated to the lowest address (sector)
3-state output
Automatic program
Program suspend / resume
Unlock bypass program
Automatic erase
Chip erase
Sector erase (sectors can be combined freely)
Erase suspend / resume
Program / Erase completion detection
Detection through data polling and toggle bits
Detection through RY (/BY) pin
Sector group protection
Any sector can be protected
Any protected sector can be temporary unprotected
Sectors can be used for boot application
Hardware reset and standby using /RESET pin
Automatic sleep mode
Boot block sector protect by /WP (ACC) pin
Conforms to common flash memory interface (CFI)
Extra One Time Protect Sector provided
Data Sheet M14931EJ5V0DS
2
MC-222254A-X
SRAM Features
Memory organization : 524,288 words
8 bits (BYTE mode)
262,144 words
16 bits (WORD mode)
Supply current : At operating : 40 mA (MAX.)
At standby : 7
A (MAX.)
Two Chip Enable inputs : /CE1s, CE2s
Byte data control : /LB, /UB
Byte data select : CIOs
Low V
CC
data retention : 1.0 to 3.6 V
Ordering Information
Part number
Flash Memory
Flash Memory
SRAM
Package
Boot sector
Access time
Access time
ns (MAX.)
ns (MAX.)
MC-222254AF9-B85X-BT3
Lowest address (sector)
85
70
77-pin TAPE FBGA (12
7)
(B type)
Data Sheet M14931EJ5V0DS
3
MC-222254A-X
Pin Configuration
/xxx indicates active low signal.
77-pin TAPE FBGA (12



7)
Top View
V
SS
I/O9
I/O5
A7
/OE
I/O7
I/O4
I/O0
A6
A18
A11
A8
A5
I/O8
I/O12
A13
A17
SA
/CEf
I/O10
V
CC
f
/WE
V
CC
s
A16
I/O11
RY(/BY)
/RESET
A12
I/O6
I/O13
A9
A15
A19
I/O14
/CE1s
I/O15, A-1
I/O1
A1
A2
A4
A10
CIOs
I/O2
A0
A3
CE2s
A20
A14
/LB
CIOf
/WP(ACC)
/UB
I/O3
NC
NC
V
SS
Top View
Bottom View
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
P N M L K J H G F E D C B A
A B C D E F G H J K L M N P
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Common Pins
A0 - A17
: Address inputs
I/O0 - I/O15 : Data inputs / outputs
/OE
: Output Enable
/WE
: Write Enable
V
SS
: Ground
NC
Note
: No Connection
Flash Memory Pins
A18 - A20 : Address inputs
I/O15, A
-
1 : Data inputs / outputs 15 (WORD mode)
LSB address input (BYTE mode)
/CEf
: Chip Enable
RY (/BY)
: Ready (Busy) output
/RESET
: Hardware reset input
V
CC
f
: Supply Voltage
/WP(ACC) : Hardware Write Protect (Acceleration)
CIOf
: Selects 8-bit or 16-bit mode
SRAM Pins
SA
: Address input (A18 for SRAM)
/CE1s
: Chip Enable 1
CE2s
: Chip Enable 2
V
CC
s
: Supply Voltage
/LB, /UB
: Byte data select
CIOs
: Selects 8-bit or 16-bit mode
Note Some signals can be applied because this pin is not internally connected.
Remark Refer to Package Drawing for the index mark.
Data Sheet M14931EJ5V0DS
4
MC-222254A-X
Block Diagram
32 M-bit Flash Memory
4,194,304 words by 8 bits
2,097,152 words by 16 bits
SA
/WE
/OE
/CE1s
/RESET
/CEf
I/O0 - I/O15, A-1
A0 - A20
4 M-bit SRAM
524,288 words by 8 bits
262,144 words by 16 bits
RY (/BY)
A0 - A17
A0 - A20
V
CC
f
V
SS
V
CC
s
V
SS
CE2s
/LB
/UB
CIOs
CIOf
/WP(ACC)
Data Sheet M14931EJ5V0DS
5
MC-222254A-X
Bus Operations Table
Operation
Flash Memory
SRAM
Common
/RESET /CEf CIOf /WP(ACC) /CE1
S
CE2
S
/LB
/UB
CIOs /OE /WE I/O0 - I/O7 I/O8-I/O15
Full standby
H
H
H
Hi-Z
Hi-Z
L
H
H
Output disable
H
L
L
H
H
H
Hi-Z
Hi-Z
Read (Flash
BYTE mode
H
L
L
Note 2
L
H
Data Out
Hi-Z
Memory
Note 1
) WORD mode
H
Data Out
Data Out
Write (Flash
BYTE mode
H
L
L
Note 2
H
L
Data In
Hi-Z
Memory)
WORD mode
H
Data In
Data In
Temporary sector group
V
ID
Note 2
Hi-Z or
Hi-Z or
unprotect
Data In/Out Data In/Out
Boot block sector protect
L
Hi-Z or
Data In/Out
Hi-Z or
Data In/Out
Flash Memory hardware reset
L
Hi-Z
Hi-Z
Read (SRAM)
BYTE mode
Note 3
L
H
L
L
H
Data Out
Hi-Z
WORD mode
Note 3
L
H
L
L
H
L
H
Data Out
Data Out
H
Hi-Z
H
L
Hi-Z
Data Out
Write (SRAM)
BYTE mode
Note 3
L
H
L
L
Data In
Hi-Z
WORD mode
Note 3
L
H
L
L
H
L
Data In
Data In
H
Hi-Z
H
L
Hi-Z
Data In
Caution Other operations except for indicated in this table are inhibited.
Notes 1. When /OE = V
IL
, V
IL
can be applied to /WE. When /OE = V
IH
, a write operation is started.
2. SRAM should be Standby.
3. Flash Memory should be Standby or Hardware reset.
Remarks 1. H : V
IH
, L : V
IL
,
: V
IH
or V
IL
2. Sector group protection and read the product ID are using a command.
3. Refer to DUAL OPERATION FLASH MEMORY 32M BITS A SERIES Information (M14914E) for the
flash memory bus operations.
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