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Datasheet: M14671EJ7V0DS00 (NEC)

 

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2000
MOS INTEGRATED CIRCUIT



PD442012A-X
2M-BIT CMOS STATIC RAM
128K-WORD BY 16-BIT
EXTENDED TEMPERATURE OPERATION
DATA SHEET
Document No. M14671EJ7V0DS00 (7th edition)
Date Published July 2001 NS CP (K)
Printed in Japan
The mark
5
5
5
5
shows major revised points.
Description
The
PD442012A-X is a high speed, low power, 2,097,152 bits (131,072 words by 16 bits) CMOS static RAM.
The
PD442012A-X has two chip enable pins (/CE1, CE2) to extend the capacity.
The
PD442012A-X is packed in 48-pin PLASTIC TSOP (I) (Normal bent).
Features
131,072 words by 16 bits organization
Fast access time : 50, 55, 70, 85, 100, 120 ns (MAX.)
Byte data control : /LB (I/O1 - I/O8), /UB (I/O9 - I/O16)
Low voltage operation
(BB version : V
CC
= 2.7 to 3.6 V, BC version : V
CC
= 2.2 to 3.6 V, DD version : V
CC
= 1.8 to 2.2 V)
Low V
CC
data retention : 1.0 V (MIN.)
Operating ambient temperature : T
A
= 25 to +85 C
Output Enable input for easy application
Two Chip Enable inputs : /CE1, CE2
Part number
Access time
Operating supply Operating ambient
Supply current
ns (MAX.)
voltage
temperature
At operating
At standby
At data retention
V
C
mA (MAX.)
A (MAX.)
A (MAX.)
PD442012A-BBxxX
50
Note 1
, 55, 70, 85
2.7 to 3.6
-
25 to +85
30
Note 2
4
2
35
Note 3
40
Note 4
PD442012A-BCxxX
70, 85, 100
2.2 to 3.6
30
PD442012A-DDxxX
85, 100, 120
1.8 to 2.2
15
3
Notes 1. V
CC
3.0 V
2. Cycle time
70 ns
3. Cycle time = 55 ns
4. Cycle time = 50 ns
5
5
5
5
5
5
5
Data Sheet M14671EJ7V0DS
2



PD442012A-X
Ordering Information
Part number
Package
Access time
Operating
Operating
Remark
ns (MAX.)
supply voltage
temperature
V
C
PD442012AGY-BB55X-MJH
48-pin PLASTIC TSOP (I)
55, 50
Note
2.7 to 3.6
-
25 to +85
BB version
PD442012AGY-BB70X-MJH
(12
18) (Normal bent)
70
PD442012AGY-BB85X-MJH
85
PD442012AGY-BC70X-MJH
70
2.2 to 3.6
BC version
PD442012AGY-BC85X-MJH
85
PD442012AGY-BC10X-MJH
100
PD442012AGY-DD85X-MJH
85
1.8 to 2.2
DD version
PD442012AGY-DD10X-MJH
100
PD442012AGY-DD12X-MJH
120
Note V
CC
3.0 V
5
5
Data Sheet M14671EJ7V0DS
3



PD442012A-X
Pin Configuration (Marking Side)
/xxx indicates active low signal.
48-pin PLASTIC TSOP (I) (12



18) (Normal bent)
[



PD442012AGY-BBxxX-MJH ]
[



PD442012AGY-BCxxX-MJH ]
[



PD442012AGY-DDxxX-MJH ]
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
/WE
CE2
IC
/UB
/LB
NC
NC
A7
A6
A5
A4
A3
A2
A1
A16
NC
GND
I/O16
I/O8
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
V
CC
I/O12
I/O4
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
/OE
GND
/CE1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A0 - A16
: Address inputs
I/O1 - I/O16 : Data inputs / outputs
/CE1, CE2
: Chip Enable 1, 2
/WE
: Write Enable
/OE
: Output Enable
/LB, /UB
: Byte data select
V
CC
: Power supply
GND
: Ground
NC
: No Connection
IC
Note
: Internal Connection
Note Leave this pin unconnected or connect to GND.
Remark Refer to Package Drawing for the 1-pin index mark.
Data Sheet M14671EJ7V0DS
4



PD442012A-X
Block Diagram
Address buffer
Address
buffer
Row
decoder
Memory cell array
2,097,152 bits
Input data
controller
A0
A16
I/O9 - I/O16
/CE1
/WE
/OE
CE2
/UB
/LB
Output data
controller
I/O1 - I/O8
V
CC
GND
Sense amplifier /
Switching circuit
Column decoder
Data Sheet M14671EJ7V0DS
5



PD442012A-X
Truth Table
/CE1
CE2
/OE
/WE
/LB
/UB
Mode
I/O
Supply current
I/O1 - I/O8
I/O9 - I/O16
H
Not selected
High impedance
High impedance
I
SB
L
Not selected
High impedance
High impedance
H
H
Not selected
High impedance
High impedance
L
H
H
H
L
Output disable
High impedance
High impedance
I
CCA
L
Output disable
High impedance
High impedance
L
H
L
L
Word read
D
OUT
D
OUT
L
H
Lower byte read
D
OUT
High impedance
H
L
Upper byte read
High impedance
D
OUT
L
L
L
Word write
D
IN
D
IN
L
H
Lower byte write
D
IN
High impedance
H
L
Upper byte write
High impedance
D
IN
Remark
: V
IH
or V
IL
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