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Datasheet: M14670EJ6V0DS00 (NEC)

 

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2000
MOS INTEGRATED CIRCUIT



PD442002-X
2M-BIT CMOS STATIC RAM
128K-WORD BY 16-BIT
EXTENDED TEMPERATURE OPERATION
DATA SHEET
Document No. M14670EJ6V0DS00 (6th edition)
Date Published July 2001 NS CP (K)
Printed in Japan
The mark
5
5
5
5
shows major revised points.
Description
The
PD442002-X is a high speed, low power, 2,097,152 bits (131,072 words by 16 bits) CMOS static RAM.
The
PD442002-X is packed in 48-pin TAPE FBGA.
Features
131,072 words by 16 bits organization
Fast access time : 50, 55, 70, 85, 100, 120 ns (MAX.)
Byte data control : /LB (I/O1 - I/O8), /UB (I/O9 - I/O16)
Low voltage operation
(BB version : V
CC
= 2.7 to 3.6 V, BC version : V
CC
= 2.2 to 3.6 V, DD version : V
CC
= 1.8 to 2.2 V)
Low V
CC
data retention : 1.0 V (MIN.)
Operating ambient temperature : T
A
= 25 to +85 C
Output Enable input for easy application
Part number
Access time
Operating supply Operating ambient
Supply current
ns (MAX.)
voltage
temperature
At operating
At standby
At data retention
V
C
mA (MAX.)
A (MAX.)
A (MAX.)
PD442002-BBxxX
50
Note 1
, 55, 70, 85
2.7 to 3.6
-
25 to +85
30
Note 2
4
2
35
Note 3
40
Note 4
PD442002-BCxxX
70, 85, 100
2.2 to 3.6
30
PD442002-DDxxX
85, 100, 120
1.8 to 2.2
15
3
Notes 1. V
CC
3.0 V
2. Cycle time
70 ns
3. Cycle time = 55 ns
4. Cycle time = 50 ns
5
5
5
5
5
5
5
Data Sheet M14670EJ6V0DS
2



PD442002-X
Ordering Information
Part number
Package
Access time
Operating
Operating
Remark
ns (MAX.)
supply voltage
temperature
V
C
PD442002F9-BB55X-BC1
48-pin TAPE FBGA (6
8)
55, 50
Note
2.7 to 3.6
-
25 to +85
BB version
PD442002F9-BB70X-BC1
70
PD442002F9-BB85X-BC1
85
PD442002F9-BC70X-BC1
70
2.2 to 3.6
BC version
PD442002F9-BC85X-BC1
85
PD442002F9-BC10X-BC1
100
PD442002F9-DD85X-BC1
85
1.8 to 2.2
DD version
PD442002F9-DD10X-BC1
100
PD442002F9-DD12X-BC1
120
Note V
CC
3.0 V
Marking Image
Part number
Marking (XX)
PD442002F9-BB55X-BC1
B1
PD442002F9-BB70X-BC1
B2
PD442002F9-BB85X-BC1
B3
PD442002F9-BC70X-BC1
C2
PD442002F9-BC85X-BC1
C3
PD442002F9-BC10X-BC1
C4
PD442002F9-DD85X-BC1
D3
PD442002F9-DD10X-BC1
D4
PD442002F9-DD12X-BC1
D5
J
S2M0-XX
INDEX MARK
Lot No.
5
5
Data Sheet M14670EJ6V0DS
3



PD442002-X
Pin Configuration
/xxx indicates active low signal.
48-pin TAPE FBGA (6



8)
[



PD442002F9-BBxxX-BC1 ]
[



PD442002F9-BCxxX-BC1 ]
[



PD442002F9-DDxxX-BC1 ]
A
B
C
D
E
F
G
H
1
2
3
4
5
6
Bottom View
6
5
4
3
2
1
Top View
1
2
3
4
5
6
6
5
4
3
2
1
A
/LB
/OE
A0
A1
A2
NC
A
NC
A2
A1
A0
/OE
/LB
B
I/O9
/UB
A3
A4
/CS
I/O1
B
I/O1
/CS
A4
A3
/UB
I/O9
C
I/O10
I/O11
A5
A6
I/O2
I/O3
C
I/O3
I/O2
A6
A5
I/O11
I/O10
D
GND
I/O12
NC
A7
I/O4
V
CC
D
V
CC
I/O4
A7
NC
I/O12
GND
E
V
CC
I/O13
NC
A16
I/O5
GND
E
GND
I/O5
A16
NC
I/O13
V
CC
F
I/O15
I/O14
A14
A15
I/O6
I/O7
F
I/O7
I/O6
A15
A14
I/O14
I/O15
G
I/O16
NC
A12
A13
/WE
I/O8
G
I/O8
/WE
A13
A12
NC
I/O16
H
NC
A8
A9
A10
A11
NC
H
NC
A11
A10
A9
A8
NC
A0 - A16
: Address inputs
I/O1 - I/O16 : Data inputs / outputs
/CS
: Chip Select
/WE
: Write Enable
/OE
: Output Enable
/LB, /UB
: Byte data select
V
CC
: Power supply
GND
: Ground
NC
: No Connection
Remark Refer to Package Drawing for the index mark.
Data Sheet M14670EJ6V0DS
4



PD442002-X
Block Diagram
Address buffer
Address
buffer
Row
decoder
Memory cell array
2,097,152 bits
Input data
controller
A0
A16
I/O9 - I/O16
Column decoder
/CS
/WE
/OE
/UB
/LB
Output data
controller
I/O1 - I/O8
V
CC
GND
Sense amplifier /
Switching circuit
Data Sheet M14670EJ6V0DS
5



PD442002-X
Truth Table
/CS
/OE
/WE
/LB
/UB
Mode
I/O
Supply current
I/O1 - I/O8
I/O9 - I/O16
H
Not selected
High impedance
High impedance
I
SB
H
H
Not selected
High impedance
High impedance
L
H
H
L
Output disable
High impedance
High impedance
I
CCA
L
Output disable
High impedance
High impedance
L
H
L
L
Word read
D
OUT
D
OUT
L
H
Lower byte read
D
OUT
High impedance
H
L
Upper byte read
High impedance
D
OUT
L
L
L
Word write
D
IN
D
IN
L
H
Lower byte write
D
IN
High impedance
H
L
Upper byte write
High impedance
D
IN
Remark
: V
IH
or V
IL
Data Sheet M14670EJ6V0DS
6



PD442002-X
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
Product
Rating
Unit
Supply voltage
V
CC
PD442002-BBxxX,
PD442002-BCxxX
0.5
Note
to +4.0
V
PD442002-DDxxX
0.5
Note
to +2.7
Input / Output voltage
V
T
PD442002-BBxxX,
PD442002-BCxxX
0.5
Note
to V
CC
+0.4 (4.0 V MAX.)
V
PD442002-DDxxX
0.5
Note
to V
CC
+0.4 (2.7 V MAX.)
Operating ambient temperature
T
A
25 to +85
C
Storage temperature
T
stg
55 to +125
C
Note 3.0 V (MIN.) (Pulse width : 30 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
PD442002-BBxxX
PD442002-BCxxX
PD442002-DDxxX
Unit
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Supply voltage
V
CC
2.7
3.6
2.2
3.6
1.8
2.2
V
High level input voltage
V
IH
2.7 V
V
CC
3.6 V
2.4
V
CC
+0.4
2.4
V
CC
+0.4
V
2.2 V
V
CC
< 2.7 V
2.0
V
CC
+0.3
1.8 V
V
CC
< 2.2 V
1.6
V
CC
+0.2
Low level input voltage
V
IL
0.3
Note
+0.5
0.3
Note
+0.4
0.2
Note
+0.2
V
Operating ambient
T
A
25
+85
25
+85
25
+85
C
temperature
Note 1.0 V (MIN.) (Pulse width : 20 ns)
Capacitance (T
A
= 25



C, f = 1 MHz)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input capacitance
C
IN
V
IN
= 0 V
8
pF
Input / Output capacitance
C
I/O
V
I/O
= 0 V
10
pF
Remarks 1. V
IN
: Input voltage
V
I/O
: Input / Output voltage
2. These parameters are not 100% tested.
Data Sheet M14670EJ6V0DS
7



PD442002-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2)
Parameter
Symbol
Test condition
PD442002-BBxxX
Unit
MIN.
TYP.
MAX.
Input leakage current
I
LI
V
IN
= 0 V to V
CC
1.0
+1.0
A
I/O leakage current
I
LO
V
I/O
= 0 V to V
CC
, /CS = V
IH
or
1.0
+1.0
A
/WE = V
IL
or /OE = V
IH
Operating supply current
I
CCA1
/CS = V
IL
,
Cycle time = 50 ns
40
mA
I
I/O
= 0 mA,
Cycle time = 55 ns
35
Minimum cycle time
Cycle time
70 ns
30
I
CCA2
/CS = V
IL
, I
I/O
= 0 mA, Cycle time =
4
I
CCA3
/CS
0.2 V, Cycle time = 1
s, I
I/O
= 0 mA,
4
V
IL
0.2 V, V
IH
V
CC
0.2 V
Standby supply current
I
SB
/CS = V
IH
or /LB = /UB = V
IH
0.6
mA
I
SB1
/CS
V
CC
0.2 V
0.3
4
A
I
SB2
/LB = /UB
V
CC
0.2 V, /CS
0.2 V
0.3
4
High level output voltage
V
OH
I
OH
= 0.5 mA
2.4
V
Low level output voltage
V
OL
I
OL
= 1.0 mA
0.4
V
Remarks 1. V
IN
: Input voltage
V
I/O
: Input / Output voltage
2. These DC characteristics are in common regardless of product classification.
5
5
5
Data Sheet M14670EJ6V0DS
8



PD442002-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2)
Parameter
Symbol
Test condition
PD442002-BCxxX
PD442002-DDxxX
Unit
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
Input leakage current
I
LI
V
IN
= 0 V to V
CC
1.0
+1.0
1.0
+1.0
A
I/O leakage current
I
LO
V
I/O
= 0 V to V
CC
, /CS = V
IH
or
1.0
+1.0
1.0
+1.0
A
/WE = V
IL
or /OE = V
IH
Operating supply current
I
CCA1
/CS = V
IL
, I
I/O
= 0 mA,
30
mA
Minimum cycle time
V
CC
2.7 V
25
V
CC
2.2 V
15
I
CCA2
/CS = V
IL
, I
I/O
= 0 mA,
4
Cycle time =
V
CC
2.7 V
2
V
CC
2.2 V
1
I
CCA3
/CS
0.2 V, Cycle time = 1
s,
4
I
I/O
= 0 mA, V
IL
0.2 V,
V
CC
2.7 V
3
V
IH
V
CC
0.2 V
V
CC
2.2 V
3
Standby supply current
I
SB
/CS = V
IH
or /LB = /UB = V
IH
0.6
mA
V
CC
2.7 V
0.6
V
CC
2.2 V
0.6
I
SB1
/CS
V
CC
0.2 V
0.3
4
A
V
CC
2.7 V
0.25
3.5
V
CC
2.2 V
0.2
3
I
SB2
/LB = /UB
V
CC
0.2 V,
0.3
4
/CS
0.2 V
V
CC
2.7 V
0.25
3.5
V
CC
2.2 V
0.2
3
High level output voltage
V
OH
I
OH
= 0.5 mA
2.4
V
V
CC
2.7 V
1.8
V
CC
2.2 V
1.5
Low level output voltage
V
OL
I
OL
= 1.0 mA
0.4
V
V
CC
2.7 V
0.4
V
CC
2.2 V
0.4
Remarks 1. V
IN
: Input voltage
V
I/O
: Input / Output voltage
2. These DC characteristics are in common regardless of product classification.
5
5
5
5
5
5
5
5
Data Sheet M14670EJ6V0DS
9



PD442002-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[



PD442002-BB55X,



PD442002-BB70X,



PD442002-BB85X ]
Input Waveform (Rise and Fall Time



5 ns)
0.1
V
CC
0.9
V
CC
Test points
V
CC
/2
V
CC
/2
Output Waveform
Test points
V
CC
/2
V
CC
/2
Output Load
1TTL + 50 pF
[



PD442002-BC70X,



PD442002-BC85X,



PD442002-BC10X ]
Input Waveform (Rise and Fall Time



5 ns)
0.1
V
CC
0.9
V
CC
Test points
V
CC
/2
V
CC
/2
Output Waveform
Test points
V
CC
/2
V
CC
/2
Output Load
1TTL + 30 pF
[



PD442002-DD85X,



PD442002-DD10X,



PD442002-DD12X ]
Input Waveform (Rise and Fall Time



5 ns)
0.1
V
CC
0.9
V
CC
Test points
V
CC
/2
V
CC
/2
Output Waveform
Test points
V
CC
/2
V
CC
/2
Output Load
1TTL + 30 pF
Data Sheet M14670EJ6V0DS
10



PD442002-X
Read Cycle (1/3) (BB version)
Parameter
Symbol
PD442002-BB55X
PD442002
PD442002
Unit
Condition
V
CC
3.0 V
-BB70X
-BB85X
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read cycle time
t
RC
50
55
70
85
ns
Address access time
t
AA
50
55
70
85
ns
Note 1
/CS access time
t
ACS
50
55
70
85
ns
/OE to output valid
t
OE
30
30
35
40
ns
/LB, /UB to output valid
t
BA
50
55
70
85
ns
Output hold from address change
t
OH
10
10
10
10
ns
/CS to output in low impedance
t
LZ
10
10
10
10
ns
Note 2
/OE to output in low impedance
t
OLZ
5
5
5
5
ns
/LB, /UB to output in low impedance
t
BLZ
10
10
10
10
ns
/CS to output in high impedance
t
HZ
20
20
25
30
ns
/OE to output in high impedance
t
OHZ
20
20
25
30
ns
/LB, /UB to output in high impedance
t
BHZ
20
20
25
30
ns
Notes 1. The output load is 1TTL + 50 pF.
2. The output load is 1TTL + 5 pF.
Read Cycle (2/3) (BC version)
Parameter
Symbol
PD442002
PD442002
PD442002
Unit
Condition
-BC70X
-BC85X
-BC10X
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read cycle time
t
RC
70
85
100
ns
Address access time
t
AA
70
85
100
ns
Note 1
/CS access time
t
ACS
70
85
100
ns
/OE to output valid
t
OE
35
40
50
ns
/LB, /UB to output valid
t
BA
70
85
100
ns
Output hold from address change
t
OH
10
10
10
ns
/CS to output in low impedance
t
LZ
10
10
10
ns
Note 2
/OE to output in low impedance
t
OLZ
5
5
5
ns
/LB, /UB to output in low impedance
t
BLZ
10
10
10
ns
/CS to output in high impedance
t
HZ
25
30
35
ns
/OE to output in high impedance
t
OHZ
25
30
35
ns
/LB, /UB to output in high impedance
t
BHZ
25
30
35
ns
Notes 1. The output load is 1TTL + 30 pF.
2. The output load is 1TTL + 5 pF.
5
Data Sheet M14670EJ6V0DS
11



PD442002-X
Read Cycle (3/3) (DD version)
Parameter
Symbol
PD442002
PD442002
PD442002
Unit
Condition
-DD85X
-DD10X
-DD12X
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read cycle time
t
RC
85
100
120
ns
Address access time
t
AA
85
100
120
ns
Note 1
/CS access time
t
ACS
85
100
120
ns
/OE to output valid
t
OE
40
50
60
ns
/LB, /UB to output valid
t
BA
85
100
120
ns
Output hold from address change
t
OH
10
10
10
ns
/CS to output in low impedance
t
LZ
10
10
10
ns
Note 2
/OE to output in low impedance
t
OLZ
5
5
5
ns
/LB, /UB to output in low impedance
t
BLZ
10
10
10
ns
/CS to output in high impedance
t
HZ
30
35
40
ns
/OE to output in high impedance
t
OHZ
30
35
40
ns
/LB, /UB to output in high impedance
t
BHZ
30
35
40
ns
Notes 1. The output load is 1TTL + 30 pF.
2. The output load is 1TTL + 5 pF.
Data Sheet M14670EJ6V0DS
12



PD442002-X
Read Cycle Timing Chart
t
RC
t
OH
t
HZ
t
BLZ
t
BA
t
LZ
t
ACS
t
BHZ
t
AA
High impedance
Data out
/LB, /UB (Input)
/CS (Input)
Address (Input)
I/O (Output)
t
OLZ
t
OE
t
OHZ
/OE (Input)
Remark In read cycle, /WE should be fixed to high level.
Data Sheet M14670EJ6V0DS
13



PD442002-X
Write Cycle (1/3) (BB version)
Parameter
Symbol
PD442002-BB55X
PD442002
PD442002
Unit
Condition
V
CC
3.0 V
-BB70X
-BB85X
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Write cycle time
t
WC
50
55
70
85
ns
/CS to end of write
t
CW
45
50
55
70
ns
/LB, /UB to end of write
t
BW
45
50
55
70
ns
Address valid to end of write
t
AW
45
50
55
70
ns
Address setup time
t
AS
0
0
0
0
ns
Write pulse width
t
WP
40
45
50
55
ns
Write recovery time
t
WR
0
0
0
0
ns
Data valid to end of write
t
DW
25
25
30
35
ns
Data hold time
t
DH
0
0
0
0
ns
/WE to output in high impedance
t
WHZ
20
20
25
30
ns
Note
Output active from end of write
t
OW
5
5
5
5
ns
Note The output load is 1TTL + 5 pF.
Write Cycle (2/3) (BC version)
Parameter
Symbol
PD442002
PD442002
PD442002
Unit
Condition
-BC70X
-BC85X
-BC10X
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Write cycle time
t
WC
70
85
100
ns
/CS to end of write
t
CW
55
70
80
ns
/LB, /UB to end of write
t
BW
55
70
80
ns
Address valid to end of write
t
AW
55
70
80
ns
Address setup time
t
AS
0
0
0
ns
Write pulse width
t
WP
50
55
60
ns
Write recovery time
t
WR
0
0
0
ns
Data valid to end of write
t
DW
30
35
40
ns
Data hold time
t
DH
0
0
0
ns
/WE to output in high impedance
t
WHZ
25
30
35
ns
Note
Output active from end of write
t
OW
5
5
5
ns
Note The output load is 1TTL + 5 pF.
5
Data Sheet M14670EJ6V0DS
14



PD442002-X
Write Cycle (3/3) (DD version)
Parameter
Symbol
PD442002
PD442002
PD442002
Unit
Condition
-DD85X
-DD10X
-DD12X
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Write cycle time
t
WC
85
100
120
ns
/CS to end of write
t
CW
70
80
100
ns
/LB, /UB to end of write
t
BW
70
80
100
ns
Address valid to end of write
t
AW
70
80
100
ns
Address setup time
t
AS
0
0
0
ns
Write pulse width
t
WP
55
60
85
ns
Write recovery time
t
WR
0
0
0
ns
Data valid to end of write
t
DW
35
40
60
ns
Data hold time
t
DH
0
0
0
ns
/WE to output in high impedance
t
WHZ
30
35
40
ns
Note
Output active from end of write
t
OW
5
5
5
ns
Note The output load is 1TTL + 5 pF.
Data Sheet M14670EJ6V0DS
15



PD442002-X
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
t
CW
t
BW
t
WHZ
t
DW
t
DH
t
OW
Indefinite data out
High
impe-
dance
High
impe-
dance
Data in
Indefinite data out
Address (Input)
/CS (Input)
/LB, /UB (Input)
I/O (Input / Output)
t
AW
t
WP
t
AS
t
WR
/WE (Input)
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remarks 1. Write operation is done during the overlap time of a low level /CS, a low level /WE and a low
level /LB (or low level /UB).
2. If /CS changes to low level at the same time or after the change of /WE to low level, the I/O pins
will remain high impedance state.
3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
read operation is executed. Therefore /OE should be at high level to make the I/O pins high
impedance.
Data Sheet M14670EJ6V0DS
16



PD442002-X
Write Cycle Timing Chart 2 (/CS Controlled)
t
WC
t
AS
t
CW
t
DW
t
DH
Data in
High impedance
Address (Input)
/CS (Input)
/LB, /UB (Input)
I/O (Input)
High
impedance
t
AW
t
WP
t
WR
/WE (Input)
t
BW
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB (or
low level /UB).
Data Sheet M14670EJ6V0DS
17



PD442002-X
Write Cycle Timing Chart 3 (/LB, /UB Controlled)
t
WC
t
DW
t
DH
Data in
High impedance
Address (Input)
/LB, /UB (Input)
I/O (Input)
High
impedance
t
AW
t
WP
t
WR
/WE (Input)
t
AS
t
BW
/CS (Input)
t
CW
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB (or
low level /UB).
Data Sheet M14670EJ6V0DS
18



PD442002-X
Low V
CC
Data Retention Characteristics (T
A
= 25 to +85



C)
Parameter
Symbol
Test Condition
PD442002
PD442002
PD442002
Unit
-BBxxX
-BCxxX
-DDxxX
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX.
Data retention
V
CCDR1
/CS
V
CC
-
0.2 V
1.0
3.6
1.0
3.6
1.0
2.2
V
supply voltage
V
CCDR2
/LB = /UB
V
CC
-
0.2 V,
1.0
3.6
1.0
3.6
1.0
2.2
/CS
0.2 V
Data retention
I
CCDR1
V
CC
= 1.2 V, /CS
V
CC
-
0.2 V
0.15
2
0.15
2
0.15
2
A
supply current
I
CCDR2
V
CC
= 1.2 V, /LB = /UB
V
CC
-
0.2 V,
0.15
2
0.15
2
0.15
2
/CS
0.2 V
Chip deselection
t
CDR
0
0
0
ns
to data retention
mode
Operation
t
R
t
RC
Note
t
RC
Note
t
RC
Note
ns
recovery time
Note t
RC
: Read cycle time
Data Sheet M14670EJ6V0DS
19



PD442002-X
Data Retention Timing Chart
(1) /CS Controlled
V
IH
(MIN.)
V
CCDR
(MIN.)
V
IL
(MAX.)
/CS
/CS
V
CC
0.2 V
GND
V
CC
(MIN.)
Note
t
CDR
Data retention mode
t
R
V
CC
Note BB version : 2.7 V, BC version : 2.2 V, DD version : 1.8 V
Remark On the data retention mode by controlling /CS, the other pins (Address, I/O, /WE, /OE, /LB, /UB) can be
in high impedance state.
(2) /LB, /UB Controlled
t
CDR
Data retention mode
V
IH
(MIN.)
V
CCDR
(MIN.)
V
IL
(MAX.)
t
R
/LB, /UB
/LB, /UB
V
CC
0.2 V
GND
V
CC
V
CC
(MIN.)
Note
Note BB version : 2.7 V, BC version : 2.2 V, DD version : 1.8 V
Remark On the data retention mode by controlling /LB and /UB, the input level of /CS must be
V
CC
-
0.2 V
or
0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state.
Data Sheet M14670EJ6V0DS
20



PD442002-X
Package Drawing
48-PIN TAPE FBGA (6x8)
ITEM
MILLIMETERS
D
8.0
0.1
6.0
0.1
A
b
x
e
0.96
0.10
A1
0.25
0.05
w
E
0.2
0.75
P48F9-75-BC1-1
A2
0.71
y
0.1
y1
0.1
0.35
0.05
0.08
ZD
1.375
ZE
1.125
A
A1
ZD
A2
INDEX MARK
ZE
S
w
B
S
w
A
S
B
b
e
A
S
y
S
y1
S
x
A B
M
D
E
Data Sheet M14670EJ6V0DS
21



PD442002-X
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
PD442002-X.
Types of Surface Mount Device
PD442002F9-BBxxX-BC1 : 48-pin TAPE FBGA (6x8)
PD442002F9-BCxxX-BC1 : 48-pin TAPE FBGA (6x8)
PD442002F9-DDxxX-BC1 : 48-pin TAPE FBGA (6x8)
Data Sheet M14670EJ6V0DS
22



PD442002-X
[ MEMO ]
Data Sheet M14670EJ6V0DS
23



PD442002-X
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.



PD442002-X
M8E 00. 4
The information in this document is current as of July, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
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(Note)
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