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Datasheet: M14669EJ7V0DS00 (NEC)

 

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2000
2M-BIT CMOS STATIC RAM
256K-WORD BY 8-BIT
EXTENDED TEMPERATURE OPERATION
MOS INTEGRATED CIRCUIT



PD442000A-X
DATA SHEET
Document No. M14669EJ7V0DS00 (7th edition)
Date Published October 2002 NS CP (K)
Printed in Japan
The mark
5
5
5
5
shows major revised points.
Description
The
PD442000A-X is a high speed, low power, 2,097,152 bits (262,144 words by 8 bits) CMOS static RAM.
The
PD442000A-X has two chip enable pins (/CE1, CE2) to extend the capacity. And battery backup is available.
The
PD442000A-X is packed in 32-pin PLASTIC TSOP (I) (Normal bent) and 32-pin PLASTIC TSOP (I) (Reverse
bent).
Features
262,144 words by 8 bits organization
Fast access time : 55, 70, 85, 100, 120 ns (MAX.)
Low voltage operation : V
CC
= 2.7 to 3.6 V (-BB55X, -BB70X, -BB85X)
V
CC
= 2.2 to 3.6 V (-BC70X, -BC85X, -BC10X)
V
CC
= 1.8 to 2.2 V (-DD85X, -DD10X, -DD12X)
Low V
CC
data retention : 1.0 V (MIN.)
Operating ambient temperature : T
A
= 25 to +85 C
Output Enable input for easy application
Two Chip Enable inputs : /CE1, CE2
PD442000A
Access time
Operating supply Operating ambient
Supply current
ns (MAX.)
voltage
temperature
At operating
At standby
At data retention
V
C
mA (MAX.)
A (MAX.)
A (MAX.)
-BB55X, -BB70X, -BB85X
55, 70, 85
2.7 to 3.6
-
25 to +85
30
Note
2
1
-BC70X, -BC85X, -BC10X
70, 85, 100
2.2 to 3.6
30
-DD85X, -DD10X, -DD12X
85, 100, 120
1.8 to 2.2
15
1.5
Note Cycle time
70 ns, -BB55X : 35 mA
Data Sheet M14669EJ7V0DS
2



PD442000A-X
Ordering Information
Part number
Package
Access time
Operating
Operating
ns (MAX.)
supply voltage
temperature
V
C
PD442000AGU-BB55X-9JH
32-pin PLASTIC TSOP (I)
55
2.7 to 3.6
-
25 to +85
PD442000AGU-BB70X-9JH
(8
13.4) (Normal bent)
70
PD442000AGU-BB85X-9JH
85
PD442000AGU-BC70X-9JH
70
2.2 to 3.6
PD442000AGU-BC85X-9JH
85
PD442000AGU-BC10X-9JH
100
PD442000AGU-DD85X-9JH
85
1.8 to 2.2
PD442000AGU-DD10X-9JH
100
PD442000AGU-DD12X-9JH
120
PD442000AGU-BB55X-9KH
32-pin PLASTIC TSOP (I)
55
2.7 to 3.6
PD442000AGU-BB70X-9KH
(8
13.4) (Reverse bent)
70
PD442000AGU-BB85X-9KH
85
PD442000AGU-BC70X-9KH
70
2.2 to 3.6
PD442000AGU-BC85X-9KH
85
PD442000AGU-BC10X-9KH
100
PD442000AGU-DD85X-9KH
85
1.8 to 2.2
PD442000AGU-DD10X-9KH
100
PD442000AGU-DD12X-9KH
120
Data Sheet M14669EJ7V0DS
3



PD442000A-X
Pin Configurations
/xxx indicates active low signal.
32-pin PLASTIC TSOP (I) (8



13.4) (Normal bent)
[



PD442000AGU-9JH ]
Marking Side
A11
A9
A8
A13
/WE
CE2
A15
V
CC
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
A3
A0 to A17
: Address inputs
I/O1 to I/O8 : Data inputs / outputs
/CE1, CE2
: Chip Enable 1, 2
/WE
: Write Enable
/OE
: Output Enable
V
CC
: Power supply
GND
: Ground
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M14669EJ7V0DS
4



PD442000A-X
32-pin PLASTIC TSOP (I) (8



13.4) (Reverse bent)
[



PD442000AGU-9KH ]
Marking Side
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A11
A9
A8
A13
/WE
CE2
A15
V
CC
A17
A16
A14
A12
A7
A6
A5
A4
A0 to A17
: Address inputs
I/O1 to I/O8 : Data inputs / outputs
/CE1, CE2
: Chip Enable 1, 2
/WE
: Write Enable
/OE
: Output Enable
V
CC
: Power supply
GND
: Ground
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M14669EJ7V0DS
5



PD442000A-X
Block Diagram
Address buffer
Address
buffer
Row
decoder
Memory cell array
2,097,152 bits
Input data
controller
A0
A17
Sense amplifier /
Switching circuit
Column decoder
/CE1
/WE
/OE
CE2
Output data
controller
V
CC
GND
I/O1
I/O8
Truth Table
/CE1
CE2
/OE
/WE
Mode
I/O
Supply current
H
Not selected
High-Z
I
SB
L
Not selected
High-Z
L
H
H
H
Output disable
High-Z
I
CCA
L
H
L
H
Read
D
OUT
L
H
L
Write
D
IN
Remark
: V
IH
or V
IL
Data Sheet M14669EJ7V0DS
6



PD442000A-X
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
-BB55X, -BB70X, -BB85X
-DD85X, -DD10X, -DD12X
-BC70X, -BC85X, -BC10X
Supply voltage
V
CC
0.5
Note
to +4.0
0.5
Note
to +2.7
V
Input / Output voltage
V
T
0.5
Note
to V
CC
+0.4 (4.0 V MAX.) 0.5
Note
to V
CC
+0.4 (2.7 V MAX.)
V
Operating ambient temperature
T
A
25 to +85
25 to +85
C
Storage temperature
T
stg
55 to +125
55 to +125
C
Note 3.0 V (MIN.) (Pulse width : 30 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
-BB55X,-BB70X,-BB85X -BC70X,-BC85X,-BC10X-DD85X,-DD10X,-DD12X
Unit
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Supply voltage
V
CC
2.7
3.6
2.2
3.6
1.8
2.2
V
High level input voltage
V
IH
2.7 V
V
CC
3.6 V
2.4
V
CC
+0.4
2.4
V
CC
+0.4
V
2.2 V
V
CC
< 2.7 V
2.0
V
CC
+0.3
1.8 V
V
CC
< 2.2 V
1.6
V
CC
+0.2
Low level input voltage
V
IL
0.3
Note
+0.5
0.3
Note
+0.4
0.2
Note
+0.2
V
Operating ambient
T
A
25
+85
25
+85
25
+85
C
temperature
Note 1.0 V (MIN.) (Pulse width : 20 ns)
Capacitance (T
A
= 25



C, f = 1 MHz)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input capacitance
C
IN
V
IN
= 0 V
8
pF
Input / Output capacitance
C
I/O
V
I/O
= 0 V
10
pF
Remarks
1. V
IN
: Input voltage
V
I/O
: Input / Output voltage
2. These parameters are not 100% tested.
Data Sheet M14669EJ7V0DS
7



PD442000A-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2)
Parameter
Symbol
Test condition
-BB55X, -BB70X, -BB85X
Unit
MIN.
TYP.
MAX.
Input leakage current
I
LI
V
IN
= 0 V to V
CC
1.0
+1.0
A
I/O leakage current
I
LO
V
I/O
= 0 V to V
CC
, /CE1 = V
IH
or
1.0
+1.0
A
CE2 = V
IL
or /WE = V
IL
or /OE = V
IH
Operating supply current
I
CCA1
/CE1 = V
IL
, CE2 = V
IH
,
Cycle time = 55 ns
35
mA
Minimum cycle time,
Cycle time
70 ns
30
I
I/O
= 0 mA
I
CCA2
/CE1 = V
IL
, CE2 = V
IH
,
4
Cycle time =
, I
I/O
= 0 mA
I
CCA3
/CE1
0.2 V, CE2
V
CC
0.2 V,
4
Cycle time = 1
s, I
I/O
= 0 mA,
V
IL
0.2 V, V
IH
V
CC
0.2 V
Standby supply current
I
SB
/CE1 = V
IH
or CE2 = V
IL
0.35
mA
I
SB1
/CE1
V
CC
0.2 V, CE2
V
CC
0.2 V
0.1
2
A
I
SB2
CE2
0.2 V
0.1
2
High level output voltage
V
OH
I
OH
= 0.5 mA
2.4
V
Low level output voltage
V
OL
I
OL
= 1.0 mA
0.4
V
Remarks 1. V
IN
: Input voltage
V
I/O
: Input / Output voltage
2. These DC characteristics are in common regardless of product classification.
Data Sheet M14669EJ7V0DS
8



PD442000A-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2)
Parameter
Symbol
Test condition
-BC70X, -BC85X, -BC10X -DD85X, -DD10X, -DD12X
Unit
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
Input leakage current
I
LI
V
IN
= 0 V to V
CC
1.0
+1.0
1.0
+1.0
A
I/O leakage current
I
LO
V
I/O
= 0 V to V
CC
, /CE1 = V
IH
or
1.0
+1.0
1.0
+1.0
A
CE2 = V
IL
or /WE = V
IL
or /OE = V
IH
Operating supply current
I
CCA1
/CE1 = V
IL
, CE2 = V
IH
,
30
mA
Minimum cycle time,
V
CC
2.7 V
25
I
I/O
= 0 mA
V
CC
2.2 V
15
I
CCA2
/CE1 = V
IL
, CE2 = V
IH
,
4
Cycle time =
,
V
CC
2.7 V
2
I
I/O
= 0 mA
V
CC
2.2 V
1
I
CCA3
/CE1
0.2 V, CE2
V
CC
0.2 V,
4
Cycle time = 1
s, I
I/O
= 0 mA,
V
IL
0.2 V,
V
CC
2.7 V
3
V
IH
V
CC
0.2 V
V
CC
2.2 V
3
Standby supply current
I
SB
/CE1 = V
IH
or CE2 = V
IL
0.35
mA
V
CC
2.7 V
0.35
V
CC
2.2 V
0.35
I
SB1
/CE1
V
CC
0.2 V,
0.1
2
A
CE2
V
CC
0.2 V
V
CC
2.7 V
0.08
2
V
CC
2.2 V
0.05
1.5
I
SB2
CE2
0.2 V
0.1
2
V
CC
2.7 V
0.08
2
V
CC
2.2 V
0.05
1.5
High level output voltage
V
OH
I
OH
= 0.5 mA
2.4
V
V
CC
2.7 V
1.8
V
CC
2.2 V
1.5
Low level output voltage
V
OL
I
OL
= 1.0 mA
0.4
V
V
CC
2.7 V
0.4
V
CC
2.2 V
0.4
Remarks 1. V
IN
: Input voltage
V
I/O
: Input / Output voltage
2. These DC characteristics are in common regardless of product classification.
Data Sheet M14669EJ7V0DS
9



PD442000A-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
Input Waveform (Rise and Fall Time



5 ns)
0.1
V
CC
0.9
V
CC
Test points
V
CC
/2
V
CC
/2
Output Waveform
Test points
V
CC
/2
V
CC
/2
Output Load
[ -BB55X, -BB70X, -BB85X ]
1TTL + 50 pF
[ -BC70X, -BC85X, -BC10X, -DD85X, -DD10X, -DD12X ]
1TTL + 30 pF
Data Sheet M14669EJ7V0DS
10



PD442000A-X
Read Cycle (1/3)
Parameter
Symbol
V
CC
2.7 V
Unit
Condition
-BB55X
-BB70X
-BB85X
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read cycle time
t
RC
55
70
85
ns
Address access time
t
AA
55
70
85
ns
Note 1
/CE1 access time
t
CO1
55
70
85
ns
CE2 access time
t
CO2
55
70
85
ns
/OE to output valid
t
OE
30
35
40
ns
Output hold from address change
t
OH
10
10
10
ns
/CE1 to output in Low-Z
t
LZ1
10
10
10
ns
Note 2
CE2 to output in Low-Z
t
LZ2
10
10
10
ns
/OE to output in Low-Z
t
OLZ
5
5
5
ns
/CE1 to output in High-Z
t
HZ1
20
25
30
ns
CE2 to output in High-Z
t
HZ2
20
25
30
ns
/OE to output in High-Z
t
OHZ
20
25
30
ns
Notes 1. The output load is 1TTL + 50 pF.
2. The output load is 1TTL + 5 pF.
Read Cycle (2/3)
Parameter
Symbol
V
CC
2.2 V
Unit
Condition
-BC70X
-BC85X
-BC10X
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read cycle time
t
RC
70
85
100
ns
Address access time
t
AA
70
85
100
ns
Note 1
/CE1 access time
t
CO1
70
85
100
ns
CE2 access time
t
CO2
70
85
100
ns
/OE to output valid
t
OE
35
40
50
ns
Output hold from address change
t
OH
10
10
10
ns
/CE1 to output in Low-Z
t
LZ1
10
10
10
ns
Note 2
CE2 to output in Low-Z
t
LZ2
10
10
10
ns
/OE to output in Low-Z
t
OLZ
5
5
5
ns
/CE1 to output in High-Z
t
HZ1
25
30
35
ns
CE2 to output in High-Z
t
HZ2
25
30
35
ns
/OE to output in High-Z
t
OHZ
25
30
35
ns
Notes 1. The output load is 1TTL + 30 pF.
2. The output load is 1TTL + 5 pF.
Data Sheet M14669EJ7V0DS
11



PD442000A-X
Read Cycle (3/3)
Parameter
Symbol
V
CC
1.8 V
Unit
Condition
-DD85X
-DD10X
-DD12X
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read cycle time
t
RC
85
100
120
ns
Address access time
t
AA
85
100
120
ns
Note 1
/CE1 access time
t
CO1
85
100
120
ns
CE2 access time
t
CO2
85
100
120
ns
/OE to output valid
t
OE
40
50
60
ns
Output hold from address change
t
OH
10
10
10
ns
/CE1 to output in Low-Z
t
LZ1
10
10
10
ns
Note 2
CE2 to output in Low-Z
t
LZ2
10
10
10
ns
/OE to output in Low-Z
t
OLZ
5
5
5
ns
/CE1 to output in High-Z
t
HZ1
30
35
40
ns
CE2 to output in High-Z
t
HZ2
30
35
40
ns
/OE to output in High-Z
t
OHZ
30
35
40
ns
Notes 1. The output load is 1TTL + 30 pF.
2. The output load is 1TTL + 5 pF.
Data Sheet M14669EJ7V0DS
12



PD442000A-X
Read Cycle Timing Chart
t
HZ2
t
RC
t
OH
t
HZ1
t
LZ2
t
CO2
t
LZ1
t
CO1
t
AA
High-Z
Data out
CE2 (Input)
/CE1 (Input)
Address (Input)
I/O (Output)
t
OLZ
t
OE
t
OHZ
/OE (Input)
Remark In read cycle, /WE should be fixed to high level.
Data Sheet M14669EJ7V0DS
13



PD442000A-X
Write Cycle (1/3)
Parameter
Symbol
V
CC
2.7 V
Unit
Condition
-BB55X
-BB70X
-BB85X
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Write cycle time
t
WC
55
70
85
ns
/CE1 to end of write
t
CW1
50
55
70
ns
CE2 to end of write
t
CW2
50
55
70
ns
Address valid to end of write
t
AW
50
55
70
ns
Address setup time
t
AS
0
0
0
ns
Write pulse width
t
WP
45
50
55
ns
Write recovery time
t
WR
0
0
0
ns
Data valid to end of write
t
DW
25
30
35
ns
Data hold time
t
DH
0
0
0
ns
/WE to output in High-Z
t
WHZ
20
25
30
ns
Note
Output active from end of write
t
OW
5
5
5
ns
Note The output load is 1TTL + 5 pF.
Write Cycle (2/3)
Parameter
Symbol
V
CC
2.2 V
Unit
Condition
-BC70X
-BC85X
-BC10X
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Write cycle time
t
WC
70
85
100
ns
/CE1 to end of write
t
CW1
55
70
80
ns
CE2 to end of write
t
CW2
55
70
80
ns
Address valid to end of write
t
AW
55
70
80
ns
Address setup time
t
AS
0
0
0
ns
Write pulse width
t
WP
50
55
60
ns
Write recovery time
t
WR
0
0
0
ns
Data valid to end of write
t
DW
30
35
40
ns
Data hold time
t
DH
0
0
0
ns
/WE to output in High-Z
t
WHZ
25
30
35
ns
Note
Output active from end of write
t
OW
5
5
5
ns
Note The output load is 1TTL + 5 pF.
Data Sheet M14669EJ7V0DS
14



PD442000A-X
Write Cycle (3/3)
Parameter
Symbol
V
CC
1.8 V
Unit
Condition
-DD85X
-DD10X
-DD12X
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Write cycle time
t
WC
85
100
120
ns
/CE1 to end of write
t
CW1
70
80
100
ns
CE2 to end of write
t
CW2
70
80
100
ns
Address valid to end of write
t
AW
70
80
100
ns
Address setup time
t
AS
0
0
0
ns
Write pulse width
t
WP
55
60
85
ns
Write recovery time
t
WR
0
0
0
ns
Data valid to end of write
t
DW
35
40
60
ns
Data hold time
t
DH
0
0
0
ns
/WE to output in High-Z
t
WHZ
30
35
40
ns
Note
Output active from end of write
t
OW
5
5
5
ns
Note The output load is 1TTL + 5 pF.
Data Sheet M14669EJ7V0DS
15



PD442000A-X
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
t
CW1
t
WHZ
t
DW
t
DH
t
OW
Indefinite data out
High-Z
High-Z
Data in
Indefinite data out
Address (Input)
/CE1 (Input)
I/O (Input / Output)
CE2 (Input)
t
CW2
t
AW
t
WP
t
AS
t
WR
/WE (Input)
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE, and a high level CE2.
2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2
changes to high level at the same time or after the change of /WE to low level, the I/O pins will
remain high impedance state.
3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
read operation is executed. Therefore /OE should be at high level to make the I/O pins high
impedance.
Data Sheet M14669EJ7V0DS
16



PD442000A-X
Write Cycle Timing Chart 2 (/CE1 Controlled)
t
WC
t
AS
t
CW1
t
DW
t
DH
Data in
High-Z
Address (Input)
/CE1 (Input)
I/O (Input)
High-Z
CE2 (Input)
t
CW2
t
AW
t
WP
t
WR
/WE (Input)
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CE1, /WE, and a high level CE2.
Data Sheet M14669EJ7V0DS
17



PD442000A-X
Write Cycle Timing Chart 3 (CE2 Controlled)
t
WC
t
AS
t
CW2
t
DW
t
DH
Data in
High-Z
Address (Input)
CE2 (Input)
I/O (Input)
High-Z
/CE1 (Input)
t
CW1
t
AW
t
WP
t
WR
/WE (Input)
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CE1, /WE, and a high level CE2.
Data Sheet M14669EJ7V0DS
18



PD442000A-X
Low V
CC
Data Retention Characteristics (T
A
= 25 to +85



C)
Parameter
Symbol
Test Condition
-BB55X,-BB70X, -BB85X -BC70X,-BC85X, -BC10X -DD85X,-DD10X, -DD12X
Unit
MIN. TYP. MAX. MIN.
TYP. MAX. MIN. TYP. MAX.
Data retention
V
CCDR1
/CE1
V
CC
-
0.2 V,
1.0
3.6
1.0
3.6
1.0
2.2
V
supply voltage
CE2
V
CC
-
0.2 V
V
CCDR2
CE2
0.2 V
1.0
3.6
1.0
3.6
1.0
2.2
Data retention
I
CCDR1
V
CC
= 1.2 V, /CE1
V
CC
-
0.2 V,
0.05
1
0.05
1
0.05
1
A
supply current
CE2
V
CC
-
0.2 V
I
CCDR2
V
CC
= 1.2 V, CE2
0.2 V
0.05
1
0.05
1
0.05
1
Chip deselection
t
CDR
0
0
0
ns
to data retention
mode
Operation
t
R
t
RC
Note
t
RC
Note
t
RC
Note
ns
recovery time
Note t
RC
: Read cycle time
Data Sheet M14669EJ7V0DS
19



PD442000A-X
Data Retention Timing Chart
(1) /CE1 Controlled
V
IH
(MIN.)
V
CCDR
(MIN.)
V
IL
(MAX.)
/CE1
/CE1
V
CC
0.2 V
GND
V
CC
(MIN.)
Note
t
CDR
Data retention mode
t
R
V
CC
Note 2.7 V (-BB55X, -BB70X, -BB85X), 2.2 V (-BC70X, -BC85X, -BC10X), 1.8 V (-DD85X, -DD10X, -DD12X)
Remark On the data retention mode by controlling /CE1, the input level of CE2 must be
V
CC
-
0.2 V or
0.2 V.
The other pins (Address, I/O, /WE, /OE) can be in high impedance state.
(2) CE2 Controlled
V
IH
(MIN.)
V
CCDR
(MIN.)
V
IL
(MAX.)
CE2
CE2
0.2 V
GND
V
CC
(MIN.)
Note
t
CDR
Data retention mode
t
R
V
CC
Note 2.7 V (-BB55X, -BB70X, -BB85X), 2.2 V (-BC70X, -BC85X, -BC10X), 1.8 V (-DD85X, -DD10X, -DD12X)
Remark On the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE, /OE) can be in
high impedance state.
Data Sheet M14669EJ7V0DS
20



PD442000A-X
Package Drawings
32-PIN PLASTIC TSOP(
I
) (8x13.4)
NOTES
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
P32GU-50-9JH-2
B
0.45 MAX.
C
0.5 (T.P.)
detail of lead end
A
8.0
0.1
H
12.4
0.2
B
T
D
0.22
0.05
G
1.0
0.05
I
11.8
0.1
J
0.8
0.2
K
L
0.5
M
0.08
N
0.08
Q
0.1
0.05
P
13.4
0.2
S
1.2 MAX.
R
3
T
0.25
U
0.6
0.15
+
5
-
3
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
M
U
L
R
Q
S
D
M
C
G
J
0.145
+
0.025
-
0.015
1
16
32
17
S
S
N
K
H
P
I
A
Data Sheet M14669EJ7V0DS
21



PD442000A-X
+
0.025
-
0.015
32-PIN PLASTIC TSOP(
I
) (8x13.4)
NOTES
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
P32GU-50-9KH-2
B
0.45 MAX.
C
0.5 (T.P.)
detail of lead end
A
8.0
0.1
H
12.4
0.2
T
D
0.22
0.05
G
1.0
0.05
I
11.8
0.1
J
0.8
0.2
K
L
0.5
M
0.08
N
0.08
Q
0.1
0.05
P
13.4
0.2
S
1.2 MAX.
R
3
T
0.25
U
0.6
0.15
+
5
-
3
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
U
L
R
Q
S
0.145
1
16
32
17
S
N
S
B
M
D
M
C
G
A
K
H
P
I
J
Data Sheet M14669EJ7V0DS
22



PD442000A-X
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
PD442000A-X.
Types of Surface Mount Device
PD442000AGU-9JH : 32-pin PLASTIC TSOP (I) (8
13.4) (Normal bent)
PD442000AGU-9KH : 32-pin PLASTIC TSOP (I) (8
13.4) (Reverse bent)
Data Sheet M14669EJ7V0DS
23



PD442000A-X
Revision History
Edition/
Page
Type of
Location
Description
Date
This
Previous
revision
(Previous edition
This edition)
edition
edition
6th edition/ pp.6, 7
pp.6, 7
Modification DC Characteristics
-BB55X,-BB70X,-BB85X(MAX.) : I
SB
= 0.6mA
0.35mA
Jul. 2002
-BC70X,-BC85X,-BC10X(MAX.) : I
SB
= 0.6mA
0.35mA
-BC70X,-BC85X,-BC10X(MAX.) :
I
SB
(V
CC
2.7 V)
= 0.6mA
0.35mA
-DD85X,-DD10X,-DD12X(MAX.) : I
SB
= 0.6mA
0.35mA
p.8
p.8
Modification AC Characteristics
Integration of Input Waveform and Output Waveform
7th edition/ pp.2, 4, 21-22 pp.2, 3, 19-20 Addition
Ordering Information, 32-pin PLASTIC TSOP (I) (8
13.4) (Reverse bent)
Oct. 2002
Pin Configurations,
PD442000AGU-***-9KH
Package Drawings,
*** : Speed grades
Recommended
BB55X, BB70X, BB85X, BC70X, BC85X, BC10X,
Soldering Conditions
DD85X, DD10X, DD12X
Data Sheet M14669EJ7V0DS
24



PD442000A-X
[ MEMO ]
Data Sheet M14669EJ7V0DS
25



PD442000A-X
[ MEMO ]
Data Sheet M14669EJ7V0DS
26



PD442000A-X
[ MEMO ]
Data Sheet M14669EJ7V0DS
27



PD442000A-X
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.



PD442000A-X
M8E 00. 4
The information in this document is current as of October, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
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