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Datasheet: M14439EJ2V0DS00 (NEC)

 

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2000
MOS INTEGRATED CIRCUIT



PD4443362
4M-BIT CMOS SYNCHRONOUS FAST STATIC RAM
128K-WORD BY 36-BIT
HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE
DATA SHEET
Document No. M14439EJ2V0DS00 (2nd edition)
Date Published February 2001 NS CP(K)
Printed in Japan
The mark
5
5
5
5
shows major revised points.
Description
The
PD4443362 is a 131,072 words by 36 bits synchronous static RAM fabricated with advanced CMOS
technology using Full-CMOS six-transistor memory cell.
The
PD4443362 is suitable for applications which require synchronous operation, high-speed, low voltage, high-
density memory and wide bit configuration, such as cache and buffer memory.
The
PD4443362 is packaged in 100-pin plastic LQFP with a 1.4 mm package thickness for high density and low
capacitive loading.
Features
Fully synchronous operation
HSTL Input / Output levels
Fast clock access time : 3.8 ns (133 MHz)
Asynchronous output enable control : /G
Byte write control : /SBa (DQa1-9), /SBb (DQb1-9), /SBc (DQc1-9), /SBd (DQd1-9)
Common I/O using three-state outputs
Internally self-timed write cycle
Late write with 1 dead cycle between Read-Write
3.3 V (Chip) / 1.5 V (I/O) supply
100-pin plastic LQFP package, 14 mm x 20 mm
Sleep Mode : ZZ (Enables sleep mode, active high)
Ordering Information
Part number
Access time
Clock frequency
Package
PD4443362GF-A75
3.8 ns
133 MHz
100-PIN PLASTIC LQFP (14 x 20)
5
5
5
5
5
5
5
5
Data Sheet M14439EJ2V0DS
2



PD4443362
Pin Configuration (Marking Side)
/xxx indicates active low signal.
100-PIN PLASTIC LQFP (14 x 20)
[



PD4443362GF ]
DQc9
DQc8
DQc7
V
DD
Q
V
SS
Q
DQc6
DQc5
DQc4
DQc3
V
SS
Q
V
DD
Q
DQc2
DQc1
NC
V
DD
NC
V
SS
DQd1
DQd2
V
DD
Q
V
SS
Q
DQd3
DQd4
DQd5
DQd6
V
SS
Q
V
DD
Q
DQd7
DQd8
DQd9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQb9
DQb8
DQb7
V
DD
Q
V
SS
Q
DQb6
DQb5
DQb4
DQb3
V
SS
Q
V
DD
Q
DQb2
DQb1
V
SS
NC
V
DD
ZZ
DQa1
DQa2
V
DD
Q
V
SS
Q
DQa3
DQa4
DQa5
DQa6
V
SS
Q
V
DD
Q
DQa7
DQa8
DQa9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
SA6
SA7
/SS
/SBd
/SBc
/SBb
NC
/SBa
NC
V
DD
V
SS
K
/K
V
REF
/G
/SW
NC
NC
SA8
SA9
NC
SA5
SA4
SA3
SA2
SA1
SA0
V
REF
NC
V
SS
V
DD
NC
V
REF
SA10
SA11
SA12
SA13
SA14
SA15
SA16
Remark Refer to Package Drawing for 1-pin index mark.
Data Sheet M14439EJ2V0DS
3



PD4443362
Pin Name and Functions
Pin name
Pin No.
Description
SA0 to SA16
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input
45, 46, 47, 48, 49, 50
DQa1 to DQa9
63, 62, 59, 58, 57, 56, 53, 52, 51
Synchronous Data Input / Output
DQb1 to DQb9
68, 69, 72, 73, 74, 75, 78, 79, 80
DQc1 to DQc9
13, 12, 9, 8, 7, 6, 3, 2, 1
DQd1 to DQd9
18, 19, 22, 23, 24, 25, 28, 29, 30
/SS
98
Synchronous Chip Select
/SW
85
Synchronous Byte Write Enable
/SBa
Note1
93
Synchronous Byte "a" Write Enable
/SBb
Note1
95
Synchronous Byte "b" Write Enable
/SBc
Note1
96
Synchronous Byte "c" Write Enable
/SBd
Note1
97
Synchronous Byte "d" Write Enable
/G
86
Asynchronous Output Enable
ZZ
Note2
64
Asynchronous Sleep Mode
K, /K
89, 88
Main Clock Input
V
DD
15, 41, 65, 91
Core Power Supply
V
SS
17, 40, 67, 90
Ground
V
DD
Q
4, 11, 20, 27, 54, 61, 70, 77
Output Buffer Power Supply
V
SS
Q
5, 10, 21, 26, 55, 60, 71, 76
Output Buffer Ground
V
REF
38, 43, 87
Input Reference
NC
14, 16, 31, 39, 42, 66, 83, 84, 92, 94
No Connection
Notes 1. If Byte Write Operation is not used, Byte Write Pins (/SBa, /SBb, /SBc, /SBd) are to be tied to V
SS
.
2. If Sleep Mode is not used, ZZ Pin is to be tied to V
SS
.
Remark This device only supports Single Differential Clock, R / R Mode.
(R / R stands for Registered Input / Registered Output.)
Data Sheet M14439EJ2V0DS
4



PD4443362
Late Write Block Diagram
K
/SBa
K
/K
/SS
/SW
/SBa
/SBb
/SBc
/SBd
Data
in
register
Write
control
logic
Address
register
Write address
register
Read
comp.
Memory
cell array
4,718,592 bits
Data
in
Data
out
Mux
Output
Register
/SW
/SBc
/SBb
DQa1 to DQa9
DQb1 to DQb9
DQc1 to DQc9
DQd1 to DQd9
/SBd
/G
/K
/SS
SA0 to SA16
Mux
ZZ
Write
clock
generator
/G
ZZ
36
17
Data Sheet M14439EJ2V0DS
5



PD4443362
Synchronous Truth Table
ZZ
/SS
/SW
/SBa
/SBb
/SBc
/SBd
Mode
DQa1
9 DQb1
9 DQc1
9 DQd1
9
Power
L
H
Not selected
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Active
L
L
H
Read
Dout
Dout
Dout
Dout
Active
L
L
L
L
L
L
L
Write
Din
Din
Din
Din
Active
L
L
L
L
H
H
H
Write
Din
Hi-Z
Hi-Z
Hi-Z
Active
L
L
L
H
L
L
L
Write
Hi-Z
Din
Din
Din
Active
L
L
L
H
H
H
H
Abort Write
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Active
H
Sleep Mode
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Standby
Remark
: Don't care
Output Enable Truth Table
Mode
/G
DQ
Read
L
Dout
Read
H
Hi-Z
Sleep (ZZ=H)
Hi-Z
Write (/SW=L)
Hi-Z, Din
Deselect (/SS=H)
Hi-Z
Remark
: Don't care
5
5
5
5
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