HTML datasheet archive (search documentation on electronic components) Search datasheet (1.687.043 components)
Search field

Datasheet: M13609EJ4V0DS00 (NEC)

 

Download: PDF   ZIP
NEC

Document Outline

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
1999
MOS INTEGRATED CIRCUIT



PD464518AL, 464536AL
4M-BIT Bi-CMOS SYNCHRONOUS FAST STATIC RAM
256K-WORD BY 18-BIT / 128K-WORD BY 36-BIT
LVTTL INTERFACE/REGISTER-LATCH/LATE WRITE
DATA SHEET
Document No. M13609EJ4V0DS00 (4th edition)
Date Published January 2001 NS CP(K)
Printed in Japan
The mark
shows major revised points.
Description
The
PD464518AL is a 262,144 words by 18 bits, and the
PD464536AL is a 131,072 words by 36 bits
synchronous static RAM fabricated with advanced Bi-CMOS technology using N-channel memory cell.
This technology and unique peripheral circuits make the
PD464518AL and
PD464536AL a high-speed device.
The
PD464518AL and
PD464536AL are suitable for applications which require high-speed, low voltage, high-
density memory and wide bit configuration, such as cache and buffer memory.
These are packaged in a 119-pin plastic BGA (Ball Grid Array).
Features
Register to latch synchronous operation
LVTTL 3.3 V Input / Output levels
Fast clock access time : 5.5 ns / 182 MHz, 6.0 ns / 166 MHz, 7.0 ns / 143 MHz
Asynchronous output enable control : /G
Single differential clock inputs
Byte write control : /SBa (DQa1-9), /SBb (DQb1-9), /SBc (DQc1-9), /SBd (DQd1-9)
Common I/O using three-state outputs
Internally self-timed write cycle
Late write with 1 dead cycle between Read-Write
Boundary scan (JTAG) IEEE 1149.1 compatible
Single +3.3 V power supply
Sleep mode : ZZ(Enables sleep mode, active high)
Ordering Information
Part number
Access time
Clock frequency
Package
PD464518ALS1-A55
5.5 ns
182 MHz
119-pin plastic BGA
PD464518ALS1-A6
6.0 ns
166 MHz
PD464518ALS1-A7
7.0 ns
143 MHz
PD464536ALS1-A55
5.5 ns
182 MHz
PD464536ALS1-A6
6.0 ns
166 MHz
PD464536ALS1-A7
7.0 ns
143 MHz
2



PD464518AL, 464536AL
Data Sheet M13609EJ4V0DS
Pin Configurations
/xxx indicates active low signal.
119-pin Plastic BGA (256K Words by 18 Bits Pin Assignment)
[



PD464518ALS1]
1
2
3
4
5
6
7
L
N
M
R
P
T
U
D
F
E
H
G
J
K
B
C
A
7
6
5
4
3
2
1
Bottom View
Top View
7
6
5
4
3
2
1
1
2
3
4
5
6
7
V
DD
Q
SA2
SA6
NC
SA9
SA12
V
DD
Q
A
V
DD
Q
SA12
SA9
NC
SA6
SA2
V
DD
Q
NC
NC
SA16
NC
SA17
NC
NC
B
NC
NC
SA17
NC
SA16
NC
NC
NC
SA3
SA7
V
DD
SA10
SA13
NC
C
NC
SA13
SA10
V
DD
SA7
SA3
NC
NC
DQa9
V
SS
NC
V
SS
NC
DQb1
D
DQb1
NC
V
SS
NC
V
SS
DQa9
NC
DQa8
NC
V
SS
/SS
V
SS
DQb2
NC
E
NC
DQb2
V
SS
/SS
V
SS
NC
DQa8
V
DD
Q
DQa7
V
SS
/G
V
SS
NC
V
DD
Q
F
V
DD
Q
NC
V
SS
/G
V
SS
DQa7
V
DD
Q
DQa6
NC
V
SS
NC
/SBb
DQb3
NC
G
NC
DQb3
/SBb
NC
V
SS
NC
DQa6
NC
DQa5
V
SS
NC
V
SS
NC
DQb4
H
DQb4
NC
V
SS
NC
V
SS
DQa5
NC
V
DD
Q
V
DD
NC
V
DD
NC
V
DD
V
DD
Q
J
V
DD
Q
V
DD
NC
V
DD
NC
V
DD
V
DD
Q
DQa4
NC
V
SS
K
V
SS
DQb5
NC
K
NC
DQb5
V
SS
K
V
SS
NC
DQa4
NC
DQa3
/SBa
/K
V
SS
NC
DQb6
L
DQb6
NC
V
SS
/K
/SBa
DQa3
NC
V
DD
Q
NC
V
SS
/SW
V
SS
DQb7
V
DD
Q
M
V
DD
Q
DQb7
V
SS
/SW
V
SS
NC
V
DD
Q
NC
DQa2
V
SS
SA1
V
SS
NC
DQb8
N
DQb8
NC
V
SS
SA1
V
SS
DQa2
NC
DQa1
NC
V
SS
SA0
V
SS
DQb9
NC
P
NC
DQb9
V
SS
SA0
V
SS
NC
DQa1
NC
SA4
V
SS
V
DD
V
DD
SA14
NC
R
NC
SA14
V
DD
V
DD
V
SS
SA4
NC
ZZ
SA5
SA8
NC
SA11
SA15
NC
T
NC
SA15
SA11
NC
SA8
SA5
ZZ
V
DD
Q
NC
TDO
TCK
TDI
TMS
V
DD
Q
U
V
DD
Q
TMS
TDI
TCK
TDO
NC
V
DD
Q
3



PD464518AL, 464536AL
Data Sheet M13609EJ4V0DS
Pin Name and Functions [



PD464518ALS1]
Pin name
Description
Function
V
DD
Core Power Supply
Supplies power for RAM core
V
SS
Ground
V
DD
Q
Output Power Supply
Supplies power for output buffers
K, /K
Main Clock Input
SA0 to SA17
Synchronous Address Input
DQa1 to DQb9
Synchronous Data Input / Output
/SS
Synchronous Chip Select
Logically selects SRAM
/SW
Synchronous Byte Write Enable
Write command
/SBa
Synchronous Byte "a" Write Enable
Write DQa1 to DQa9
/SBb
Synchronous Byte "b" Write Enable
Write DQb1 to DQb9
/G
Asynchronous Output Enable
Asynchronous input
ZZ
Sleep Mode Enable
Enables sleep mode, active high
NC
No Connection
TMS
Test Mode Select (JTAG)
TDI
Test Data Input (JTAG)
TCK
Test Clock Input (JTAG)
TDO
Test Data Output (JTAG)
4



PD464518AL, 464536AL
Data Sheet M13609EJ4V0DS
119-pin plastic BGA (128K Words by 36 Bits Pin Assignment)
[



PD464536ALS1 ]
1
2
3
4
5
6
7
L
N
M
R
P
T
U
D
F
E
H
G
J
K
B
C
A
7
6
5
4
3
2
1
Bottom View
Top View
7
6
5
4
3
2
1
1
2
3
4
5
6
7
V
DD
Q
SA2
SA5
NC
SA9
SA12
V
DD
Q
A
V
DD
Q
SA12
SA9
NC
SA5
SA2
V
DD
Q
NC
NC
SA15
NC
SA16
NC
NC
B
NC
NC
SA16
NC
SA15
NC
NC
NC
SA3
SA6
V
DD
SA10
SA13
NC
C
NC
SA13
SA10
V
DD
SA6
SA3
NC
DQb8
DQb9
V
SS
NC
V
SS
DQc9
DQc8
D
DQc8
DQc9
V
SS
NC
V
SS
DQb9
DQb8
DQb6
DQb7
V
SS
/SS
V
SS
DQc7
DQc6
E
DQc6
DQc7
V
SS
/SS
V
SS
DQb7
DQb6
V
DD
Q
DQb5
V
SS
/G
V
SS
DQc5
V
DD
Q
F
V
DD
Q
DQc5
V
SS
/G
V
SS
DQb5
V
DD
Q
DQb3
DQb4
/SBb
NC
/SBc
DQc4
DQc3
G
DQc3
DQc4
/SBc
NC
/SBb
DQb4
DQb3
DQb1
DQb2
V
SS
NC
V
SS
DQc2
DQc1
H
DQc1
DQc2
V
SS
NC
V
SS
DQb2
DQb1
V
DD
Q
V
DD
NC
V
DD
NC
V
DD
V
DD
Q
J
V
DD
Q
V
DD
NC
V
DD
NC
V
DD
V
DD
Q
DQa1
DQa2
V
SS
K
V
SS
DQd2
DQd1
K
DQd1
DQd2
V
SS
K
V
SS
DQa2
DQa1
DQa3
DQa4
/SBa
/K
/SBd
DQd4
DQd3
L
DQd3
DQd4
/SBd
/K
/SBa
DQa4
DQa3
V
DD
Q
DQa5
V
SS
/SW
V
SS
DQd5
V
DD
Q
M
V
DD
Q
DQd5
V
SS
/SW
V
SS
DQa5
V
DD
Q
DQa6
DQa7
V
SS
SA1
V
SS
DQd7
DQd6
N
DQd6
DQd7
V
SS
SA1
V
SS
DQa7
DQa6
DQa8
DQa9
V
SS
SA0
V
SS
DQd9
DQd8
P
DQd8
DQd9
V
SS
SA0
V
SS
DQa9
DQa8
NC
SA4
V
SS
V
DD
V
DD
SA14
NC
R
NC
SA14
V
DD
V
DD
V
SS
SA4
NC
ZZ
NC
SA7
SA8
SA11
NC
NC
T
NC
NC
SA11
SA8
SA7
NC
ZZ
V
DD
Q
NC
TDO
TCK
TDI
TMS
V
DD
Q
U
V
DD
Q
TMS
TDI
TCK
TDO
NC
V
DD
Q
5



PD464518AL, 464536AL
Data Sheet M13609EJ4V0DS
Pin Name and Functions [



PD464536ALS1]
Pin name
Description
Function
V
DD
Core Power Supply
Supplies power for RAM core
V
SS
Ground
V
DD
Q
Output Power Supply
Supplies power for output buffers
K, /K
Main Clock
SA0 to SA16
Synchronous Address Input
DQa1 to DQd9
Synchronous Data Input / Output
/SS
Synchronous Chip Select
Logically selects SRAM
/SW
Synchronous Byte Write Enable
Write command
/SBa
Synchronous Byte "a" Write Enable
Write DQa1 to DQa9
/SBb
Synchronous Byte "b" Write Enable
Write DQb1 to DQb9
/SBc
Synchronous Byte "c" Write Enable
Write DQc1 to DQc9
/SBd
Synchronous Byte "d" Write Enable
Write DQd1 to DQd9
/G
Asynchronous Output Enable
Asynchronous input
ZZ
Sleep Mode Enable
Enables sleep mode, active high
NC
No Connection
TMS
Test Mode Select (JTAG)
TDI
Test Data Input (JTAG)
TCK
Test Clock Input (JTAG)
TDO
Test Data Output (JTAG)
© 2018 • ICSheet
Contact form
Main page