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Datasheet: M12180EJ6V0DSJ1 (NEC)

 

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1996
MOS INTEGRATED CIRCUIT



PD432232L
2M-BIT CMOS SYNCHRONOUS FAST SRAM
64K-WORD BY 32-BIT
PIPELINED OPERATION
Document No. M12180EJ6V0DSJ1 (6th edition)
Date Published November 2000 NS CP(K)
Printed in Japan
DATA SHEET
The mark
shows major revised points.
Description
The
PD432232L is a 65,536-word by 32-bit synchronous static RAM fabricated with advanced CMOS technology
using N-channel four-transistor memory cell.
The
PD432232L integrates unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as
SRAM core. All input registers are controlled by a positive edge of the single clock input (CLK).
The
PD432232L is suitable for applications which require synchronous operation, high speed, low voltage, high
density and wide bit configuration, such as cache and buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State
("Sleep"). In the "Sleep" state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes
normal operation.
The
PD432232LGF is packaged in 100-pin plastic LQFP with a 1.4 mm package thickness for high density and low
capacitive loading.
Features
3.3 V (Chip) / 3.3V or 2.5V (I/O) Supply
Synchronous Operation
Internally self-timed Write control
Burst Read / Write: Interleaved Burst and Linear Burst
Sequence
Fully Registered Inputs and Outputs for Pipelined
operation
All Registers triggered off Positive Clock Edge
Single-Cycle deselect timing
3.3 V or 2.5 V LVTTL Compatible: All Inputs and
Outputs
Fast Clock Access Time: 5 ns / 100 MHz, 7 ns / 83
MHz, 8 ns / 66 MHz
Asynchronous Output Enable: /G
Burst Sequence Selectable: MODE
Sleep Mode: ZZ (ZZ =Open or Low: Normal Operation)
Separate Byte Write Enable: /BW1 - /BW4, /BWE
Global Write Enable: /GW
Three Chip Enables for Easy Depth Expansion
Common I/O Using Three State Outputs
Ordering Information
Part number
Access Time
Clock frequency
Package
PD432232LGF-A5
5 ns
100 MHz
100-PIN PLASTIC LQFP (14 x 20)
PD432232LGF-A7
7 ns
83 MHz
100-PIN PLASTIC LQFP (14 x 20)
PD432232LGF-A8
8 ns
66 MHz
100-PIN PLASTIC LQFP (14 x 20)
2



PD432232L
Data Sheet M12180EJ6V0DS
Pin Configuration (Marking Side)
/xxx indicates active low signal.
100-PIN PLASTIC LQFP (14 x 20)
[



PD432232LGF ]
NC
I/O17
I/O18
V
DD
Q
V
SS
Q
I/O19
I/O20
I/O21
I/O22
V
SS
Q
V
DD
Q
I/O23
I/O24
NC
V
DD
NC
V
SS
I/O25
I/O26
V
DD
Q
V
SS
Q
I/O27
I/O28
I/O29
I/O30
V
SS
Q
V
DD
Q
I/O31
I/O32
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
I/O16
I/O15
V
DD
Q
V
SS
Q
I/O14
I/O13
I/O12
I/O11
V
SS
Q
V
DD
Q
I/O10
I/O9
V
SS
NC
V
DD
ZZ
I/O8
I/O7
V
DD
Q
V
SS
Q
I/O6
I/O5
I/O4
I/O3
V
SS
Q
V
DD
Q
I/O2
I/O1
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6
A7
/CE
CE2
/BW4
/BW3
/BW2
/BW1
/CE2
V
DD
V
SS
CLK
/GW
/BWE
/G
/AC
/AP
/ADV
A8
A9
MODE
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A10
A11
A12
A13
A14
A15
NC
Remark Refer to Package Drawing for the 1-pin index mark.
3



PD432232L
Data Sheet M12180EJ6V0DS
Pin Identification
Symbol
Pin No.
Description
A0 - A15
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49
Synchronous Address Input
I/O1 - I/O32
52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73,
74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19,
22, 23, 24, 25, 28, 29
Synchronous Data In,
Synchronous / Asynchronous Data Out
/ADV
83
Synchronous Burst Address Advance Input
/AP
84
Synchronous Address Status Processor Input
AC
85
Synchronous Address Status Controller Input
/CE, CE2, /CE2
98, 97, 92
Synchronous Chip Enable Input
/BW1 - /BW4, /BWE
93, 94, 95, 96, 87
Synchronous Byte Write Enable Input
/GW
88
Synchronous Global Write Input
/G
86
Asynchronous Output Enable Input
CLK
89
Clock Input
MODE
31
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
ZZ
64
Asynchronous Power Down State Input
V
DD
15, 41, 65, 91
Power Supply
V
SS
17, 40, 67, 90
Ground
V
DD
Q
4, 11, 20, 27, 54, 61, 70, 77
Output Buffer Power Supply
V
SS
Q
5, 10, 21, 26, 55, 60, 71, 76
Output Buffer Ground
NC
1, 14, 16, 30, 38, 39, 42, 43, 50, 51, 66, 80
No Connection
4



PD432232L
Data Sheet M12180EJ6V0DS
Block Diagram
Address
register
Binary
counter
and logic
CLR
Q0
Q1
Byte 1
Write register
Byte 1
Write driver
8
Byte 2
Write register
Byte 2
Write driver
8
Byte 3
Write register
Byte 3
Write driver
8
Byte 4
Write register
Byte 4
Write driver
8
Enable
register
Row & column
decoder
Memory matrix
1,024 rows
64
32 columns
(2,097,152 bits)
Output
register
Output
buffer
Input
register
32
16
16
14
16
A0, A1
A1'
A0'
32
4
32
A0 - A15
MODE
/ADV
CLK
/AC
/AP
/BW1
/BW2
/BW3
/BW4
/BWE
/GW
/CE
CE2
/CE2
/G
I/O1 - I/O32
Enable delay
register
ZZ
Power down control
Burst Sequence
Interleaved Burst Sequence Table (MODE = Open or V
DD
)
External Address
A15 - A2, A1, A0
1st Burst Address
A15 - A2, A1, /A0
2nd Burst Address
A15 - A2, /A1, A0
3rd Burst Address
A15 - A2, /A1, /A0
Linear Burst Sequence Table (MODE = V
SS
)
External Address
A15 - A2, 0, 0
A15 - A2, 0, 1
A15 - A2, 1, 0
A15 - A2, 1, 1
1st Burst Address
A15 - A2, 0, 1
A15 - A2, 1, 0
A15 - A2, 1, 1
A15 - A2, 0, 0
2nd Burst Address
A15 - A2, 1, 0
A15 - A2, 1, 1
A15 - A2, 0, 0
A15 - A2, 0, 1
3rd Burst Address
A15 - A2, 1, 1
A15 - A2, 0, 0
A15 - A2, 0, 1
A15 - A2, 1, 0
5



PD432232L
Data Sheet M12180EJ6V0DS
Asynchronous Truth Table
Operation
/G
I/O
Read Cycle
L
Dout
Read Cycle
H
Hi-Z
Write Cycle
X
Hi-Z, Din
Deselected
X
Hi-Z
Remark X means "don't care."
Synchronous Truth Table
Operation
/CE
CE2
/CE2
/AP
/AC
/ADV
/WRITE
CLK
Address
Deselected
Note
H
X
X
X
L
X
X
L
H
N/A
Deselected
Note
L
L
X
L
X
X
X
L
H
N/A
Deselected
Note
L
X
H
L
X
X
X
L
H
N/A
Deselected
Note
L
L
X
H
L
X
X
L
H
N/A
Deselected
Note
L
X
H
H
L
X
X
L
H
N/A
Read Cycle / Begin Burst
L
H
L
L
X
X
X
L
H
External
Read Cycle / Begin Burst
L
H
L
H
L
X
H
L
H
External
Read Cycle / Continue Burst
X
X
X
H
H
L
H
L
H
Next
Read Cycle / Continue Burst
H
X
X
X
H
L
H
L
H
Next
Read Cycle / Suspend Burst
X
X
X
H
H
H
H
L
H
Current
Read Cycle / Suspend Burst
H
X
X
X
H
H
H
L
H
Current
Write Cycle / Begin Burst
L
H
L
H
L
X
L
L
H
External
Write Cycle / Continue Burst
X
X
X
H
H
L
L
L
H
Next
Write Cycle / Continue Burst
H
X
X
X
H
L
L
L
H
Next
Write Cycle / Suspend Burst
X
X
X
H
H
H
L
L
H
Current
Write Cycle / Suspend Burst
H
X
X
X
H
H
L
L
H
Current
Note Deselect status is held until new "Begin Burst" entry.
Remarks 1. X means "don't care."
2. /WRITE = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) and /BWE are
LOW or /GW is LOW.
/WRITE = H means the following two cases.
(1) /BWE and /GW are HIGH.
(2) /BW1, /BW2, /BW3, /BW4 and /GW are HIGH, and /BWE is LOW.
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