HTML datasheet archive (search documentation on electronic components) Search datasheet (1.687.043 components)
Search field

Datasheet: M10060EJ7V0DSJ1 (NEC)

 

Download: PDF   ZIP
NEC

Document Outline

1994
DATA SHEET
MOS INTEGRATED CIRCUIT
PD485506
LINE BUFFER
5K-WORD BY 16-BIT/10K-WORD BY 8-BIT
The mark shows major revised points.
Document No. M10060EJ7V0DSJ1 (7th edition)
Date Published December 2000 N CP(K)
Printed in Japan
Description
The
PD485506 is a high speed FIFO (First In First Out) line buffer. Word organization can be changed either
5,048 words by 16 bits or 10,096 words by 8 bits. Its CMOS static circuitry provides high speed access and low power
consumption.
The
PD485506 can be used for one line delay and time axis conversion in high speed facsimile machines and
digital copiers.
Moreover, the
PD485506 can execute read and write operations independently on an asynchronous basis. Thus
the
PD485506 is suitable as a buffer for data transfer between units with different transfer rates and as a buffer for
the synchronization of multiple input signals.
There are four versions, E, K, P, X and L. This data sheet can be applied to the version X and L. These versions
operate with different specifications. Each version is identified with its lot number (refer to 7. Example of Stamping).
Features
5,048 words by 16 bits (Word mode) /10,096 words by 8 bits (Byte mode)
Asynchronous read/write operations available
Variable length delay bits; 21 to 5,048 bits or 10,096 bits (Cycle time: 25 ns)
15 to 5,048 bits or 10,096 bits (Cycle time: 35 ns)
Power supply voltage V
CC
= 5.0 V
0.5 V
Suitable for sampling two lines of A3 size paper (16 dots/mm)
All input/output TTL compatible
3-state output
Full static operation; data hold time = infinity
Ordering Information
Part Number
R/W Cycle Time
Package
PD485506G5-25-7JF
25 ns
44-pin plastic TSOP (II) (10.16 mm (400))
PD485506G5-35-7JF
35 ns
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
PD485506
2
Data Sheet M10060EJ7V0DS00
Pin Configuration (Marking side)
44-pin plastic TSOP (
II
) (10.16 mm (400))
[
PD485506G5-7JF]
D
IN0
to D
IN15
: Data Inputs
D
OUT0
to D
OUT15
: Data Outputs
WCK
: Write Clock Input
RCK
: Read Clock Input
WE
: Write Enable Input
RE
: Read Enable Input
OE
: Output Enable Input
RSTW
: Reset Write Input
RSTR
: Reset Read Input
MD
: Mode Set Input
V
CC
: +5.0 V Power Supply
GND
: Ground
Remark
Refer to Package Drawing for the 1-pin index mark.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
D
IN0
D
IN1
D
IN2
D
IN3
D
IN4
D
IN5
D
IN6
D
IN7
WE
MD
GND
RSTW
WCK
V
CC
D
IN8
D
IN9
D
IN10
D
IN11
D
IN12
D
IN13
D
IN14
D
IN15
D
OUT0
D
OUT1
D
OUT2
D
OUT3
D
OUT4
D
OUT5
D
OUT6
D
OUT7
RE
GND
RSTR
RCK
V
CC
D
OUT8
D
OUT9
D
OUT10
D
OUT11
D
OUT12
D
OUT13
D
OUT14
D
OUT15
OE
PD485506
3
Data Sheet M10060EJ7V0DS00
Block Diagram
WE
D
OUT0
D
OUT1
D
OUT2
D
OUT3
D
OUT4
D
OUT5
D
OUT6
D
OUT7
RSTR
RE
V
CC
GND
Write Address Pointer
Mode Controller
40,384 bits
(5,048 words by 8 bits)
Memory Cell Array
RSTW
WCK
RCK
Output Buffer
Read Address Pointer
40,384 bits
(5,048 words by 8 bits)
Memory Cell Array
Input Buffer
Output Buffer
D
OUT8
D
OUT9
D
OUT10
D
OUT11
D
OUT12
D
OUT13
D
OUT14
D
OUT15
Output Controller
Output Controller
OE
MD
D
IN0
D
IN1
D
IN2
D
IN3
D
IN4
D
IN5
D
IN6
D
IN7
D
IN8
D
IN9
D
IN10
D
IN11
D
IN12
D
IN13
D
IN14
D
IN15
Input Buffer
Input Controller
Input Controller
PD485506
4
Data Sheet M10060EJ7V0DS00
1. Input/Output Pin Function
Pin
Pin
Symbol
Pin
Number
Name
44 37,
D
IN0
Data
|
Input
30 23
D
IN15
1 8,
D
OUT0
Data
|
Output
15 22
D
OUT15
33
RSTW
Reset
Write
Input
12
RSTR
Reset
Read
Input
36
WE
Write
Enable
Input
10
RE
Read
Enable
Input
9
OE
Output
Enable
Input
32
WCK
Write
Clock
Input
13
RCK
Read
Clock
Input
35
MD
Mode
Set
Input
I/O
Function
In
Write data input pins.
The data inputs are strobed by the rising edge of WCK at the end of a cycle
and the setup and hold times (t
DS
, t
DH
) are defined at this point.
Out
Read data output pins.
The access time is regulated from the rising edge of RCK at the beginning of a
cycle and defined by t
AC
.
In
Reset input pin for the initialization of the write address pointer.
The state of RSTW is strobed by the rising edge of WCK at the beginning of a
cycle and the setup and hold times (t
RS
, t
RH
) are defined.
In
Reset input pin for the initialization of the read address pointer.
The state of RSTR is strobed by the rising edge of RCK at the beginning of a
cycle and the setup and hold times (t
RS
, t
RH
) are defined.
In
Write operation control signal input pin.
When WE is in the disable mode ("H" level), the internal write operation is
inhibited and the write address pointer stops at the current position.
In
Read operation control signal input pin.
When RE is in the disable mode ("H" level), the internal read operation is
inhibited and the read address pointer stops at the current position. The data
outputs remain valid for that address.
In
Output operation control signal input pin.
When OE is in the disable mode ("H" level), the data out is inhibited and the
output changes to high impedance. The internal read operation is executed at
that time and the read address pointer incremented in synchronization with the
read clock.
In
Write clock input pin.
When WE is enabled ("L" level), the write operation is executed in
synchronization with the write clock. The write address pointer is incremented
simultaneously.
In
Read clock input pin.
When RE is enabled ("L" level), the read operation is executed in synchroniza-
tion with the read clock. The read address pointer is incremented
simultaneously.
In
Mode set input pin.
The level of MD gives the operation mode. When MD is in "L" level,
5,048 words by 16 bits configuration with D
IN0
- D
IN15
, D
OUT0
- D
OUT15
is enabled.
When MD is in "H" level, 10,096 words by 8 bits configuration with D
IN0
- D
IN7
,
D
OUT0
- D
OUT7
is enabled.
PD485506
5
Data Sheet M10060EJ7V0DS00
2. Operation Mode
PD485506 is a synchronous memory. All signals are strobed at the rising edge of the clock (RCK, WCK).
For this reason, setup time and hold time are specified for the rising edge of the clock (RCK, WCK).
2.1 Mode Set Cycle (5,048 words by 16 bits or 10,096 words by 8 bits organization)
PD485506 has a capability of selecting from two operation modes by judging the MD level when RSTW or
RSTR is enabled in the reset cycle.
MD Level
Bit Configuration
Data Inputs/Outputs
Control Signal
"L"
5,048 words by 16 bits
D
IN0
- D
IN15
WCK, WE, RSTW
D
OUT0
- D
OUT15
RCK, RE, RSTR
"H"
10,096 words by 8 bits
D
IN0
- D
IN7
WCK, WE, RSTW
D
OUT0
- D
OUT7
RCK, RE, RSTR
Caution
Don't change the MD level during a reset cycle. (See Figure 4.6, 7, 8, 9 Mode Set Cycle Timing
Chart)
5,048 Words by 16 Bits FIFO
WCK
WE
RSTW
D
IN0
- D
IN15
D
OUT0
- D
OUT15
OE
RSTR
RE
RCK
5,048 Words
by
16 Bits
10,096 Words by 8 Bits FIFO
OE
RSTR
RE
RCK
D
IN0
- D
IN7
D
OUT0
- D
OUT7
WCK
WE
RSTW
10,096 Words by 8 Bits
Remark
Fix D
IN8
- D
IN15
to "L" or "H" level in the 10,096 words by 8 bits mode.
© 2018 • ICSheet
Contact form
Main page