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Datasheet: M16C62A (Mitsubishi Electric Semiconductor)

Single-chip 16-bit Cmos Microcomputer

 

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Mitsubishi Electric Semiconductor

Document Outline

Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
1
------Table of Contents------
Description
The M16C/62A group of single-chip microcomputers are built using the high-performance silicon gate
CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP.
These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruc-
tion efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed.
They also feature a built-in multiplier and DMAC, making them ideal for controlling office, communications,
industrial equipment, and other high-speed processing applications.
The M16C/62A group includes a wide range of products with different internal memory types and sizes and
various package types.
Features
Memory capacity .................................. ROM (See Figure 1.1.4. ROM Expansion)
RAM 3K to 20K bytes
Shortest instruction execution time ...... 62.5ns (f(X
IN
)=16MH
Z
, V
CC
=5V)
100ns (f(X
IN
)=10MH
Z
, V
CC
=3V, with software one-wait) : Mask ROM, flash memory 5V version
Supply voltage ..................................... 4.2V to 5.5V (f(X
IN
)=16MH
Z
, without software wait) : Mask ROM, flash memory 5V version
2.7V to 5.5V (f(X
IN
)=10MH
Z
with software one-wait) : Mask ROM, flash memory 5V version
Low power consumption ...................... 25.5mW ( f(X
IN
)=10MH
Z
, with software one-wait, V
CC
= 3V)
Interrupts .............................................. 25 internal and 8 external interrupt sources, 4 software
interrupt sources; 7 levels (including key input interrupt)
Multifunction 16-bit timer ...................... 5 output timers + 6 input timers
Serial I/O .............................................. 5 channels (3 for UART or clock synchronous, 2 for clock synchro-
nous)
DMAC .................................................. 2 channels (trigger: 24 sources)
A-D converter ....................................... 10 bits X 8 channels (Expandable up to 10 channels)
D-A converter ....................................... 8 bits X 2 channels
CRC calculation circuit ......................... 1 circuit
Watchdog timer .................................... 1 line
Programmable I/O ............................... 87 lines
Input port ..............................................
_______
1 line (P8
5
shared with NMI pin)
Memory expansion .............................. Available (to a maximum of 1M bytes)
Chip select output ................................ 4 lines
Clock generating circuit ....................... 2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
Applications
Audio, cameras, office equipment, communications equipment, portable equipment
Timer ............................................................. 77
Serial I/O ..................................................... 107
A-D Converter ............................................. 148
D-A Converter ............................................. 158
CRC Calculation Circuit .............................. 160
Programmable I/O Ports ............................. 162
Electrical characteristic ............................... 173
Flash memory version ................................. 216
Central Processing Unit (CPU) ..................... 11
Reset ............................................................. 14
Processor Mode ............................................ 21
Clock Generating Circuit ............................... 35
Protection ...................................................... 44
Interrupts ....................................................... 45
Watchdog Timer ............................................ 65
DMAC ........................................................... 67
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
2
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P0
0
/D
0
P0
1
/D
1
P0
2
/D
2
P0
3
/D
3
P0
4
/D
4
P0
5
/D
5
P0
6
/D
6
P0
7
/D
7
P1
0
/D
8
P1
1
/D
9
P1
2
/D
10
P1
3
/D
11
P1
4
/D
12
V
REF
AV
SS
V
CC
X
IN
X
OUT
V
SS
RESET
CNVss
P8
7
/X
CIN
P8
6
/X
COUT
BYTE
P2
0
/A
0
(/D
0
/-)
P2
1
/A
1
(/D
1
/D
0
)
P2
2
/A
2
(/D
2
/D
1
)
P2
3
/A
3
(/D
3
/D
2
)
P2
4
/A
4
(/D
4
/D
3
)
P2
5
/A
5
(/D
5
/D
4
)
P2
6
/A
6
(/D
6
/D
5
)
P2
7
/A
7
(/D
7
/D
6
)
P3
0
/A
8
(/-/D
7
)
P3
1
/A
9
P3
2
/A
10
P3
3
/A
11
P3
4
/A
12
P3
5
/A
13
P3
6
/A
14
P3
7
/A
15
P4
0
/A
16
P4
1
/A
17
P4
2
/A
18
P4
3
/A
19
P7
4
/TA2
OUT
/W
P7
6
/TA3
OUT
P5
6
/ALE
P7
7
/TA3
IN
P5
5
/HOLD
P5
4
/HLDA
P5
3
/BCLK
P5
2
/RD
Vcc
Vss
P5
7
/RDY/CLK
OUT
P4
5
/CS1
P4
6
/CS2
P4
7
/CS3
AVcc
P6
3
/T
X
D
0
P6
5
/CLK
1
P6
6
/RxD
1
P6
7
/T
X
D
1
P6
1
/CLK
0
P6
2
/RxD
0
P10
0
/AN
0
P10
1
/AN
1
P10
2
/AN
2
P10
3
/AN
3
P9
3
/DA
0
/TB3
IN
P9
4
/DA
1
/TB4
IN
P9
5
/ANEX0/CLK4
P9
6
/ANEX1/S
OUT
4
P9
1
/TB1
IN
/S
IN
3
P9
2
/TB2
IN
/S
OUT
3
P8
0
/TA4
OUT
/U
P6
0
/CTS
0
/RTS
0
P6
4
/CTS
1
/RTS
1
/CLKS
1
P7
2
/CLK
2
/TA1
OUT
/V
P8
2
/INT
0
P7
1
/RxD
2
/SCL/TA0
IN
/TB5
IN
(Note)
P8
3
/INT
1
P8
5
/NMI
P9
7
/AD
TRG
/S
IN
4
P4
4
/CS0
P5
0
/WRL/WR
P5
1
/WRH/BHE
P9
0
/TB0
IN
/CLK3
P7
0
/T
X
D
2
/SDA/TA0
OUT
(Note)
P8
4
/INT
2
P8
1
/TA4
IN
/U
P7
5
/TA2
IN
/W
P1
5
/D
13
/INT3
P1
6
/D
14
/INT4
P1
7
/D
15
/INT5
P10
7
/AN
7
/KI
3
P10
6
/AN
6
/KI
2
P10
5
/AN
5
/KI
1
P10
4
/AN
4/
KI
0
P7
3
/CTS
2
/RTS
2
/TA1
IN
/V
Note: P7
0
and P7
1
are N channel open-drain output pin.
Pin Configuration
Figures 1.1.1 and 1.1.2 show the pin configurations (top view).
PIN CONFIGURATION (top view)
Package: 100P6S-A
Figure 1.1.1. Pin configuration (top view)
M16C/62A Group
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
3
1 2
3
4
5
6
7
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P0
0
/D
0
P0
1
/D
1
P0
2
/D
2
P0
3
/D
3
P0
4
/D
4
P0
5
/D
5
P0
6
/D
6
P0
7
/D
7
P1
0
/D
8
P1
1
/D
9
P1
2
/D
10
P1
3
/D
11
P1
4
/D
12
V
REF
AV
SS
V
CC
X
IN
X
OUT
V
SS
RESET
CNVss
P8
7
/X
CIN
P8
6
/X
COUT
BYTE
P2
0
/A
0
(/D
0
/-)
P2
1
/A
1
(/D
1
/D
0
)
P2
2
/A
2
(/D
2
/D
1
)
P2
3
/A
3
(/D
3
/D
2
)
P2
4
/A
4
(/D
4
/D
3
)
P2
5
/A
5
(/D
5
/D
4
)
P2
6
/A
6
(/D
6
/D
5
)
P2
7
/A
7
(/D
7
/D
6
)
P3
0
/A
8
(/-/D
7
)
P3
1
/A
9
P3
2
/A
10
P3
3
/A
11
P3
4
/A
12
P3
5
/A
13
P3
6
/A
14
P3
7
/A
15
P4
0
/A
16
P4
1
/A
17
P4
2
/A
18
P4
3
/A
19
P7
4
/TA2
OUT
/W
P7
6
/TA3
OUT
P5
6
/ALE
P7
7
/TA3
IN
P5
5
/HOLD
P5
4
/HLDA
P5
3
/BCLK
P5
2
/RD
Vcc
Vss
P5
7
/RDY/CLK
OUT
P4
5
/CS1
P4
6
/CS2
P4
7
/CS3
AVcc
P6
3
/T
X
D
0
P6
5
/CLK
1
P6
6
/RxD
1
P6
7
/T
X
D
1
P6
1
/CLK
0
P6
2
/RxD
0
P10
0
/AN
0
P10
1
/AN
1
P10
2
/AN
2
P10
3
/AN
3
P9
3
/DA
0
/TB3
IN
P9
4
/DA
1
/TB4
IN
P9
5
/ANEX0/CLK4
P9
6
/ANEX1/S
OUT
4
P9
1
/TB1
IN
/S
IN
3
P9
2
/TB2
IN
/S
OUT
3
P8
1
/TA4
IN
/U
P8
0
/TA4
OUT
/U
P6
0
/CTS
0
/RTS
0
P6
4
/CTS
1
/RTS
1
/CLKS
1
P8
2
/INT
0
P8
3
/INT
1
P8
5
/NMI
P9
7
/AD
TRG
/S
IN
4
P4
4
/CS0
P5
0
/WRL/WR
P5
1
/WRH/BHE
P9
0
/TB0
IN
/CLK3
P8
4
/INT
2
P7
2
/CLK
2
/TA1
OUT
/V
P7
1
/RxD
2
/SCL/TA0
IN
/TB5
IN
(Note)
P7
0
/T
X
D
2
/SDA/TA0
OUT
(Note)
P7
5
/TA2
IN
/W
P7
3
/CTS
2
/RTS
2
/TA1
IN
/V
P1
5
/D
13
/INT
3
P1
6
/D
14
/INT
4
P1
7
/D
15
/INT
5
P10
7
/AN
7
/KI
3
P10
6
/AN
6
/KI
2
P10
5
/AN
5
/KI
1
P10
4
/AN
4/
KI
0
Note: P7
0
and P7
1
are N channel open-drain output pin.
Figure 1.1.2. Pin configuration (top view)
Package: 100P6Q-A
PIN CONFIGURATION (top view)
M16C/62A Group
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
4
Block Diagram
Figure 1.1.3 is a block diagram of the M16C/62A group.
Timer
Timer TA0 (16 bits)
Timer TA1 (16 bits)
Timer TA2 (16 bits)
Timer TA3 (16 bits)
Timer TA4 (16 bits)
Timer TB0 (16 bits)
Timer TB1 (16 bits)
Timer TB2 (16 bits)
Timer TB3 (16 bits)
Timer TB4 (16 bits)
Timer TB5 (16 bits)
Internal peripheral functions
Watchdog timer
(15 bits)
DMAC
(2 channels)
D-A converter
(8 bits X 2 channels)
A-D converter
(10 bits
X
8 channels
Expandable up to 10 channels)
UART/clock synchronous SI/O
(8 bits
X
3 channels)
System clock generator
X
IN
-X
OUT
X
CIN
-X
COUT
M16C/60 series16-bit CPU core
I/O ports
Port P0
8
Port P1
8
Port P2
8
Port P3
8
Port P4
8
Port P5
8
Port P6
8
8
R0L
R0H
R1H
R1L
R2
R3
A0
A1
FB
R0L
R0H
R1H
R1L
R2
R3
A0
A1
FB
Registers
ISP
USP
Stack pointer
CRC arithmetic circuit (CCITT )
(Polynomial : X
16
+X
12
+X
5
+1)
Multiplier
7
8
8
Port P10
Port P9
Port P8
Port P7
Memory
Port P8
5
ROM
(Note 1)
RAM
(Note 2)
Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.
SB
FLG
PC
Program counter
Clock synchronous SI/O
(8 bits
X
2 channels)
Vector table
INTB
Flag register
Figure 1.1.3. Block diagram of M16C/62A group
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
5
Item
Performance
Number of basic instructions
91 instructions
Shortest instruction execution time
62.5ns(f(X
IN
)=16MH
Z
, V
CC
=5V)
100ns (f(X
IN
)=10MH
Z
, V
CC
=3V, with software one-wait)
: Mask ROM, flash memory 5V version
Memory
ROM
(See the figure 1.1.4. ROM Expansion)
capacity
RAM
3K to 20K bytes
I/O port
P0 to P10 (except P8
5
)
8 bits x 10, 7 bits x 1
Input port
P8
5
1 bit x 1
Multifunction TA0, TA1, TA2, TA3, TA4
16 bits x 5
timer
TB0, TB1, TB2, TB3, TB4, TB5
16 bits x 6
Serial I/O
UART0, UART1, UART2
(UART or clock synchronous) x 3
SI/O3, SI/O4
(Clock synchronous) x 2
A-D converter
10 bits x (8 + 2) channels
D-A converter
8 bits x 2
DMAC
2 channels (trigger: 24 sources)
CRC calculation circuit
CRC-CCITT
Watchdog timer
15 bits x 1 (with prescaler)
Interrupt
25 internal and 8 external sources, 4 software sources, 7 levels
Clock generating circuit
2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
Supply voltage
4.2V to 5.5V (f(X
IN
)=16MH
Z
, without software wait)
: Mask ROM, flash memory 5V version
2.7V to 5.5V (f(X
IN
)=10MH
Z
with software one-wait)
: Mask ROM, flash memory 5V version
Power consumption
25.5mW (f(X
IN
) = 10MH
Z
, V
CC
=3V with software one-wait)
I/O
I/O withstand voltage
5V
characteristics Output current
5mA
Memory expansion
Available (to a maximum of 1M bytes)
Device configuration
CMOS high performance silicon gate
Package
100-pin plastic mold QFP
Table 1.1.1. Performance outline of M16C/62A group
Performance Outline
Table 1.1.1 is a performance outline of M16C/62A group.
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
6
Mitsubishi plans to release the following products in the M16C/62A group:
(1) Support for mask ROM version, external ROM version, and flash memory version
(2) ROM capacity
(3) Package
100P6S-A
: Plastic molded QFP (mask ROM, and flash memory versions)
100P6Q-A
: Plastic molded QFP(mask ROM, and flash memory versions)
The M16C/62A group products currently supported are listed in Table 1.1.2.
Table 1.1.2. M16C/62A group
ROM Size
(Byte)
External
ROM
128K
96K
64K
32K
M30620M8A-XXXFP/GP
M30622M8A-XXXFP/GP
M30620MAA-XXXFP/GP
M30622MAA-XXXFP/GP
M30620MCA-XXXFP/GP
M30622MCA-XXXFP/GP
Mask ROM version
Flash memory version
M30624FGAFP/GP
256K
M30624MGA-XXXFP/GP
M30622M4A-XXXFP/GP
External ROM version
M30620SAFP/GP
M30622SAFP/GP
M30620FCAFP/GP
RAM capacity
ROM capacity
Package type
Remarks
Type No.
March. 2001
M30622M4A-XXXFP
3K byte
100P6S-A
M30622M4A-XXXGP
100P6Q-A
M30620M8A-XXXFP
64K byte
10K byte
100P6S-A
Mask ROM version
M30620M8A-XXXGP
100P6Q-A
M30622M8A-XXXFP
4K byte
100P6S-A
M30622M8A-XXXGP
100P6Q-A
M30620MAA-XXXFP
10K byte
100P6S-A
3K byte
M30622SAFP
External ROM
version
M30622SAGP
100P6Q-A
100P6S-A
10K byte
M30620MCA-XXXGP
M30620MCA-XXXFP
M30622MCA-XXXFP
M30622MCA-XXXGP
5K byte
128K byte
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
M30620SAFP
10K byte
100P6Q-A
M30620SAGP
M30620MAA-XXXGP
96K byte
100P6Q-A
M30622MAA-XXXFP
5K byte
100P6S-A
M30622MAA-XXXGP
100P6Q-A
M30624MGA-XXXFP
20K byte
100P6S-A
M30624MGA-XXXGP
100P6Q-A
256K byte
M30624FGAFP
M30624FGAGP
20K byte
256K byte
Flash memory
5V version
100P6S-A
100P6Q-A
32K byte
**
: Under development
**
M30620FCAFP
M30620FCAGP
10K byte
128K byte
100P6S-A
100P6Q-A
Figure 1.1.4. ROM expansion
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
7
Package type:
FP : Package
100P6S-A
GP :
100P6Q-A
ROM No.
Omitted for flash memory version
ROM capacity:
4 : 32K bytes
8 : 64K bytes
A : 96K bytes
C : 128K bytes
G: 256K bytes
Memory type:
M : Mask ROM version
S : External ROM version
F : Flash memory version
Type No. M 3 0 6 2 2 M 8 A X X X F P
M16C/62 Group
M16C Family
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
Figure 1.1.5. Type No., memory size, and package
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
8
V
CC
, V
SS
CNV
SS
X
IN
X
OUT
BYTE
AV
CC
AV
SS
V
REF
P0
0
to P0
7
D
0
to D
7
P1
0
to P1
7
D
8
to D
15
P2
0
to P2
7
A
0
to A
7
A
0
/D
0
to
A
7
/D
7
A
0
A
1
/D
0
to A
7
/D
6
P3
0
to P3
7
A
8
to A
15
A
8
/D
7
,
A
9
to A
15
P4
0
to P4
7
Signal name
Power supply
input
CNV
SS
Reset input
Clock input
Clock output
External data
bus width
select input
Analog power
supply input
Reference
voltage input
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
Supply 2.7V to 5.5 V to the V
CC
pin. Supply 0 V to the V
SS
pin.
Function
This pin switches between processor modes. Connect this pin to the
V
SS
pin when after a reset you want to start operation in single-chip
mode (memory expansion mode) or the V
CC
pin when starting
operation in microprocessor mode.
A "L" on this input resets the microcomputer.
These pins are provided for the main clock generating circuit.Connect
a ceramic resonator or crystal between the X
IN
and the X
OUT
pins. To
use an externally derived clock, input it to the X
IN
pin and leave the
X
OUT
pin open.
This pin selects the width of an external data bus. A 16-bit width is
selected when this input is "L"; an 8-bit width is selected when this
input is "H". This input must be fixed to either "H" or "L". Connect this
pin to the V
SS
pin when not using external data bus.
This pin is a power supply input for the A-D converter. Connect this
pin to V
CC
.
This pin is a power supply input for the A-D converter. Connect this
pin to V
SS
.
This pin is a reference voltage input for the A-D converter.
This is an 8-bit CMOS I/O port. It has an input/output port direction
register that allows the user to set each pin for input or output
individually. When used for input in single-chip mode, the port can be
set to have or not have a pull-up resistor in units of four bits by
software. In memory expansion and microprocessor modes, selection
of the internal pull-resistor is not available.
When set as a separate bus, these pins input and output data (D
0
D
7
).
This is an 8-bit I/O port equivalent to P0. P1
5
to P1
7
also function as
external interrupt pins as selected by software.
When set as a separate bus, these pins input and output data
(D
8
D
15
).
This is an 8-bit I/O port equivalent to P0.
These pins output 8 low-order address bits (A
0
A
7
).
If the external bus is set as an 8-bit wide multiplexed bus, these pins
input and output data (D
0
D
7
) and output 8 low-order address bits
(A
0
A
7
) separated in time by multiplexing.
If the external bus is set as a 16-bit wide multiplexed bus, these pins
input and output data (D
0
D
6
) and output address (A
1
A
7
) separated
in time by multiplexing. They also output address (A
0
).
This is an 8-bit I/O port equivalent to P0.
These pins output 8 middle-order address bits (A
8
A
15
).
If the external bus is set as a 16-bit wide multiplexed bus, these pins
input and output data (D
7
) and output address (A
8
) separated in time
by multiplexing. They also output address (A
9
A
15
).
This is an 8-bit I/O port equivalent to P0.
Pin name
Input
Input
Input
Output
Input
Input
Input/output
Input/output
Input/output
Input/output
I/O type
Analog power
supply input
Input/output
Output
Input/output
Output
Input/output
Input/output
Output
Input/output
Output
Input/output
Output
Output
A
16
to A
19
,
CS
0
to CS
3
These pins output A
16
A
19
and CS
0
CS
3
signals. A
16
A
19
are 4 high-
order address bits. CS
0
CS
3
are chip select signals used to specify an
access space.
RESET
Pin Description
Pin Description
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
9
Pin Description
Signal name
Function
Pin name
I/O type
I/O port P5
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input
Input/output
Input/output
I/O port P6
I/O port P7
I/O port P8
I/O port P8
5
I/O port P9
I/O port P10
P5
0
to P5
7
P6
0
to P6
7
P7
0
to P7
7
P8
0
to P8
4
,
P8
6
,
P8
7
,
P8
5
P9
0
to P9
7
P10
0
to P10
7
This is an 8-bit I/O port equivalent to P0. In single-chip mode, P5
7
in
this port outputs a divide-by-8 or divide-by-32 clock of X
IN
or a clock of
the same frequency as X
CIN
as selected by software.
Output
Output
Output
Output
Output
Input
Output
Input
This is an 8-bit I/O port equivalent to P0. When used for input in single-
chip, memory expansion, and microprocessor modes, the port can be
set to have or not have a pull-up resistor in units of four bits by
software. Pins in this port also function as UART0 and UART1 I/O pins
as selected by software.
This is an 8-bit I/O port equivalent to P6 (P7
0
and P7
1
are N channel
open-drain output). Pins in this port also function as timer A
0
A
3
,
timer B5 or UART2 I/O pins as selected by software.
This is an 8-bit I/O port equivalent to P6. Pins in this port also function
as SI/O3, 4 I/O pins, Timer B0B4 input pins, D-A converter output pins,
A-D converter extended input pins, or A-D trigger input pins as selected
by software.
This is an 8-bit I/O port equivalent to P6. Pins in this port also function
as A-D converter input pins as selected by software. Furthermore, P10
4
P10
7
also function as input pins for the key input interrupt function.
WRL / WR,
WRH / BHE,
RD,
BCLK,
HLDA,
HOLD,
ALE,
RDY
Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE
signals. WRL and WRH, and BHE and WR can be switched using
software control.
WRL, WRH, and RD selected
With a 16-bit external data bus, data is written to even addresses
when the WRL signal is "L" and to the odd addresses when the WRH
signal is "L". Data is read when RD is "L".
WR, BHE, and RD selected
Data is written when WR is "L". Data is read when RD is "L". Odd
addresses are accessed when BHE is "L". Use this mode when using
an 8-bit external data bus.
While the input level at the HOLD pin is "L", the microcomputer is
placed in the hold state. While in the hold state, HLDA outputs a "L"
level. ALE is used to latch the address. While the input level of the
RDY pin is "L", the microcomputer is in the ready state.
P8
0
to P8
4
, P8
6
, and P8
7
are I/O ports with the same functions as P6.
Using software, they can be made to function as the I/O pins for timer
A4 and the input pins for external interrupts. P8
6
and P8
7
can be set
using software to function as the I/O pins for a sub clock generation
circuit. In this case, connect a quartz oscillator between P8
6
(X
COUT
pin) and P8
7
(X
CIN
pin). P8
5
is an input-only port that also functions
for NMI. The NMI interrupt is generated when the input at this pin
changes from "H" to "L". The NMI function cannot be cancelled using
software. The pull-up cannot be set for this pin.
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
10
Operation of Functional Blocks
The M16C/62A group accommodates certain units in a single chip. These units include ROM and RAM to
store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations.
Also included are peripheral units such as timers, serial I/O, D-A converter, DMAC, CRC calculation circuit,
A-D converter, and I/O ports.
The following explains each unit.
Memory
Figure 1.3.1 is a memory map of the M16C/62A group. The address space extends the 1M bytes from
address 00000
16
to FFFFF
16
. From FFFFF
16
down is ROM. For example, in the M30622MCA-XXXFP,
there is 128K bytes of internal ROM from E0000
16
to FFFFF
16
. The vector table for fixed interrupts such as
_______
the reset and NMI are mapped to FFFDC
16
to FFFFF
16
. The starting address of the interrupt routine is
stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the
internal register (INTB). See the section on interrupts for details.
From 00400
16
up is RAM. For example, in the M30622MCA-XXXFP, 5K bytes of internal RAM is mapped
to the space from 00400
16
to 017FF
16
. In addition to storing data, the RAM also stores the stack used when
calling subroutines and when interrupts are generated.
The SFR area is mapped to 00000
16
to 003FF
16
. This area accommodates the control registers for periph-
eral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Figures 1.6.1 to 1.6.3 are location
of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and cannot be
used for other purposes.
The special page vector table is mapped to FFE00
16
to FFFDB
16
. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions
can be used as 2-byte instructions, reducing the number of program steps.
In memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be
used. For example, in the M30622MCA-XXXFP, the following spaces cannot be used.
The space between 01800
16
and 03FFF
16
(Memory expansion and microprocessor modes)
The space between D0000
16
and DFFFF
16
(Memory expansion mode)
Figure 1.3.1. Memory map
00000
16
YYYYY
16
FFFFF
16
00400
16
04000
16
XXXXX
16
D0000
16
External area
Internal ROM area
SFR area
For details, see Figures
1.6.1 to 1.6.3
Internal RAM area
Internal reserved
area (Note 1)
Internal reserved
area (Note 2)
FFE00
16
FFFDC
16
FFFFF
16
Note 1: During memory expansion and microprocessor modes, can not be used.
Note 2: In memory expansion mode, can not be used.
Note 3: These memory maps show an instance in which PM13 is set to 0; but in the
case of products in which the internal RAM and the internal ROM are expanded
to over 15 Kbytes and 192 Kbytes, respectively, they show an instance in which
PM13 is set to 1.
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer
Reset
Special page
vector table
DBC
NMI
Address YYYYY
16
3K bytes
00FFF
16
053FF
16
017FF
16
013FF
16
Address XXXXX
16
ROM size
02BFF
16
5K bytes
4K bytes
10K bytes
20K bytes
RAM size
32K bytes
C0000
16
E8000
16
F0000
16
E0000
16
96K bytes
64K bytes
128K bytes
256K bytes
F8000
16
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
11
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 1.4.1. Seven of these registers (R0, R1, R2, R3, A0,
A1, and FB) come in two sets; therefore, these have two register banks.
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),
and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can
use as 32-bit data registers (R2R0/R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
H
L
b15
b8
b7
b0
R0
(Note)
H
L
b15
b8
b7
b0
R1
(Note)
R2
(Note)
b15
b0
R3
(Note)
b15
b0
A0
(Note)
b15
b0
A1
(Note)
b15
b0
FB
(Note)
b15
b0
Data
registers
Address
registers
Frame base
registers
b15
b0
b15
b0
b15
b0
b15
b0
b0
b19
b0
b19
H
L
Program counter
Interrupt table
register
User stack pointer
Interrupt stack
pointer
Static base
register
Flag register
PC
INTB
USP
ISP
SB
FLG
Note: These registers consist of two register banks.
C
D
Z
S
B
O
I
U
IPL
Figure 1.4.1. Central processing unit register
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
12
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-
ured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.4.2 shows the flag
register (FLG). The following explains the function of each flag:
Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is "1", a single-step interrupt is generated after instruction execution. This flag is
cleared to "0" when the interrupt is acknowledged.
Bit 2: Zero flag (Z flag)
This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, cleared to "0".
Bit 3: Sign flag (S flag)
This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, cleared to "0".
Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is "0" ; register bank 1 is
selected when this flag is "1".
Bit 5: Overflow flag (O flag)
This flag is set to "1" when an arithmetic operation resulted in overflow; otherwise, cleared to "0".
Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is "0", and is enabled when this flag is "1". This flag is cleared to
"0" when the interrupt is acknowledged.
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
13
Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is "0" ; user stack pointer (USP) is selected
when this flag is "1".
This flag is cleared to "0" when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
Bits 8 to 11: Reserved area
Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for
details.
Figure 1.4.2. Flag register (FLG)
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Flag register (FLG)
C
D
Z
S
B
O
I
U
IPL
b0
b15
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
14
Figure 1.5.2. Reset sequence
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See "Software Reset" for details of software resets.) This section explains on hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
reset pin level "L" (0.2V
CC
max.) for at least 20 cycles. When the reset pin level is then returned to the "H"
level while main clock is stable, the reset status is cancelled and program execution resumes from the
address in the reset vector table.
Figure 1.5.1 shows the example reset circuit. Figure 1.5.2 shows the reset sequence.
Figure 1.5.1. Example reset circuit
BCLK
Address
Address
Address
Microprocessor
mode BYTE = "H"
Microprocessor
mode BYTE = "L"
Content of reset vector
Single chip
mode
BCLK 24cycles
FFFFC
16
FFFFD
16
FFFFE
16
Content of reset vector
FFFFC
16
FFFFE
16
Content of reset vector
FFFFE
16
X
IN
RESET
RD
WR
CS0
RD
WR
CS0
FFFFC
16
More than 20 cycles are needed
RESET
V
CC
0.8V
RESET
V
CC
0V
0V
5V
5V
4.0V
Example when V
CC
= 5V
.
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
15
____________
Table 1.5.1 shows the statuses of the other pins while the RESET pin level is "L". Figures 1.5.3 and 1.5.4
show the internal status of the microcomputer immediately after the reset is cancelled.
____________
Table 1.5.1. Pin status when RESET pin level is "L"
Status
CNV
SS
= V
CC
CNV
SS
= V
SS
BYTE = V
SS
BYTE = V
CC
Pin name
P0
P1
P2, P3, P4
0
to P4
3
P4
4
P4
5
to P4
7
P5
0
P5
1
P5
2
P5
3
P5
4
P5
5
P5
6
P5
7
P6, P7, P8
0
to P8
4
,
P8
6
, P8
7
, P9, P10
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Data input (floating)
Data input (floating)
Address output (undefined)
BCLK output
ALE output ("L" level is output)
CS0 output ("H" level is output)
WR output ("H" level is output)
RD output ("H" level is output)
RDY input (floating)
Input port (floating)
BCLK output
BHE output (undefined)
HLDA output (The output value
depends on the input to the
HOLD pin)
HOLD input (floating)
Data input (floating)
Address output (undefined)
CS0 output ("H" level is output)
Input port (floating)
(pull-up resistor is on)
Input port (floating)
Input port (floating)
RDY input (floating)
ALE output ("L" level is output)
HOLD input (floating)
HLDA output (The output value
depends on the input to the
HOLD pin)
RD output ("H" level is output)
BHE output (undefined)
WR output ("H" level is output)
Input port (floating)
(pull-up resistor is on)
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
16
Figure 1.5.3. Device's internal status after a reset is cleared
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Note 1: When the V
CC
level is applied to the CNV
SS
pin, it is 03
16
at a reset.
Note 2: "00
16
" is read out when set bit 7 (SDDS) of the UART2 special mode register ( address 0377
16
) to "1".
(1)
(0004
16
)
Processor mode register 0 (Note 1)
00
16
(2)
(0005
16
)
Processor mode register 1
0
0
0
(3)
(0006
16
)
System clock control register 0
1
0
0
0
0
1
0
0
(4)
(0007
16
)
System clock control register 1
0
0
0
1
0
0
0
0
(5)
(0008
16
)
Chip select control register
0
0
0
0
0
0
1
0
(6)
(0009
16
)
Address match interrupt enable register
0
0
(7) Protect register
(000A
16
)
0
0
0
(9)
(000F
16
)
Watchdog timer control register
0
0
?
0
? ? ? ?
(11)
(0014
16
)
Address match interrupt register 1
(0015
16
)
(0016
16
)
0
00
16
00
16
0 0 0
(12)
(002C
16
)
DMA0 control register
0 0 0 0 0 ? 0 0
(13)
(003C
16
)
DMA1 control register
0 0 0 0 0 ? 0 0
(21)
(004B
16
)
DMA0 interrupt control register
? 0 0 0
(22)
(004C
16
)
DMA1 interrupt control register
? 0 0 0
(23)
(004D
16
)
Key input interrupt control register
? 0 0 0
(20)
(004A
16
)
Bus collision detection interrupt
control register
0 0 0
?
(8)
(0010
16
)
Address match interrupt register 0
(0011
16
)
(0012
16
)
0
00
16
00
16
0 0 0
(10)
(14)
(0044
16
)
INT3 interrupt control register
0 0 ? 0 0 0
(15)
(0045
16
)
Timer B5 interrupt control register
? 0 0 0
(16)
(0046
16
)
Timer B4 interrupt control register
? 0 0 0
(17)
(0047
16
)
Timer B3 interrupt control register
? 0 0 0
(18)
(0048
16
)
SI/O4 interrupt control register
0 0 ? 0 0 0
(19)
(0049
16
)
SI/O3 interrupt control register
0 0 ? 0 0 0
(24)
A-D conversion interrupt control register
(25)
(26)
UART2 transmit interrupt control register
UART2 receive interrupt control register
(004E
16
)
? 0 0 0
(004F
16
)
(0050
16
)
? 0 0 0
? 0 0 0
0
0
0
(27)
(28)
(29)
(30)
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
(31)
(32)
(33)
(34)
(35)
(36)
(37)
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
(38)
Timer B2 interrupt control register
(39)
INT0 interrupt control register
(40)
INT1 interrupt control register
(41)
INT2 interrupt control register
(45)
Three-phase output buffer register 0
(46)
Three-phase output buffer register 1
Three-phase PWM control register 0
(43)Three-phase PWM control register 1
(44)
(42)
Timer B3,4,5 count start flag
(47)
Timer B3 mode register
(48)
Timer B4 mode register
(49)
Timer B5 mode register
(50)
Interrupt cause select register
00
16
UART2 transmit/receive control register 1
UART2 transmit/receive control register 0
(0378
16
)
(037D
16
)
(037C
16
)
00
16
0 0 0
0 0 0 0 1
0 1 0
0 0 0 0 0
(57)
UART2 transmit/receive mode register
(55)
(56)
(52)
SI/O4 control register
(54) UART2 special mode register
(0051
16
)
(0052
16
)
(0053
16
)
(0054
16
)
(0055
16
)
(0056
16
)
(0057
16
)
(0058
16
)
(0059
16
)
(005A
16
)
(005B
16
)
(005C
16
)
(005D
16
)
(005E
16
)
(005F
16
)
(034A
16
)
(034B
16
)
(0348
16
)
(0349
16
)
(0340
16
)
(035B
16
)
(035C
16
)
(035D
16
)
(035F
16
)
(0366
16
)
(0377
16
)
(0362
16
)
SI/O3 control register
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
0 0
? 0 0 0
0 0
? 0 0 0
0 0
00
16
00
16
00
16
00
16
0 0 ?
0 0 0 0
0 0 ?
0 0 0 0
0 0 ?
0 0 0 0
40
16
00
16
40
16
(51)
0 0 0
(53) UART2 special mode register 2
(0376
16
)
00
16
UART2 special mode register 3 (Note 2)
(0375
16
)
?
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
17
(0383
16
)
Trigger select flag
(0384
16
)
Up-down flag
(62)
(61)
(0396
16
)
Timer A0 mode register
(63)
(0397
16
)
Timer A1 mode register
(64)
(0398
16
)
Timer A2 mode register
(67)
(039B
16
)
Timer B0 mode register
(68)
(039C
16
)
Timer B1 mode register
(69)
(039D
16
)
Timer B2 mode register
(70)
(65)
(0399
16
)
Timer A3 mode register
(66)
(039A
16
)
Timer A4 mode register
(0382
16
)
One-shot start flag
(60)
00
16
00
16
0
00
16
00
16
00
16
00
16
00
16
0 ?
0 0 0 0
0 0 ?
0 0 0 0
0 0 ?
0 0 0 0
(03AC
16
)
UART1 transmit/receive control register 0
(75)
(03AD
16
)
UART1 transmit/receive control register 1
(76)
(03B0
16
)
UART transmit/receive control register 2
(77)
0
(03A0
16
)
UART0 transmit/receive mode register
(71)
(03A4
16
)
UART0 transmit/receive control register 0
(72)
(03A5
16
)
UART0 transmit/receive control register 1
(73)
00
16
0 0 0
1 0 0 0
0 0 0
0 0 1 0
0
0
(03A8
16
)
UART1 transmit/receive mode register
(74)
00
16
0 0 0
1 0 0 0
0 0 0
0 0 1 0
0
0
0
0 0 0 0
0
(03D7
16
)
A-D control register 1
00
16
0
0
0
0
0 0 0
Count start flag
(0380
16
)
00
16
0
(0381
16
)
Clock prescaler reset flag
(58)
(59)
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values
must therefore be set.
Note1: When the V
CC
level is applied to the CNV
SS
pin, it is 02
16
at a reset.
Note2: This register is only exist in flash memory version.
(03E2
16
)
Port P0 direction register
(84)
(03E3
16
)
Port P1 direction register
(85)
(03E6
16
)
Port P2 direction register
(86)
(03E7
16
)
Port P3 direction register
(87)
(03EA
16
)
Port P4 direction register
(88)
(03EB
16
)
Port P5 direction register
(89)
(03EE
16
)
Port P6 direction register
(90)
(03EF
16
)
Port P7 direction register
(91)
(03F2
16
)
Port P8 direction register
(92)
(03F3
16
)
Port P9 direction register
(93)
(03F6
16
)
Port P10 direction register
(94)
(03FC
16
)
Pull-up control register 0
(95)
(03FD
16
)
Pull-up control register 1(Note1)
(96)
(03FE
16
)
Pull-up control register 2
(97)
Port control register
(98)
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
0 0
0
0
0
0 0
(03DC
16
)
D-A control register
(83)
00
16
Frame base register (FB)
(101)
Address registers (A0/A1)
(100)
Interrupt table register (INTB)
(102)
User stack pointer (USP)
(103)
Interrupt stack pointer (ISP)
(104)
Static base register (SB)
(105)
Flag register (FLG)
(106)
0000
16
0000
16
00000
16
0000
16
0000
16
0000
16
0000
16
Data registers (R0/R1/R2/R3)
(99)
0000
16
(03FF
16
)
(03B6
16
)
Flash memory control register 1 (Note2)
(78)
0
(107)
(03B7
16
)
Flash memory control register 0 (Note2)
(03BA
16
)
DMA1 cause select register
00
16
(03D4
16
)
A-D control register 2
(80)
(03D6
16
)
A-D control register 0
(81)
(82)
0
0 0 0
0 ? ? ?
0
0 0 0 0
(03B8
16
)
DMA0 cause select register
(79)
00
16
0
0 0 0 1
0
? ? ? ?
? ? ?
(108)
Figure 1.5.4. Device's internal status after a reset is cleared
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
18
Figure 1.6.1. Location of peripheral unit control registers (1)
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
0040
16
0041
16
0042
16
0043
16
0044
16
0045
16
0046
16
0047
16
0048
16
0049
16
004A
16
004B
16
004C
16
004D
16
004E
16
004F
16
0050
16
0051
16
0052
16
0053
16
0054
16
0055
16
0056
16
0057
16
0058
16
0059
16
005A
16
005B
16
005C
16
005D
16
005E
16
005F
16
0060
16
0061
16
0062
16
0063
16
0064
16
0065
16
032A
16
032B
16
032C
16
032D
16
032E
16
032F
16
0330
16
0331
16
0332
16
0333
16
0334
16
0335
16
0336
16
0337
16
0338
16
0339
16
033A
16
033B
16
033C
16
033D
16
033E
16
033F
16
DMA0 control register (DM0CON)
DMA0 source pointer (SAR0)
DMA0 transfer counter (TCR0)
DMA1 control register (DM1CON)
DMA1 source pointer (SAR1)
DMA1 transfer counter (TCR1)
DMA1 destination pointer (DAR1)
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
Processor mode register 0 (PM0)
Address match interrupt register 0 (RMAD0)
Address match interrupt register 1 (RMAD1)
Chip select control register (CSR)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
Address match interrupt enable register (AIER)
Protect register (PRCR)
Processor mode register 1(PM1)
DMA0 destination pointer (DAR0)
Timer A1 interrupt control register (TA1IC)
UART0 transmit interrupt control register (S0TIC)
Timer A0 interrupt control register (TA0IC)
Timer A2 interrupt control register (TA2IC)
UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control register (S1TIC)
UART1 receive interrupt control register (S1RIC)
DMA1 interrupt control register (DM1IC)
DMA0 interrupt control register (DM0IC)
Key input interrupt control register (KUPIC)
A-D conversion interrupt control register (ADIC)
Bus collision detection interrupt control register (BCNIC)
UART2 transmit interrupt control register (S2TIC)
UART2 receive interrupt control register (S2RIC)
INT1 interrupt control register (INT1IC)
Timer B0 interrupt control register (TB0IC)
Timer B2 interrupt control register (TB2IC)
Timer A3 interrupt control register (TA3IC)
INT2 interrupt control register (INT2IC)
INT0 interrupt control register (INT0IC)
Timer B1 interrupt control register (TB1IC)
Timer A4 interrupt control register (TA4IC)
INT3 interrupt control register (INT3IC)
Timer B5 interrupt control register (TB5IC)
Timer B4 interrupt control register (TB4IC)
Timer B3 interrupt control register (TB3IC)
SI/O4 interrupt control register (S4IC)
INT5 interrupt control register (INT5IC)
SI/O3 interrupt control register (S3IC)
INT4 interrupt control register (INT4IC)
Note 1: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
19
Figure 1.6.2. Location of peripheral unit control registers (2)
0380
16
0381
16
0382
16
0383
16
0384
16
0385
16
0386
16
0387
16
0388
16
0389
16
038A
16
038B
16
038C
16
038D
16
038E
16
038F
16
0390
16
0391
16
0392
16
0393
16
0394
16
0395
16
0396
16
0397
16
0398
16
0399
16
039A
16
039B
16
039C
16
039D
16
039E
16
039F
16
03A0
16
03A1
16
03A2
16
03A3
16
03A4
16
03A5
16
03A6
16
03A7
16
03A8
16
03A9
16
03AA
16
03AB
16
03AC
16
03AD
16
03AE
16
03AF
16
03B0
16
03B1
16
03B2
16
03B3
16
03B4
16
03B5
16
03B6
16
03B7
16
03B8
16
03B9
16
03BA
16
03BB
16
03BC
16
03BD
16
03BE
16
03BF
16
0340
16
0341
16
0342
16
0343
16
0344
16
0345
16
0346
16
0347
16
0348
16
0349
16
034A
16
034B
16
034C
16
034D
16
034E
16
034F
16
0350
16
0351
16
0352
16
0353
16
0354
16
0355
16
0356
16
0357
16
0358
16
0359
16
035A
16
035B
16
035C
16
035D
16
035E
16
035F
16
0360
16
0361
16
0362
16
0363
16
0364
16
0365
16
0366
16
0367
16
0368
16
0369
16
036A
16
036B
16
036C
16
036D
16
036E
16
036F
16
0370
16
0371
16
0372
16
0373
16
0374
16
0375
16
0376
16
0377
16
0378
16
0379
16
037A
16
037B
16
037C
16
037D
16
037E
16
037F
16
Timer A1-1 register (TA11)
Timer A2-1 register (TA21)
Dead time timer(DTT)
Timer B2 interrupt occurrence frequency set counter(ICTB2)
Three-phase PWM control register 0(INVC0)
Three-phase PWM control register 1(INVC1)
Three-phase output buffer register 0(IDB0)
Three-phase output buffer register 1(IDB1)
Timer B3 register (TB3)
Timer B4 register (TB4)
Timer B5 register (TB5)
Timer B3, 4, 5 count start flag (TBSR)
Timer B3 mode register (TB3MR)
Timer B4 mode register (TB4MR)
Timer B5 mode register (TB5MR)
Interrupt cause select register (IFSR)
Timer A0 (TA0)
Timer A1 (TA1)
Timer A2 (TA2)
Timer B0 (TB0)
Timer B1 (TB1)
Timer B2 (TB2)
Count start flag (TABSR)
One-shot start flag (ONSF)
Timer A0 mode register (TA0MR)
Timer A1 mode register (TA1MR)
Timer A2 mode register (TA2MR)
Timer B0 mode register (TB0MR)
Timer B1 mode register (TB1MR)
Timer B2 mode register (TB2MR)
Up-down flag (UDF)
Timer A3 (TA3)
Timer A4 (TA4)
Timer A3 mode register (TA3MR)
Timer A4 mode register (TA4MR)
Trigger select register (TRGSR)
Clock prescaler reset flag (CPSRF)
UART0 transmit/receive mode register (U0MR)
UART0 transmit buffer register (U0TB)
UART0 receive buffer register (U0RB)
UART1 transmit/receive mode register (U1MR)
UART1 transmit buffer register (U1TB)
UART1 receive buffer register (U1RB)
UART0 bit rate generator (U0BRG)
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
UART1 bit rate generator (U1BRG)
UART1 transmit/receive control register 0 (U1C0)
UART1 transmit/receive control register 1 (U1C1)
DMA1 request cause select register (DM1SL)
DMA0 request cause select register (DM0SL)
CRC data register (CRCD)
CRC input register (CRCIN)
SI/O3
transmit/receive register
(S3TRR)
SI/O4
transmit/receive register
(S4TRR)
SI/O3 control register (S3C)
SI/O3
bit rate generator
(S3BRG)
SI/O4
bit rate generator
(S4BRG)
SI/O4 control register (S4C)
UART2 special mode register (U2SMR)
UART2 receive buffer register (U2RB)
UART2 transmit buffer register (U2TB)
UART2 transmit/receive control register 0 (U2C0)
UART2 transmit/receive mode register (U2MR)
UART2 transmit/receive control register 1 (U2C1)
UART2 bit rate generator (U2BRG)
UART transmit/receive control register 2 (UCON)
Timer A4-1 register (TA41)
UART2 special mode register 2(U2SMR2)
Note 1: This register is only exist in flash memory version.
Note 2: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for
read or write.
Flash memory control register 0 (FMR0) (Note1)
Flash memory control register 1 (FMR1) (Note1)
UART2 special mode register 3(U2SMR3)
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
20
Figure 1.6.3. Location of peripheral unit control registers (3)
03C0
16
03C1
16
03C2
16
03C3
16
03C4
16
03C5
16
03C6
16
03C7
16
03C8
16
03C9
16
03CA
16
03CB
16
03CC
16
03CD
16
03CE
16
03CF
16
03D0
16
03D1
16
03D2
16
03D3
16
03D4
16
03D5
16
03D6
16
03D7
16
03D8
16
03D9
16
03DA
16
03DB
16
03DC
16
03DD
16
03DE
16
03DF
16
03E0
16
03E1
16
03E2
16
03E3
16
03E4
16
03E5
16
03E6
16
03E7
16
03E8
16
03E9
16
03EA
16
03EB
16
03EC
16
03ED
16
03EE
16
03EF
16
03F0
16
03F1
16
03F2
16
03F3
16
03F4
16
03F5
16
03F6
16
03F7
16
03F8
16
03F9
16
03FA
16
03FB
16
03FC
16
03FD
16
03FE
16
03FF
16
A-D register 7 (AD7)
A-D register 0 (AD0)
A-D register 1 (AD1)
A-D register 2 (AD2)
A-D register 3 (AD3)
A-D register 4 (AD4)
A-D register 5 (AD5)
A-D register 6 (AD6)
Port P0 (P0)
Port P0 direction register (PD0)
Port P1 (P1)
Port P1 direction register (PD1)
Port P2 (P2)
Port P2 direction register (PD2)
Port P3 (P3)
Port P3 direction register (PD3)
Port P4 (P4)
Port P4 direction register (PD4)
Port P5 (P5)
Port P5 direction register (PD5)
Port P6 (P6)
Port P6 direction register (PD6)
Port P7 (P7)
Port P7 direction register (PD7)
Port P8 (P8)
Port P8 direction register (PD8)
Port P9 (P9)
Port P9 direction register (PD9)
Port P10 (P10)
Port P10 direction register (PD10)
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
Pull-up control register 2 (PUR2)
A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)
D-A register 0 (DA0)
D-A register 1 (DA1)
D-A control register (DACON)
A-D control register 2 (ADCON2)
Port control register (PCR)
Note : Locations in the SFR area where nothing is allocated are reserved
areas. Do not access these areas for read or write.
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Reset
21
Software Reset
Writing "1" to bit 3 of the processor mode register 0 (address 0004
16
) applies a (software) reset to the
microcomputer. A software reset has the same effect as a hardware reset. The contents of internal RAM
are preserved.
Software Reset
Processor Mode
(1) Types of Processor Mode
One of three processor modes can be selected: single-chip mode, memory expansion mode, and micro-
processor mode. The functions of some pins, the memory map, and the access space differ according to
the selected processor mode.
Single-chip mode
In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be
accessed. However, after the reset has been released and the operation of shifting from the micropro-
cessor mode has started ("H" applied to the CNV
SS
pin), the internal ROM area cannot be accessed
even if the CPU shifts to the single-chip mode.
Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal peripheral
functions.
Memory expansion mode
In memory expansion mode, external memory can be accessed in addition to the internal memory
space (SFR, internal RAM, and internal ROM). However, after the reset has been released and the
operation of shifting from the microprocessor mode has started ("H" applied to the CNV
SS
pin), the
internal ROM area cannot be accessed even if the CPU shifts to the memory expansion mode.
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See "Bus
Settings" for details.)
Microprocessor mode
In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. The
internal ROM area cannot be accessed.
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus width and register settings. (See "Bus
Settings" for details.)
(2) Setting Processor Modes
The processor mode is set using the CNV
SS
pin and the processor mode bits (bits 1 and 0 at address
0004
16
). Do not set the processor mode bits to "10
2
".
Regardless of the level of the CNV
SS
pin, changing the processor mode bits selects the mode. Therefore,
never change the processor mode bits when changing the contents of other bits. Do not change the
processor mode bits simultaneously with other bits when changing the processor mode bits "01
2
" or
"11
2
". Change the processor mode bits after changing the other bits. Also do not attempt to shift to or from
the microprocessor mode within the program stored in the internal ROM area.
Applying V
SS
to CNV
SS
pin
The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode
is selected by writing "01
2
" to the processor mode bits.
Applying V
CC
to CNV
SS
pin
The microcomputer starts to operate in microprocessor mode after being reset.
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode
22
Figure 1.7.1. Processor mode register 0 and 1
Processor mode register 0 (Note 1)
Symbol
Address
When reset
PM0
0004
16
00
16
(Note 2)
Bit name
Function
Bit symbol
W
R
b7
b6
b5
b4
b3
b2
b1
b0
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Do not set
1 1: Microprocessor mode
b1 b0
PM03
PM01
PM00
Processor mode bit
PM02
R/W mode select bit
0 : RD,BHE,WR
1 : RD,WRH,WRL
Software reset bit
The device is reset when this bit is set
to "1". The value of this bit is "0" when
read.
PM04
0 0 : Multiplexed bus is not used
0 1 : Allocated to CS2 space
1 0 : Allocated to CS1 space
1 1 : Allocated to entire space (Note4)
b5 b4
Multiplexed bus space
select bit
PM05
PM06
PM07
Port P4
0
to P4
3
function
select bit (Note 3)
0 : Address output
1 : Port function
(Address is not output)
BCLK output disable bit
0 : BCLK is output
1 : BCLK is not output
(Pin is left floating)
Note 1: Set bit 1 of the protect register (address 000A
16
) to "1" when writing new
values to this register.
Note 2: If the V
CC
voltage is applied to the CNV
SS
, the value of this register when
reset is 03
16
. (PM00 and PM01 both are set to "1".)
Note 3: Valid in microprocessor and memory expansion modes.
Note 4: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-
bit width.The processor operates using the separate bus after reset is revoked, so the entire
space multiplexed bus cannot be chosen in microprocessor mode.
P3
1
to P3
7
become a port if the entire space multiplexed bus is chosen, so only 256 bytes can
be used in each chip select.
Processor mode register 1 (Note 1)
Symbol
Address
When reset
PM1
0005
16
00000XX0
2
Bit name
Function
Bit symbol
W
R
b7
b6
b5
b4
b3
b2
b1
b0
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns
out to be
indeterminate.
Reserved bit
Must always be set to "0"
0
Note 1: Set bit 1 of the protect register (address 000A
16
) to "1" when writing new values to this register.
Note 2: When the reset is revoked, this bit is set to "0". To expand the internal area, set this bit to "1"
in user program. And the top of user program must be allocated to D0000
16
or subsequent
address.
PM17
Wait bit
0 : No wait state
1 : Wait state inserted
Reserved bit
Must always be set to "0"
0
Internal reserved area
expansion bit (Note 2)
PM13
0: The internal RAM area is 15 kbytes
or less and the internal ROM area is
192 kbytes or less
1: Expands the internal RAM area
and internal ROM area to over 15
kbytes and to over 192 kbytes
respectively. (Note 2)
0 0
Reserved bit
Must always be set to "0"
Reserved bit
Must always be set to "0"
Figure 1.7.1 shows the processor mode register 0 and 1.
Figure 1.7.2 shows the memory maps applicable for each of the modes.
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode
23
Single-chip mode
SFR area
Internal
RAM area
Inhibited
Internal
ROM area
Microprocessor mode
SFR area
Internal
RAM area
External
area
Internally
reserved area
00000
16
00400
16
XXXXX
16
YYYYY
16
FFFFF
16
D0000
16
External area :
Accessing this area allows the user to
access a device connected externally
to the microcomputer.
04000
16
Memory expansion mode
SFR area
Internal
RAM area
External
area
Internal
ROM area
Internally
reserved area
Internally
reserved area
Note : These memory maps show an instance in which PM13 is set to 0; but in the case of products in which the
internal RAM and the internal ROM are expanded to over 15 Kbytes and 192 Kbytes, respectively, they show
an instance in which PM13 is set to 1.
Address YYYYY
16
3K bytes
00FFF
16
053FF
16
017FF
16
013FF
16
Address XXXXX
16
ROM size
02BFF
16
5K bytes
4K bytes
10K bytes
20K bytes
RAM size
32K bytes
C0000
16
E8000
16
F0000
16
E0000
16
96K bytes
64K bytes
128K bytes
256K bytes
F8000
16
Figure 1.7.2. Memory maps in each processor mode (without memory area expansion, normal mode)
Internal Reserved Area Expansion Bit (PM13)
This bit expands the internal RAM area and the internal ROM area, and changes the chip select area. In
M30624MGA/FGA, for example, to set this bit to "1" expands the internal RAM area and the internal ROM
area to 20 Kbytes and 256 Kbytes respectively. Refer to Figure 1.7.3 for the chip select area. When the
reset is revoked, this bit is set to "0". To expand the internal area, set this bit to "1" in user program. And
the top of user program must be allocated to D0000
16
or subsequent address.
In the case of the product in which the internal ROM is 192 Kbytes or less and the internal RAM is 15
Kbytes or less, set this bit to "0" when this product is used in the memory expansion mode or the micro-
processor mode. When the product is used in the single chip mode, the internal area is not expanded and
any action is not affected, even if this bit is set to "1".
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode
24
SFR area
(1K bytes)
Internal RAM area
(15K bytes)
External area
00000
16
00400
16
FFFFF
16
D0000
16
08000
16
Internal RAM area
(15K bytes)
External area
Internal ROM area
(192K bytes)
CS3
(16K bytes)
CS2
(128K bytes)
CS1
(32K bytes)
CS0
Memory expansion mode
: 640K bytes
Microprocessor mode
: 832K bytes
28000
16
30000
16
04000
16
Internal reserved area expansion bit="0"
SFR area
(1K bytes)
After reset
SFR area
(1K bytes)
00000
16
00400
16
FFFFF
16
C0000
16
08000
16
Internal RAM area
(20K bytes)
Internal ROM area
(256K bytes)
CS3
(8K bytes)
CS2
(128K bytes)
CS1
(32K bytes)
CS0
Memory expansion mode
: 576K bytes
Microprocessor mode
: 832K bytes
28000
16
30000
16
05400
16
Internal reserved area expansion bit="1" (Note)
SFR area
(1K bytes)
After reset, and set the
Internal reserved area expansion bit to "1"
06000
16
BFFFF
16
CFFFF
16
Note: When the reset is revoked, this bit is set to "0". Therefore, the top
of the user program must be allocated to D0000
16
or subsequent address.
Memory expansion
mode
Microprocessor
mode
Memory expansion
mode
Microprocessor
mode
Internal RAM area
(20K bytes)
Internal reserved area
External area
External area
Internal reserved area
Figure 1.7.3. Memory location and chip select area in each processor mode
Figure 1.7.3 shows the memory maps and the chip selection areas effected by PM13 (the internal re-
served area expansion bit) in each processor mode for the product having an internal RAM of more than
15K bytes and a ROM of more than 192K bytes.
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Settings
25
Bus Settings
The BYTE pin and bits 4 to 6 of the processor mode register 0 (address 0004
16
) are used to change the bus settings.
Table 1.8.1 shows the factors used to change the bus settings.
Bus setting
Switching factor
Switching external address bus width
Bit 6 of processor mode register 0
Switching external data bus width
BYTE pin
Switching between separate and multiplex bus
Bits 4 and 5 of processor mode register 0
(1) Selecting external address bus width
The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K
bytes address space) or 20 bits (1M bytes address space). When bit 6 of the processor mode register 0
is set to "1", the external address bus width is set to 16 bits, and P2 and P3 become part of the address
bus. P4
0
to P4
3
can be used as programmable I/O ports. When bit 6 of processor mode register 0 is set
to "0", the external address bus width is set to 20 bits, and P2, P3, and P4
0
to P4
3
become part of the
address bus.
(2) Selecting external data bus width
The external data bus width can be set to 8 or 16 bits. (Note, however, that only the separate bus can be
set.) When the BYTE pin is "L", the bus width is set to 16 bits; when "H", it is set to 8 bits. (The internal bus
width is permanently set to 16 bits.) While operating, fix the BYTE pin either to "H" or to "L".
(3) Selecting separate/multiplex bus
The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0.
Separate bus
In this mode, the data and address are input and output separately. The data bus can be set using the
BYTE pin to be 8 or 16 bits. When the BYTE pin is "H", the data bus is set to 8 bits and P0 functions as
the data bus and P1 as a programmable I/O port. When the BYTE pin is "L", the data bus is set to 16
bits and P0 and P1 are both used for the data bus.
When the separate bus is used for access, a software wait can be selected.
Multiplex bus
In this mode, data and address I/O are time multiplexed. With the BYTE pin = "H", the 8 bits from D
0
to
D
7
are multiplexed with A
0
to A
7
.
With the BYTE pin = "L", the 8 bits from D
0
to D
7
are multiplexed with A
1
to A
8
. D
8
to D
15
are not
multiplexed. In this case, the external devices connected to the multiplexed bus are mapped to the
microcomputer's even addresses (every 2nd address). To access these external devices, access the
even addresses as bytes.
The ALE signal latches the address. It is output from P5
6
.
Before using the multiplex bus for access, be sure to insert a software wait.
If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width.
The processor operates using the separate bus after reset is revoked, so the entire space multiplexed
bus cannot be chosen in microprocessor mode.
P3
1
to P3
7
become a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used
in each chip select.
Table 1.8.1. Factors for switching bus settings
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M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Settings
26
P5
6
I/O port
ALE
ALE
ALE
ALE
ALE
P5
7
I/O port
RDY
RDY
RDY
RDY
RDY
P0
0
to P0
7
I/O port
Data bus
Data bus
Data bus
Data bus
I/O port
Either CS1 or CS2 is for
multiplexed bus and others
are for separate bus
(separate bus)
multiplexed
bus for the
entire
space
Single-chip
mode
Memory expansion mode/microprocessor modes
Memory
expansion mode
Data bus width
BYTE pin level
Port P4
0
to P4
3
function select bit = 0
"01", "10"
"00"
"11" (Note 1)
8 bit
"H"
8 bits
"H"
16 bits
"L"
8 bits
"H"
16 bits
"L"
Note 1: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width.
The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be
chosen in microprocessor mode.
P3
1
to P3
7
become a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used
in each chip select.
Note 2: Address bus when in separate bus mode.
Processor mode
Multiplexed bus
space select bit
CS (chip select) or programmable I/O port
(For details, refer to "Bus control")
Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK
(For details, refer to "Bus control")
Port P4
0
to P4
3
function select bit = 1
P1
0
to P1
7
I/O port
I/O port
Data bus
I/O port
Data bus
I/O port
P2
1
to P2
7
I/O port
Address bus
Address bus
Address bus
Address bus
Address bus
/data bus
(Note 2)
/data bus
(Note 2)
/data bus
P2
0
I/O port
Address bus
Address bus
Address bus
Address bus
Address bus
/data bus
(Note 2)
/data bus
P3
0
I/O port
Address bus
Address bus
Address bus
Address bus
A
8
/D
7
/data bus
(Note 2)
P3
1
to P3
7
I/O port
Address bus
Address bus
Address bus
Address bus
I/O port
P4
0
to P4
3
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
P4
0
to P4
3
I/O port
Address bus
Address bus
Address bus
Address bus
I/O port
P4
4
to P4
7
I/O port
P5
0
to P5
3
I/O port
P5
4
I/O port
HLDA
HLDA
HLDA
HLDA
HLDA
P5
5
I/O port
HOLD
HOLD
HOLD
HOLD
HOLD
Table 1.8.2. Pin functions for each processor mode
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M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
27
Bus Control
The following explains the signals required for accessing external devices and software waits. The signals
required for accessing the external devices are valid when the processor mode is set to memory expansion
mode and microprocessor mode. The software waits are valid in all processor modes.
(1) Address bus/data bus
The address bus consists of the 20 pins A
0
to A
19
for accessing the 1M bytes of address space.
The data bus consists of the pins for data I/O. When the BYTE pin is "H", the 8 ports D
0
to D
7
function
as the data bus. When BYTE is "L", the 16 ports D
0
to D
15
function as the data bus.
When a change is made from single-chip mode to memory expansion mode, the value of the address
bus is undefined until external memory is accessed.
(2) Chip select signal
The chip select signal is output using the same pins as P4
4
to P4
7
. Bits 0 to 3 of the chip select control
register (address 0008
16
) set each pin to function as a port or to output the chip select signal. The chip
select control register is valid in memory expansion mode and microprocessor mode. In single-chip
mode, P4
4
to P4
7
function as programmable I/O ports regardless of the value in the chip select control
register.
_______
In microprocessor mode, only CS0 outputs the chip select signal after the reset state has been can-
_______
_______
celled. CS1 to CS3 function as input ports. Figure 1.9.1 shows the chip select control register.
The chip select signal can be used to split the external area into as many as four blocks. Tables 1.9.1
and 1.9.2 show the external memory areas specified using the chip select signal.
Processor mode
Memory expansion mode
Chip select signal
CS0
CS1
CS2
CS3
30000
16
to
CFFFF
16
(640K bytes)
Microprocessor mode
28000
16
to
2FFFF
16
(32K bytes)
08000
16
to
27FFF
16
(128K bytes)
04000
16
to
07FFF
16
(16K bytes)
30000
16
to
FFFFF
16
(832K bytes)
Table 1.9.1. External areas specified by the chip select signals
(A product having an internal RAM equal to or less than 15K bytes and a ROM equal to or less than 192K bytes)(Note)
Note :Be sure to set bit 3 (PM13) of processor mode register 1 to "0".
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
28
W
Function
Bit symbol
Bit name
Chip select control register
Symbol
Address When
reset
CSR
0008
16
01
16
R
b7
b6
b5
b4
b3
b2
b1
b0
CS1
CS0
CS3
CS2
CS0 output enable bit
CS1 output enable bit
CS2 output enable bit
CS3 output enable bit
CS1W
CS0W
CS3W
CS2W
CS0 wait bit
CS1 wait bit
CS2 wait bit
CS3 wait bit
0 : Chip select output disabled
(Normal port pin)
1 : Chip select output enabled
0 : Wait state inserted
1 : No wait state
Figure 1.9.1. Chip select control register
Processor mode
Memory expansion mode
Chip select signal
CS0
CS1
CS2
CS3
30000
16
to CFFFF
16
(640K bytes)
28000
16
to
2FFFF
16
(32K bytes)
08000
16
to
27FFF
16
(128K bytes)
When PM13=0
Microprocessor mode
30000
16
to BFFFF
16
(576K bytes)
03000
16
to FFFFF
16
(816K bytes)
When PM13=0
When PM13=1
When PM13=1
04000
16
to
07FFF
16
(16K bytes)
06000
16
to
07FFF
16
(8K bytes)
Table 1.9.2. External areas specified by the chip select signals
(A product having an internal RAM of more than 15K bytes and a ROM of more than 192K bytes)
The timing of the chip select signal changing to "L"(active) is synchronized with the address bus. But the
timing of the chip select signal changing to "H" depends on the area which will be accessed in the next
cycle. Figure 1.9.2 shows the output example of the address bus and chip select signal.
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
29
Figure 1.9.2. Output Examples about Address Bus and Chip Select Signal (Separated Bus without
Wait)
Example 1) After access the external area, both the address signal and
the chip select signal change concurrently in the next cycle.
In this example, after access to the external area(i), an access to the area
indicated by the other chip select signal(j) will occur in the next cycle. In
this case, both the address bus and the chip select signal change between
the two cycles.
Note : These examples show the address bus and chip select signal within the successive two cycles.
According to the combination of these examples, the chip select can be elongated to over 2cycles.
BCLK
Read/Write
signal
Data bus
Address bus
Chip select
(CS i)
Access to the
External Area( i )
Chip select
(CS j)
Access to the Other
External Area( j )
Address
Data
Example 2) After access the external area, only the chip select signal
changes in the next cycle (the address bus does not change).
In this example, an access to the internal ROM or the internal RAM in the
next cycle will occur, after access to the external area. In this case, the
chip select signal changes between the two cycles, but the address does
not change.
Example 4) After access the external area, either the address signal and
the chip select signal do not change in the next cycle.
In this example, any access to any area does not occur in the next cycle
(either instruction prefetch does not occur). In this case,either the address
bus and chip select signal do not change between the two cycles.
Example 3) After access the external area, only the address bus changes
in the next cycle (the chip select signal does not change).
In this example, after access to the external area(i), an access to the area
indicated by the same chip select signal(i) will occur in the next cycle. In
this case, the address bus changes between the two cycles, but the chip
select signal does not change.
BCLK
Access to the
External Area
Internal ROM/RAM
Access
Read/Write
signal
Data bus
Address bus
Chip select
Address
Data
BCLK
Access to the
External Area
No Access
Read/Write
signal
Data bus
Address bus
Chip select
Address
Data
BCLK
Access to the
External Area( i )
Access to the Same
External Area( i )
Read/Write
signal
Data bus
Address bus
Chip select
(CS i)
Address
Data
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
30
_____
______
________
Table 1.9.4. Operation of RD, WR, and BHE signals
Status of external data bus
RD
BHE
WR
H
L
L
L
H
L
H
L
H
L
H
H
Write 1 byte of data to odd address
Read 1 byte of data from odd address
Write 1 byte of data to even address
Read 1 byte of data from even address
Data bus width
A0
H
H
L
L
H
L
L
L
L
H
L
L
H
L
H / L
L
H
H / L
8-bit
(BYTE = "H")
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
Read 1 byte of data
16-bit
(BYTE = "L")
Not used
Not used
Status of external data bus
Read data
Write 1 byte of data to even address
Write 1 byte of data to odd address
Write data to both even and odd addresses
WRH
WRL
RD
Data bus width
16-bit
(BYTE = "L")
H
H
H
H
L
H
L
H
H
L
L
L
_____
________
_________
Table 1.9.3. Operation of RD, WRL, and WRH signals
(3) Read/write signals
With a 16-bit data bus (BYTE pin ="L"), bit 2 of the processor mode register 0 (address 0004
16
) select the
_____ ________
______
_____
________
_________
combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus (BYTE
_____
______
_______
pin = "H"), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0
(address 0004
16
) to "0".) Tables 1.9.3 and 1.9.4 show the operation of these signals.
_____
______
________
After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected.
_____ _________
_________
When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the
processor mode register 0 (address 0004
16
) has been set (Note).
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A
16
) to "1".
(4) ALE signal
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the
ALE signal falls.
When BYTE pin = "H"
When BYTE pin = "L"
ALE
Address
Data (Note 1)
Address (Note 2)
D
0
/A
0
to D
7
/A
7
A
8
to A
19
ALE
Address
Data (Note 1)
Address
D
0
/A
1
to D
7
/A
8
A
9
to A
19
Address
A
0
Note 1: Floating when reading.
Note 2: When multiplexed bus for the entire space is selected, these are I/O ports.
Figure 1.9.3. ALE signal and address/data bus
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
31
_____
________
Figure 1.9.4. Example of RD signal extended by RDY signal
BCLK
RD
CS
i
(i=0 to 3)
RDY
tsu(RDY - BCLK)
BCLK
RD
CS
i
(i=0 to 3)
RDY
tsu(RDY - BCLK)
In an instance of separate bus
In an instance of multiplexed bus
Accept timing of RDY signal
: Wait using RDY signal
: Wait using software
Accept timing of RDY signal
________
Note: The RDY signal cannot be received immediately prior to a software wait.
Table 1.9.5. Microcomputer status in wait state (Note)
Item
Status
Oscillation
On
___
_____
R/W signal, address bus, data bus, CS
________
Maintain status when RDY signal received
__________
ALE signal, HLDA, programmable I/O ports
Internal peripheral circuits
On
________
(5) The RDY signal
________
RDY is a signal that facilitates access to an external device that requires long access time. As shown in
________
Figure 1.9.4, if an "L" is being input to the RDY at the BCLK falling edge, the bus turns to the wait state. If
________
an "H" is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state. Table 1.9.5
shows the state of the microcomputer with the bus in the wait state, and Figure 1.9.4 shows an example
____
________
in which the RD signal is prolonged by the RDY signal.
________
The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of the
________
chip select control register (address 0008
16
) are set to "0". The RDY signal is invalid when setting "1" to
________
all bits 4 to 7 of the chip select control register (address 0008
16
), but the RDY pin should be treated as
properly as in non-using.
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32
Table 1.9.6. Microcomputer status in hold state
Item
Status
Oscillation
ON
___
_____
_______
R/W signal, address bus, data bus, CS, BHE
Floating
Programmable I/O ports
P0, P1, P2, P3, P4, P5
Floating
P6, P7, P8, P9, P10
Maintains status when hold signal is received
__________
HLDA
Output "L"
Internal peripheral circuits
ON (but watchdog timer stops)
ALE signal
Undefined
__________
HOLD > DMAC > CPU
(6) Hold signal
The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting "L" to
__________
the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status
__________
__________
is maintained and "L" is output from the HLDA pin as long as "L" is input to the HOLD pin. Table 1.9.6
shows the microcomputer status in the hold state.
__________
Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence.
Figure 1.9.5. Bus-using priorities
(7) External bus status when the internal area is accessed
Table 1.9.7 shows the external bus status when the internal area is accessed.
Table 1.9.7. External bus status when the internal area is accessed
Item
SFR accessed
Internal ROM/RAM accessed
Address bus
Address output
Maintain status before accessed
address of external area
Data bus
When read
Floating
Floating
When write
Output data
Undefined
RD, WR, WRL, WRH
RD, WR, WRL, WRH output
Output "H"
BHE
BHE output
Maintain status before accessed
status of external area
CS
Output "H"
Output "H"
ALE
Output "L"
Output "L"
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(9) Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
0005
16
) (Note) and bits 4 to 7 of the chip select control register (address 0008
16
).
A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the
wait bit of the processor mode register 1. When set to "0", each bus cycle is executed in one BCLK cycle.
When set to "1", each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been
reset, this bit defaults to "0". When set to "1", a wait is applied to all memory areas (two or three BCLK
cycles), regardless of the contents of bits 4 to 7 of the chip select control register. Set this bit after referring
to the recommended operating conditions (main clock input oscillation frequency) of the electric character-
________
istics. However, when the user is using the RDY signal, the relevant bit in the chip select control register's
bits 4 to 7 must be set to "0".
When the wait bit of the processor mode register 1 is "0", software waits can be set independently for
each of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register
_______
_______
correspond to chip selects CS0 to CS3. When one of these bits is set to "1", the bus cycle is executed in
one BCLK cycle. When set to "0", the bus cycle is executed in two or three BCLK cycles. These bits
default to "0" after the microcomputer has been reset.
The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also,
insert a software wait if using the multiplex bus to access the external memory area.
Table 1.9.8 shows the software wait and bus cycles. Figure 1.9.6 shows example of bus timing when
using software waits.
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A
16
) to "1".
Area
Bus status
Wait bit
Bits 4 to 7 of chip select
control register
Bus cycle
Invalid
1
2 BCLK cycles
External
memory
area
Separate bus
0
1
1 BCLK cycle
Separate bus
0
0
2 BCLK cycles
Separate bus
1
0 (Note)
2 BCLK cycles
Multiplex bus
0
0
3 BCLK cycles
Multiplex bus
1
3 BCLK cycles
0 (Note)
SFR
Internal
ROM/RAM
0
Invalid
1 BCLK cycle
Invalid
Invalid
2 BCLK cycles
Note: When using the RDY signal, always set to "0".
Table 1.9.8. Software waits and bus cycles
(8) BCLK output
The user can choose the BCLK output by use of bit 7 of processor mode register 0 (0004
16
) (Note).
When set to "1", the output floating.
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A
16
) to "1".
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Figure 1.9.6. Typical bus timings using software wait
Output
Input
Address
Address
< Separate bus (with wait) >
BCLK
Read signal
Write signal
Data bus
BCLK
Read signal
Address bus/
Data bus
Chip select (Note 2)
Address
Address
Data output
Address
Address
Input
ALE
< Multiplexed bus >
Write signal
BCLK
Read signal
Write signal
Address bus (Note 2)
Address
Address
Bus cycle (Note 1)
< Separate bus (no wait) >
Output
Data bus
Input
Note 1: These example timing charts indicate bus cycle length.
After this bus cycle sometimes come read and write cycles in succession.
Note 2: The address bus and chip select may be extended depending on the CPU status
such as that of the instruction queue buffer.
Bus cycle (Note 1)
Bus cycle (Note 1)
Bus cycle (Note 1)
Bus cycle (Note 1)
Bus cycle (Note 1)
Address bus (Note 2)
Address bus (Note 2)
Chip select (Note 2)
Chip select (Note 2)
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Figure 1.10.2. Examples of sub-clock
Table 1.10.1. Main clock and sub-clock generating circuits
Clock Generating Circuit
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the
CPU and internal peripheral units.
Example of oscillator circuit
Figure 1.10.1 shows some examples of the main clock circuit, one using an oscillator connected to the
circuit, and the other one using an externally derived clock for input. Figure 1.10.2 shows some examples
of sub-clock circuits, one using an oscillator connected to the circuit, and the other one using an externally
derived clock for input. Circuit constants in Figures 1.10.1 and 1.10.2 vary with each oscillator used. Use
the values recommended by the manufacturer of your oscillator.
Figure 1.10.1. Examples of main clock
Main clock generating circuit
Sub-clock generating circuit
Use of clock
CPU's operating clock source
CPU's operating clock source
Internal peripheral units'
Timer A/B's count clock
operating clock source
source
Usable oscillator
Ceramic or crystal oscillator
Crystal oscillator
Pins to connect oscillator
X
IN
, X
OUT
X
CIN
, X
COUT
Oscillation stop/restart function
Available
Available
Oscillator status immediately after reset
Oscillating
Stopped
Other
Externally derived clock can be input
Microcomputer
(Built-in feedback resistor)
X
IN
X
OUT
Externally derived clock
Open
Vcc
Vss
Microcomputer
(Built-in feedback resistor)
X
IN
X
OUT
R
d
C
IN
C
OUT
(Note)
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between X
IN
and X
OUT
following the instruction.
Microcomputer
(Built-in feedback resistor)
X
CIN
X
COUT
Externally derived clock
Open
Vcc
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between X
CIN
and X
COUT
following the instruction.
Microcomputer
(Built-in feedback resistor)
X
CIN
X
COUT
(Note)
C
CIN
C
COUT
R
Cd
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Clock Control
Figure 1.10.3 shows the block diagram of the clock generating circuit.
Sub clock
CM04
f
C32
CM0i : Bit i at address 0006
16
CM1i : Bit i at address 0007
16
WDCi : Bit i at address 000F
16
X
CIN
CM10 "1"
Write signal
1/32
X
COUT
Q
S
R
WAIT instruction
X
OUT
Main clock
CM05
f
C
CM02
f
1
Q
S
R
NMI
Interrupt request
level judgment
output
RESET
Software reset
f
C
CM07=0
CM07=1
f
AD
Divider
a
d
1/2
1/2
1/2
1/2
CM06=0
CM17,CM16=00
CM06=0
CM17,CM16=01
CM06=0
CM17,CM16=10
CM06=1
CM06=0
CM17,CM16=11
d
a
Details of divider
X
IN
f
8
f
32
c
b
b
1/2
c
f
32
SIO2
f
8
SIO2
f
1
SIO2
BCLK
Figure 1.10.3. Clock generating circuit
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The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 0006
16
). Stopping the
clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock
oscillation circuit can be reduced using the X
IN
-X
OUT
drive capacity select bit (bit 5 at address 0007
16
).
Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit
changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is re-
tained.
(2) Sub-clock
The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset.
After oscillation is started using the port X
C
select bit (bit 4 at address 0006
16
), the sub-clock can be
selected as the BCLK by using the system clock select bit (bit 7 at address 0006
16
). However, be sure
that the sub-clock oscillation has fully stabilized before switching.
After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock
oscillation circuit can be reduced using the X
CIN
-X
COUT
drive capacity select bit (bit 3 at address 0006
16
).
Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit
changes to "1" when shifting to stop mode and at a reset.
When the X
CIN
/X
COUT
is used, set ports P8
6
and P8
7
as the input ports without pull-up.
(3) BCLK
The BCLK is the clock that drives the CPU, and is f
C
or the clock is derived by dividing the main clock by
1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK signal can
be output from BCLK pin by the BCLK output disable bit (bit 7 at address 0004
16
) in the memory expan-
sion and the microprocessor modes.
The main clock division select bit 0(bit 6 at address 0006
16
) changes to "1" when shifting from high-
speed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation
mode to stop mode, the value before stop mode is retained.
(4) Peripheral function clock(f
1
, f
8
, f
32
, f
1SIO2
, f
8SIO2
,f
32SIO2
,f
AD
)
The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function
clock stop bit (bit 2 at 0006
16
) to "1" and then executing a WAIT instruction.
(5) f
C32
This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts.
(6) f
C
This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer.
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Figure 1.10.4 shows the system clock control registers 0 and 1.
Figure 1.10.4. Clock control registers 0 and 1
System clock control register 0 (Note 1)
Symbol
Address
When reset
CM0
0006
16
48
16
Bit name
Function
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
0 0 : I/O port P5
7
0 1 : f
C
output
1 0 : f
8
output
1 1 : f
32
output
b1 b0
CM07
CM05
CM04
CM03
CM01
CM02
CM00
CM06
Clock output function
select bit
(Valid only in single-chip
mode)
WAIT peripheral function
clock stop bit
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8)
X
CIN
-X
COUT
drive capacity
select bit (Note 2)
0 : LOW
1 : HIGH
Port X
C
select bit
0 : I/O port
1 : X
CIN
-X
COUT
generation (Note 9)
Main clock (X
IN
-X
OUT
)
stop bit (Note 3, 4, 5)
0 : On
1 : Off
Main clock division select
bit 0 (Note 7)
0 : CM16 and CM17 valid
1 : Division by 8 mode
System clock select bit
(Note 6)
0 : X
IN
, X
OUT
1 : X
CIN
, X
COUT
Note 1: Set bit 0 of the protect register (address 000A
16
) to "1" before writing to this register.
Note 2: Changes to "1" when shiffing to stop mode and at a reset.
Note 3: When entering low power dissipation mode, main clock stops by using this bit. To stop the main clock, when the
sub clock oscillation is stable, set system clock select bit (CM07) to "1" before setting this bit to "1".
Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 5: If this bit is set to "1", X
OUT
turns "H". The built-in feedback resistor remains being connected, so X
IN
turns
pulled up to X
OUT
("H") via the feedback resistor.
Note 6: Set port X
C
select bit (CM04) to "1" and stabilize the sub-clock oscillating before setting this bit from "0" to "1".
Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to "0" and stabilize the
main clock oscillating before setting this bit from "1" to "0".
Note 7: This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 8: f
C32
is not included.
Do not set to
"1"
when using low-speed or low power dissipation mode.
Note 9: When the X
CIN
/X
COUT
is used, set ports P8
6
and P8
7
as the input ports without pull-up.
System clock control register 1 (Note 1)
Symbol
Address
When reset
CM1
0007
16
20
16
Bit name
Function
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
CM10
All clock stop control bit
(Note4)
0 : Clock on
1 : All clocks off (stop mode)
Note 1: Set bit 0 of the protect register (address 000A
16
) to
"1" before writing to this register.
Note 2: This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 0006
16
) is
"0". If
"1", division mode is
fixed at 8.
Note 4: If this bit is set to "1", X
OUT
turns "H", and the built-in feedback resistor is cut off. X
CIN
and X
COUT
turn high-
impedance state.
CM15
X
IN
-X
OUT
drive capacity
select bit (Note 2)
0 : LOW
1 : HIGH
W
R
W
R
CM16
CM17
Reserved bit
Always set to
"0"
Reserved bit
Always set to
"0"
Main clock division
select bit 1 (Note 3)
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
b7 b6
0
0
Reserved bit
Always set to
"0"
Reserved bit
Always set to
"0"
0
0
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Clock Generating Circuit
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Pin
Memory expansion mode
Single-chip mode
Microprocessor mode
_______
_______
Address bus, data bus, CS0 to CS3,
Retains status before stop mode
________
BHE
_____
______
________
_________
RD, WR, WRL, WRH
"H"
__________
HLDA, BCLK
"H"
ALE
"H"
Port
Retains status before stop mode Retains status before stop mode
CLK
OUT
When fc selected
Valid only in single-chip mode
"H"
When f
8
, f
32
selected
Valid only in single-chip mode
Retains status before stop mode
Table 1.10.2. Port status during stop mode
Clock Output
In single-chip mode, the clock output function select bits (bits 0 and 1 at address 0006
16
) enable f
8
, f
32
, or
fc to be output from the P5
7
/CLK
OUT
pin. When the WAIT peripheral function clock stop bit (bit 2 at address
0006
16
) is set to "1", the output of f
8
and f
32
stops when a WAIT instruction is executed.
Stop Mode
Writing "1" to the all-clock stop control bit (bit 0 at address 0007
16
) stops all oscillation and the microcom-
puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that V
CC
re-
mains above 2V.
Because the oscillation , BCLK, f
1
to f
32
, f
1SIO2
to f
32SIO2
, f
C
, f
C32
, and f
AD
stops in stop mode, peripheral
functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B
operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2), SI/O3,4
functions provided an external clock is selected. Table 1.10.2 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode,
that interrupt must first have been enabled, and the priority level of the interrupt which is not used to cancel
must have been changed to 0. If returning by an interrupt, that interrupt routine is executed. If only a
_______
hardware reset or an NMI interrupt is used to cancel stop mode, change the priority level of all interrupt to
0, then shift to stop mode.
When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division
select bit 0 (bit 6 at address 0006
16
) is set to "1". When shifting from low-speed/low power dissipation mode
to stop mode, the value before stop mode is retained.
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Table 1.10.3. Port status during wait mode
Pin
Memory expansion mode
Single-chip mode
Microprocessor mode
_______
_______
Address bus, data bus, CS0 to CS3,
Retains status before wait mode
________
BHE
_____
______
________
_________
RD, WR, WRL, WRH
"H"
__________
HLDA,BCLK
"H"
ALE
"H"
Port
Retains status before wait mode
Retains status before wait mode
CLK
OUT
When f
C
selected
Valid only in single-chip mode
Does not stop
When f
8
, f
32
selected Valid only in single-chip mode
Does not stop when the WAIT
peripheral function clock stop
bit is "0".
When the WAIT peripheral
function clock stop bit is "1",
the status immediately prior
to entering wait mode is main-
tained.
Wait Mode
When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this
mode, oscillation continues but the BCLK and watchdog timer stop. Writing "1" to the WAIT peripheral
function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal
peripheral functions, allowing power dissipation to be reduced. However, peripheral function clock f
C32
does not stop so that the peripherals using f
C32
do not contribute to the power saving. When the MCU
running in low-speed or low power dissipation mode, do not enter WAIT mode with this bit set to "1". Table
1.10.3 shows the status of the ports in wait mode.
Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, that
interrupt must first have been enabled, and the priority level of the interrupt which is not used to cancel must
have been changed to 0. If returning by an interrupt, the clock in which the WAIT instruction executed is set
to BCLK by the microcomputer, and the action is resumed from the interrupt routine. If only a hardware
_______
reset or an NMI interrupt is used to cancel wait mode, change the priority level of all interrupt to 0,then shift
to wait mode.
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Status Transition of BCLK
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0
1
0
0
0
Invalid
Division by 2 mode
1
0
0
0
0
Invalid
Division by 4 mode
Invalid
Invalid
0
1
0
Invalid
Division by 8 mode
1
1
0
0
0
Invalid
Division by 16 mode
0
0
0
0
0
Invalid
No-division mode
Invalid
Invalid
1
Invalid
0
1
Low-speed mode
Invalid
Invalid
1
Invalid
1
1
Low power dissipation mode
Status Transition of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table 1.10.4 shows the operating modes corresponding to the settings of system clock control
registers 0 and 1.
When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address
0006
16
) changes to "1" when shifting from high-speed/medium-speed to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
The following shows the operational modes of BCLK.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this
mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4
mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption
mode, make sure the sub-clock is oscillating stably.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is divided by 1 to obtain the BCLK.
(6) Low-speed mode
f
C
is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before
transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub-
clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately
after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
f
C
is the BCLK and the main clock is stopped.
Note : Before the count source for BCLK can be changed from X
IN
to X
CIN
or vice versa, the clock to which
the count source is going to be switched must be oscillating stably. Allow a wait time in software for
the oscillation to stabilize before switching over the clock.
CM17
CM16
CM07
CM06
CM05
CM04
Operating mode of BCLK
Table 1.10.4. Operating modes dictated by settings of system clock control registers 0 and 1
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Power control
The following is a description of the three available power control modes:
Modes
Power control is available in three modes.
(a) Normal operation mode
High-speed mode
Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the BCLK.
Each peripheral function operates according to its assigned clock.
Medium-speed mode
Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the
BCLK. The CPU operates with the BCLK. Each peripheral function operates according to its as-
signed clock.
Low-speed mode
f
C
becomes the BCLK. The CPU operates according to the f
C
clock. The f
C
clock is supplied by the
subclock. Each peripheral function operates according to its assigned clock.
Low power dissipation mode
The main clock operating in low-speed mode is stopped. The CPU operates according to the f
C
clock. The f
C
clock is supplied by the subclock. The only peripheral functions that operate are those
with the subclock selected as the count source.
(b) Wait mode
The CPU operation is stopped. The oscillators do not stop.
(c) Stop mode
All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three
modes listed here, is the most effective in decreasing power consumption.
Figure 1.10.5 is the state transition diagram of the above modes.
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Figure 1.10.5. State transition diagram of Power control mode
Transition of stop mode, wait mode
Transition of normal mode
Reset
Medium-speed mode
(divided-by-8 mode)
Interrupt
CM10 = "1"
All oscillators stopped
CPU operation stopped
Medium-speed mode
(divided-by-8 mode)
BCLK : f(X
IN
)/8
CM07 = "0" CM06 = "1"
Low-speed mode
High-speed mode
Main clock is oscillating
Sub clock is stopped
Main clock is oscillating
Sub clock is stopped
Main clock is stopped
Sub clock is oscillating
Main clock is oscillating
Sub clock is oscillating
Low power dissipation mode
High-speed/medium-
speed mode
Low-speed/low power
dissipation mode
Normal mode
Stop mode
Stop mode
Stop mode
All oscillators stopped
All oscillators stopped
Wait mode
Wait mode
Wait mode
CPU operation stopped
CPU operation stopped
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
CM10 = "1"
Interrupt
Interrupt
CM10 = "1"
BCLK : f(X
IN
)/2
CM07 = "0" CM06 = "0"
CM17 = "0" CM16 = "1"
Medium-speed mode
(divided-by-2 mode)
BCLK : f(X
IN
)/16
CM07 = "0" CM06 = "0"
CM17 = "1" CM16 = "1"
Medium-speed mode
(divided-by-16 mode)
BCLK : f(X
IN
)/4
CM07 = "0" CM06 = "0"
CM17 = "1" CM16 = "0"
Medium-speed mode
(divided-by-4 mode)
BCLK : f(X
IN
)
CM07 = "0" CM06 = "0"
CM17 = "0" CM16 = "0"
BCLK : f(X
IN
)/8
Medium-speed mode
(divided-by-8 mode)
CM07 = "0"
CM06 = "1"
High-speed mode
BCLK : f(X
IN
)/2
CM07 = "0" CM06 = "0"
CM17 = "0" CM16 = "1"
Medium-speed mode
(divided-by-2 mode)
BCLK : f(X
IN
)/16
CM07 = "0" CM06 = "0"
CM17 = "1" CM16 = "1"
Medium-speed mode
(divided-by-16 mode)
BCLK : f(X
IN
)/4
CM07 = "0" CM06 = "0"
CM17 = "1" CM16 = "0"
Medium-speed mode
(divided-by-4 mode)
BCLK : f(X
IN
)
CM07 = "0" CM06 = "0"
CM17 = "0" CM16 = "0"
BCLK : f(X
CIN
)
CM07 = "1"
BCLK : f(X
CIN
)
CM07 = "1"
Main clock is oscillating
Sub clock is oscillating
CM07 = "0"
(Note 1, 3)
CM07 = "0" (Note 1)
CM06 = "1"
CM04 = "0"
CM07 = "1"
(Note 2)
CM07 = "0" (Note 1)
CM06 = "0" (Note 3)
CM04 = "1"
CM07 = "1" (Note 2)
CM05 = "1"
CM05 = "0"
CM05 = "1"
CM04 = "0"
CM04 = "1"
CM06 = "0"
(Notes 1,3)
CM06 = "1"
CM04 = "0"
CM04 = "1"
(Notes 1, 3)
Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 3: Change CM06 after changing CM17 and CM16.
Note 4: Transit in accordance with arrow.
(Refer to the following for the transition of normal mode.)
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Protection
44
Protection
The protection function is provided so that the values in important registers cannot be changed in the event
that the program runs out of control. Figure 1.10.6 shows the protect register. The values in the processor
mode register 0 (address 0004
16
), processor mode register 1 (address 0005
16
), system clock control reg-
ister 0 (address 0006
16
), system clock control register 1 (address 0007
16
), port P9 direction register (ad-
dress 03F3
16
) , SI/O3 control register (address 0362
16
) and SI/O4 control register (address 0366
16
) can
only be changed when the respective bit in the protect register is set to "1". Therefore, important outputs
can be allocated to port P9.
If, after "1" (write-enabled) has been written to the port P9 direction register and SI/Oi control register
(i=3,4) write-enable bit (bit 2 at address 000A
16
), a value is written to any address, the bit automatically
reverts to "0" (write-inhibited). However, the system clock control registers 0 and 1 write-enable bit (bit 0 at
000A
16
) and processor mode register 0 and 1 write-enable bit (bit 1 at 000A
16
) do not automatically return
to "0" after a value has been written to an address. The program must therefore be written to return these
bits to "0".
Protect register
Symbol
Address
When reset
PRCR
000A
16
XXXXX000
2
Bit name
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
0 : Write-inhibited
1 : Write-enabled
PRC1
PRC0
PRC2
Enables writing to processor mode
registers 0 and 1 (addresses 0004
16
and 0005
16
)
Function
0 : Write-inhibited
1 : Write-enabled
Enables writing to system clock
control registers 0 and 1 (addresses
0006
16
and 0007
16
)
Enables writing to port P9 direction
register (address 03F3
16
) and SI/Oi
control register (i=3,4) (addresses
0362
16
and 0366
16
) (Note
)
0 : Write-inhibited
1 : Write-enabled
W
R
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.
Note: Writing a value to an address after "1" is written to this bit returns the bit
to "0" . Other bits do not automatically return to "0" and they must therefore
be reset by the program.
Figure 1.10.6. Protect register
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Interrupt
45
Maskable interrupt :
An interrupt which can be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority can be changed by priority level.
Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
Figure 1.11.1. Classification of interrupts
Interrupt
Software
Hardware
Special
Peripheral I/O (Note)
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Reset
_______
NMI
________
DBC
Watchdog timer
Single step
Address matched
Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
Overview of Interrupt
Type of Interrupts
Figure 1.11.1 lists the types of interrupts.
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Interrupt
46
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
Undefined instruction interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
Overflow interrupt
An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to
"1". The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
BRK interrupt
A BRK interrupt occurs when executing the BRK instruction.
INT interrupt
An INT interrupt occurs when specifying one of software interrupt numbers 0 through 63 and execut-
ing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O inter-
rupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/
O interrupt does.
The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is
involved.
So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack
pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to "0" and
select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from
the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt re-
quest. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a
shift.
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Interrupt
47
Hardware Interrupts
Hardware interrupts are classified into two types -- special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
Reset
____________
Reset occurs if an "L" is input to the RESET pin.
_______
NMI interrupt
_______
_______
An NMI interrupt occurs if an "L" is input to the NMI pin.
________
DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
Watchdog timer interrupt
Generated by the watchdog timer.
Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug
flag (D flag) set to "1", a single-step interrupt occurs after one instruction is executed.
Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated by
the address match interrupt register is executed with the address match interrupt enable bit set to "1".
If an address other than the first address of the instruction in the address match interrupt register is set,
no address match interrupt occurs.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func-
tions are dependent on classes of products, so the interrupt factors too are dependent on classes of
products. The interrupt vector table is the same as the one for software interrupt numbers 0 through
31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
Bus collision detection interrupt
This is an interrupt that the serial I/O bus collision detection generates.
DMA0 interrupt, DMA1 interrupt
These are interrupts that DMA generates.
Key-input interrupt
___
A key-input interrupt occurs if an "L" is input to the KI pin.
A-D conversion interrupt
This is an interrupt that the A-D converter generates.
UART0, UART1, UART2/NACK, SI/O3 and SI/O4 transmission interrupt
These are interrupts that the serial I/O transmission generates.
UART0, UART1, UART2/ACK, SI/O3 and SI/O4 reception interrupt
These are interrupts that the serial I/O reception generates.
Timer A0 interrupt through timer A4 interrupt
These are interrupts that timer A generates
Timer B0 interrupt through timer B5 interrupt
These are interrupts that timer B generates.
________
________
INT0 interrupt through INT5 interrupt
______
______
An INT interrupt occurs if either a rising edge or a falling edge or a both edge is input to the INT pin.
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Interrupt
48
Interrupt source
Vector table addresses
Remarks
Address (L) to address (H)
Undefined instruction
FFFDC
16
to FFFDF
16
Interrupt on UND instruction
Overflow
FFFE0
16
to FFFE3
16
Interrupt on INTO instruction
BRK instruction
FFFE4
16
to FFFE7
16
If the vector contains FF
16
, program execution starts from
the address shown by the vector in the variable vector table
Address match
FFFE8
16
to FFFEB
16
There is an address-matching interrupt enable bit
Single step (Note)
FFFEC
16
to FFFEF
16
Do not use
Watchdog timer
FFFF0
16
to FFFF3
16
________
DBC (Note)
FFFF4
16
to FFFF7
16
Do not use
_______
NMI
FFFF8
16
to FFFFB
16
_______
External interrupt by input to NMI pin
Reset
FFFFC
16
to FFFFF
16
Note: Interrupts used for debugging purposes only.
Figure 1.11.2. Format for specifying interrupt vector addresses
Mid address
Low address
0 0 0 0
High address
0 0 0 0
0 0 0 0
Vector address + 0
Vector address + 1
Vector address + 2
Vector address + 3
LSB
MSB
Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector
table. Set the first address of the interrupt routine in each vector table. Figure 1.11.2 shows the format for
specifying the address.
Two types of interrupt vector tables are available -- fixed vector table in which addresses are fixed and
variable vector table in which addresses can be varied by the setting.
Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFDC
16
to FFFFF
16
. One vector table comprises four bytes. Set the first address of
interrupt routine in each vector table. Table 1.11.1 shows the interrupts assigned to the fixed vector
tables and addresses of vector tables.
Table 1.11.1. Interrupts assigned to the fixed vector tables and addresses of vector tables
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Interrupt
49
Table 1.11.2. Interrupts assigned to the variable vector tables and addresses of vector tables
Software interrupt number
Interrupt source
Vector table address
Address (L) to address (H)
Remarks
Cannot be masked I flag
+0 to +3 (Note 1)
BRK instruction
Software interrupt number 0
+44 to +47 (Note 1)
Software interrupt number 11
+48 to +51 (Note 1)
Software interrupt number 12
+52 to +55 (Note 1)
Software interrupt number 13
+56 to +59 (Note 1)
Software interrupt number 14
+68 to +71 (Note 1)
Software interrupt number 17
+72 to +75 (Note 1)
Software interrupt number 18
+76 to +79 (Note 1)
Software interrupt number 19
+80 to +83 (Note 1)
Software interrupt number 20
+84 to +87 (Note 1)
Software interrupt number 21
+88 to +91 (Note 1)
Software interrupt number 22
+92 to +95 (Note 1)
Software interrupt number 23
+96 to +99 (Note 1)
Software interrupt number 24
+100 to +103 (Note 1)
Software interrupt number 25
+104 to +107 (Note 1)
Software interrupt number 26
+108 to +111 (Note 1)
Software interrupt number 27
+112 to +115 (Note 1)
Software interrupt number 28
+116 to +119 (Note 1)
Software interrupt number 29
+120 to +123 (Note 1)
Software interrupt number 30
+124 to +127 (Note 1)
Software interrupt number 31
+128 to +131 (Note 1)
Software interrupt number 32
+252 to +255 (Note 1)
Software interrupt number 63
to
Note 1: Address relative to address in interrupt table register (INTB).
Note 2: It is selected by interrupt request cause bit (bit 6, 7 in address 035F
16
).
Note 3: When IIC mode is selected, NACK and ACK interrupts are selected.
Cannot be masked I flag
+40 to +43 (Note 1)
Software interrupt number 10
+60 to +63 (Note 1)
Software interrupt number 15
+64 to +67 (Note 1)
Software interrupt number 16
+20 to +23 (Note 1)
Software interrupt number 5
+24 to +27 (Note 1)
Software interrupt number 6
+28 to +31 (Note 1)
Software interrupt number 7
+32 to +35 (Note 1)
Software interrupt number 8
+16 to +19 (Note 1)
INT3
Software interrupt number 4
+36 to +39 (Note 1)
SI/O3/INT4
Software interrupt number 9
SI/O4/INT5
Timer B3
Timer B4
Timer B5
(Note 2)
(Note 2)
to
DMA0
DMA1
Key input interrupt
A-D
UART0 transmit
UART0 receive
UART1 transmit
UART1 receive
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
INT0
INT1
INT2
Software interrupt
Bus collision detection
UART2 transmit/NACK (Note 3)
UART2 receive/ACK (Note 3)
Variable vector tables
The addresses in the variable vector table can be modified, according to the user's settings. Indicate
the first address using the interrupt table register (INTB). The 256-byte area subsequent to the ad-
dress the INTB indicates becomes the area for the variable vector tables. One vector table comprises
four bytes. Set the first address of the interrupt routine in each vector table. Table 1.11.2 shows the
interrupts assigned to the variable vector tables and addresses of vector tables.
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Interrupt
50
Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selec-
tion bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is
indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit
are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the
IPL are located in the flag register (FLG).
Figure 1.11.3 shows the memory map of the interrupt control registers.
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Interrupt
51
Figure 1.11.3. Interrupt control registers
Symbol
Address
When reset
INTiIC(i=3)
0044
16
XX00X000
2
SiIC/INTjIC (i=4, 3)
0048
16
, 0049
16
XX00X000
2
(j=5, 4)
0048
16
, 0049
16
XX00X000
2
INTiIC(i=0 to 2)
005D
16
to 005F
16
XX00X000
2
Bit name
Function
Bit symbol
W
R
b7
b6
b5
b4
b3
b2
b1
b0
ILVL0
IR
POL
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns
out to be indeterminate.
Interrupt priority level
select bit
Interrupt request bit
Polarity select bit
Reserved bit
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
Always set to "0"
ILVL1
ILVL2
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that does not generate the
interrupt request for that register. For details, see the precautions for interrupts.
(Note 1)
Interrupt control register (Note2)
b7
b6
b5
b4
b3
b2
b1
b0
Bit name
Function
Bit symbol
W
R
Symbol
Address
When reset
TBiIC(i=3 to 5)
0045
16
to 0047
16
XXXXX000
2
BCNIC
004A
16
XXXXX000
2
DMiIC(i=0, 1)
004B
16
, 004C
16
XXXXX000
2
KUPIC
004D
16
XXXXX000
2
ADIC
004E
16
XXXXX000
2
SiTIC(i=0 to 2)
0051
16
, 0053
16
, 004F
16
XXXXX000
2
SiRIC(i=0 to 2)
0052
16
, 0054
16
, 0050
16
XXXXX000
2
TAiIC(i=0 to 4)
0055
16
to 0059
16
XXXXX000
2
TBiIC(i=0 to 2)
005A
16
to 005C
16
XXXXX000
2
ILVL0
IR
Interrupt priority level
select bit
Interrupt request bit
0 : Interrupt not requested
1 : Interrupt requested
ILVL1
ILVL2
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns
out to be indeterminate.
(Note 1)
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that does not generate the
interrupt request for that register. For details, see the precautions for interrupts.
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0
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Interrupt
52
Interrupt Enable Flag (I flag)
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this
flag to "1" enables all maskable interrupts; setting it to "0" disables all maskable interrupts. This flag is set
to "0" after reset.
Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The
interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
Table 1.11.4. Interrupt levels enabled according
to the contents of the IPL
Table 1.11.3. Settings of interrupt priority
levels
Interrupt priority
level select bit
Interrupt priority
level
Priority
order
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Low
High
b2 b1 b0
Enabled interrupt priority levels
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
IPL
2
IPL
1
IPL
0
IPL
Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits
of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared
with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.
Therefore, setting the interrupt priority level to "0" disables the interrupt.
Table 1.11.3 shows the settings of interrupt priority levels and Table 1.11.4 shows the interrupt levels
enabled, according to the contents of the IPL.
The following are conditions under which an interrupt is accepted:
interrupt enable flag (I flag) = "1"
interrupt request bit = "1"
interrupt priority level > IPL
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are
independent, and they are not affected by one another.
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Interrupt
53
Example 1:
INT_SWITCH1:
FCLR
I
; Disable interrupts.
AND.B
#00h, 0055h
; Clear TA0IC int. priority level and int. request bit.
NOP
; Four NOP instructions are required when using HOLD function.
NOP
FSET
I
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
I
; Disable interrupts.
AND.B
#00h, 0055h
; Clear TA0IC int. priority level and int. request bit.
MOV.W MEM, R0
; Dummy read.
FSET
I
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG
; Push Flag register onto stack
FCLR
I
; Disable interrupts.
AND.B
#00h, 0055h
; Clear TA0IC int. priority level and int. request bit.
POPC
FLG
; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
Rewrite the interrupt control register
To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-
ated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
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Interrupt
54
Interrupt Sequence
An interrupt sequence -- what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed -- is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading ad-
dress 00000
16
. After this, the corresponding interrupt request bit becomes "0".
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence
in the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to
"0" (the U flag, however does not change if the INT instruction, in software interrupt numbers 32
through 63, is executed)
(4) Saves the content of the temporary register (Note) within the CPU in the stack area.
(5) Saves the content of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.
Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the
occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the
time required for executing the interrupt sequence (b). Figure 1.11.4 shows the interrupt response time.
Instruction
Interrupt sequence
Instruction in
interrupt routine
Time
Interrupt response time
(a)
(b)
Interrupt request acknowledged
Interrupt request generated
(a) Time from interrupt request is generated to when the instruction then under execution is completed.
(b) Time in which the instruction sequence is executed.
Figure 1.11.4. Interrupt response time
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Interrupt
55
Interrupt sources without priority levels
7
Value set in the IPL
_______
Watchdog timer, NMI
Other
Not changed
0
Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown
in Table 1.11.6 is set in the IPL.
Table 1.11.6. Relationship between interrupts without interrupt priority levels and IPL
Stack pointer (SP) value
Interrupt vector address
16-Bit bus, without wait
8-Bit bus, without wait
Even
Even
Odd (Note 2)
Odd (Note 2)
Even
Odd
Even
Odd
18 cycles (Note 1)
19 cycles (Note 1)
19 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
Table 1.11.5. Time required for executing the interrupt sequence
Reset
Indeterminate
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Indeterminate
SP-2
contents
SP-4
contents
vec
contents
vec+2
contents
Interrupt
information
Address
0000
Indeterminate
SP-2
SP-4
vec
vec+2
PC
BCLK
Address bus
Data bus
W
R
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction (without wait).
Time (b) is as shown in Table 1.11.5.
________
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match
interrupt or of a single-step interrupt.
Note 2: Locate an interrupt vector address in an even address, if possible.
Figure 1.11.5. Time required for executing the interrupt sequence
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56
Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter
(PC) are saved in the stack area.
First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8
lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the
program counter. Figure 1.11.6 shows the state of the stack as it was before the acceptance of the
interrupt request, and the state the stack after the acceptance of the interrupt request.
Save other necessary registers at the beginning of the interrupt routine using software. Using the
PUSHM instruction alone can save all the registers except the stack pointer (SP).
Address
Content of previous stack
Stack area
[SP]
Stack pointer
value before
interrupt occurs
m
m 1
m 2
m 3
m 4
Stack status before interrupt request
is acknowledged
Stack status after interrupt request
is acknowledged
Content of previous stack
m + 1
MSB
LSB
m
m 1
m 2
m 3
m 4
Address
Flag register (FLG
L
)
Content of previous stack
Stack area
Flag register
(FLG
H
)
Program
counter (PC
H
)
[SP]
New stack
pointer value
Content of previous stack
m + 1
MSB
LSB
Program counter (PC
L
)
Program counter (PC
M
)
Figure 1.11.6. State of stack before and after acceptance of interrupt request
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Interrupt
57
Figure 1.11.7. Operation of saving registers
(2) Stack pointer (SP) contains odd number
[SP]
(Odd)
[SP] 1 (Even)
[SP] 2(Odd)
[SP] 3 (Even)
[SP] 4(Odd)
[SP] 5 (Even)
Address
Sequence in which order
registers are saved
(2)
(1)
Finished saving registers
in four operations.
(3)
(4)
(1) Stack pointer (SP) contains even number
[SP]
(Even)
[SP] 1(Odd)
[SP] 2 (Even)
[SP] 3(Odd)
[SP] 4 (Even)
[SP] 5 (Odd)
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Address
Program counter (PC
M
)
Stack area
Flag register (FLG
L
)
Program counter (PC
L
)
Sequence in which order
registers are saved
(2) Saved simultaneously,
all 16 bits
(1) Saved simultaneously,
all 16 bits
Finished saving registers
in two operations.
Program counter (PC
M
)
Stack area
Flag register (FLG
L
)
Program counter (PC
L
)
Saved simultaneously,
all 8 bits
Flag register
(FLG
H
)
Program
counter (PC
H
)
Flag register
(FLG
H
)
Program
counter (PC
H
)
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
content of the stack pointer (Note) , at the time of acceptance of an interrupt request, is even or odd. If
the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the
program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at
a time. Figure 1.11.7 shows the operation of the saving registers.
Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the stack pointer
indicated by the U flag. Otherwise, it is the interrupt stack pointer (ISP).
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
58
Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking
whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level
select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware
priority is accepted.
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority),
watchdog timer interrupt, etc. are regulated by hardware.
Figure 1.11.8 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register
(FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter
(PC), both of which have been saved in the stack area. Then control returns to the program that was being
executed before the acceptance of the interrupt request, so that the suspended process resumes.
Return the other registers saved by software within the interrupt routine using the POPM or similar instruc-
tion before executing the REIT instruction.
Interrupt resolution circuit
When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest
priority level. Figure 1.11.9 shows the circuit that judges the interrupt priority level.
Figure 1.11.8. Hardware interrupts priorities
_______
________
Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
59
Figure 1.11.9. Maskable interrupts priorities (peripheral I/O interrupts)
Timer B2
Timer B0
Timer A3
Timer A1
Timer B1
Timer A4
Timer A2
UART1 reception
UART0 reception
UART2 reception/ACK
A-D conversion
DMA1
Bus collision detection
Timer A0
UART1 transmission
UART0 transmission
UART2 transmission/NACK
Key input interrupt
DMA0
Processor interrupt priority level (IPL)
Interrupt enable flag (I flag)
INT1
INT2
INT0
Watchdog timer
Reset
DBC
NMI
Interrupt
request
accepted
Level 0 (initial value)
Priority level of each interrupt
High
Low
Priority of peripheral I/O interrupts
(if priority levels are same)
Timer B4
INT3
Timer B3
Timer B5
Serial I/O4/INT5
Serial I/O3/INT4
Address match
Interrupt request level judgment output
to clock generating circuit (Fig.1.10.3)
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
______
INT Interrupt
60
______
INT Interrupt
________
________
INT0 to INT5 are triggered by the edges of external inputs. The edge polarity is selected using the polarity
select bit.
________
Of interrupt control registers, 0048
16
is used both as serial I/O4 and external interrupt INT5 input control
________
register, and 0049
16
is used both as serial I/O3 and as external interrupt INT4 input control register. Use the
interrupt request cause select bits - bits 6 and 7 of the interrupt request cause select register (035F
16
) - to
specify which interrupt request cause to select. After having set an interrupt request cause, be sure to clear
the corresponding interrupt request bit before enabling an interrupt.
Either of the interrupt control registers - 0048
16
, 0049
16
- has the polarity-switching bit. Be sure to set this bit
to "0" to select an serial I/O as the interrupt request cause.
As for external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge
by setting "1" in the INTi interrupt polarity switching bit of the interrupt request cause select register
(035F
16
). To select both edges, set the polarity switching bit of the corresponding interrupt control register
to `falling edge' ("0").
Figure 1.11.10 shows the Interrupt request cause select register.
Figure 1.11.10. Interrupt request cause select register
Interrupt request cause select register
Bit name
Function
Bit symbol
W
R
Symbol
Address
When reset
IFSR
035F
16
00
16
IFSR0
b7
b6
b5
b4
b3
b2
b1
b0
INT0 interrupt polarity
switching bit
0 : SIO3
1 : INT4
0 : SIO4
1 : INT5
0 : One edge
1 : Two edges
0 : One edge
1 : Two edges
0 : One edge
1 : Two edges
0 : One edge
1 : Two edges
0 : One edge
1 : Two edges
INT1 interrupt polarity
switching bit
INT2 interrupt polarity
switching bit
INT3 interrupt polarity
switching bit
INT4 interrupt polarity
switching bit
INT5 interrupt polarity
switching bit
0 : One edge
1 : Two edges
Interrupt request cause
select bit
Interrupt request cause
select bit
IFSR1
IFSR2
IFSR3
IFSR4
IFSR5
IFSR6
IFSR7
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
________
NMI Interrupt
61
Interrupt control circuit
Key input interrupt control register
(address 004D
16
)
Key input interrupt
request
P10
7
/KI
3
P10
6
/KI
2
P10
5
/KI
1
P10
4
/KI
0
Port P10
4
-P10
7
pull-up
select bit
Port P10
7
direction
register
Pull-up
transistor
Port P10
7
direction register
Port P10
6
direction
register
Port P10
5
direction
register
Port P10
4
direction
register
Pull-up
transistor
Pull-up
transistor
Pull-up
transistor
Figure 1.11.11. Block diagram of key input interrupt
______
NMI Interrupt
______
______
______
An NMI interrupt is generated when the input to the P8
5
/NMI pin changes from "H" to "L". The NMI interrupt
is a non-maskable external interrupt. The pin level can be checked in the port P8
5
register (bit 5 at address
03F0
16
).
This pin cannot be used as a normal port input.
Key Input Interrupt
If the direction register of any of P10
4
to P10
7
is set for input and a falling edge is input to that port, a key
input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancel-
ling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P10
4
to
P10
7
as A-D input ports. Figure 1.11.11 shows the block diagram of the key input interrupt. Note that if an
"L" level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as
an interrupt.
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address Match Interrupt
62
Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match
the program counter value. Two address match interrupts can be set, each of which can be enabled and
disabled by an address match interrupt enable bit. Address match interrupts are not affected by the inter-
rupt enable flag (I flag) and processor interrupt priority level (IPL). For an address match interrupt, the value
of the program counter (PC) that is saved to the stack area varies depending on the instruction being
executed. Note that when using the external data bus in width of 8 bits, the address match interrupt cannot
be used for external area.
Figure 1.11.12 shows the address match interrupt-related registers.
Bit name
Bit symbol
Symbol
Address When
reset
AIER
0009
16
XXXXXX00
2
Address match interrupt enable register
Function
W
R
Address match interrupt 0
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
AIER0
Address match interrupt 1
enable bit
AIER1
Symbol
Address
When reset
RMAD0
0012
16
to 0010
16
X00000
16
RMAD1
0016
16
to 0014
16
X00000
16
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to
be indeterminated.
b7
b6
b5
b4
b3
b2
b1
b0
W
R
Address setting register for address match interrupt
Function
Values that can be set
Address match interrupt register i (i = 0, 1)
00000
16
to FFFFF
16
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to
be indeterminated.
0 : Interrupt disabled
1 : Interrupt enabled
b0 b7
b0
b3
(b19)
(b16)
b7
b0
(b15)
(b8)
b7
(b23)
Figure 1.11.12. Address match interrupt-related registers
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions for Interrupts
63
Precautions for Interrupts
(1) Reading address 00000
16
When maskable interrupt is occurred, CPU reads the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 00000
16
will then be set to "0".
Even if the address 00000
16
is read out by software, "0" is set to the enabled highest priority interrupt
source request bit. Therefore interrupt can be canceled and unexpected interrupt can occur.
Do not read address 00000
16
by software.
(2) Setting the stack pointer
The value of the stack pointer immediately after reset is initialized to 0000
16
. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in
_______
the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack
pointer at the beginning of a program. Concerning the first instruction immediately after reset, generat-
_______
ing any interrupts including the NMI interrupt is prohibited.
_______
(3) The NMI interrupt
_______
_______
The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc via a pull-up resistor if
unused. Be sure to work on it.
_______
The NMI pin also serves as P8
5
, which is exclusively input. Reading the contents of the P8 register
allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time
_______
when the NMI interrupt is input.
_______
Do not reset the CPU with the input to the NMI pin being in the "L" state.
_______
Do not attempt to go into stop mode with the input to the NMI pin being in the "L" state. With the input to
_______
the NMI being in the "L" state, the CM10 is fixed to "0", so attempting to go into stop mode is turned
down.
_______
Do not attempt to go into wait mode with the input to the NMI pin being in the "L" state. With the input to
_______
the NMI pin being in the "L" state, the CPU stops but the oscillation does not stop, so no power is saved.
In this instance, the CPU is returned to the normal state by a later interrupt.
_______
Signals input to the NMI pin require an "L" level of 1 clock or more, from the operation clock of the CPU.
(4) External interrupt
________
Either an "L" level or an "H" level of at least 250 ns width is necessary for the signal input to pins INT
0
________
through INT
5
regardless of the CPU operation clock.
________
________
When the polarity of the INT
0
to INT
5
pins is changed, the interrupt request bit is sometimes set to "1".
After changing the polarity, set the interrupt request bit to "0". Figure 1.11.13 shows the procedure for
______
changing the INT interrupt generate factor.
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions for Interrupts
64
______
Figure 1.11.13. Switching condition of INT interrupt request
Set the interrupt priority level to level 0
(Disable INT
i
interrupt)
Set the polarity select bit
Clear the interrupt request bit to "0"
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INTi interrupt request)
Clear the interrupt enable flag to "0"
(Disable interrupt)
Set the interrupt enable flag to "1"
(Enable interrupt)
Note: Execute the setting above individually. Don't execute two or
more settings at once(by one instruction).
Example 1:
INT_SWITCH1:
FCLR
I
; Disable interrupts.
AND.B
#00h, 0055h
; Clear TA0IC int. priority level and int. request bit.
NOP
; Four NOP instructions are required when using HOLD function.
NOP
FSET
I
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
I
; Disable interrupts.
AND.B
#00h, 0055h
; Clear TA0IC int. priority level and int. request bit.
MOV.W MEM, R0
; Dummy read.
FSET
I
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG
; Push Flag register onto stack
FCLR
I
; Disable interrupts.
AND.B
#00h, 0055h
; Clear TA0IC int. priority level and int. request bit.
POPC
FLG
; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
(5) Rewrite the interrupt control register
To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-
ated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
65
Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. Therefore, we recom-
mend using the watchdog timer to improve reliability of a system.The watchdog timer is a 15-bit counter
which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog timer interrupt
is generated when an underflow occurs in the watchdog timer. When X
IN
is selected for the BCLK
,
bit 7 of
the watchdog timer control register (address 000F
16
) selects the prescaler division ratio (by 16 or by 128).
When X
CIN
is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog
timer control register (address 000F
16
). Thus the watchdog timer's period can be calculated as given
below. The watchdog timer's period is, however, subject to an error due to the prescaler.
BCLK
Write to the watchdog timer
start register
(address 000E
16
)
RESET
Watchdog timer
interrupt request
Watchdog timer
Set to
"7FFF
16
"
1/128
1/16
"CM07 = 0"
"WDC7 = 1"
"CM07 = 0"
"WDC7 = 0"
"CM07 = 1"
HOLD
1/2
Prescaler
For example, suppose that BCLK runs at 16 MHz and that 16 has been chosen for the dividing ratio of the
prescaler, then the watchdog timer's period becomes approximately 32.8 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E
16
) and when
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E
16
). In stop mode, wait mode and hold state, the
watchdog timer and prescaler are stopped. Counting is resumed from the held value when the modes or
state are released.
Figure 1.12.1 shows the block diagram of the watchdog timer. Figure 1.12.2 shows the watchdog timer-
related registers.
With X
IN
chosen for BCLK
Watchdog timer period =
prescaler dividing ratio (16 or 128) X watchdog timer count (32768)
BCLK
Figure 1.12.1. Block diagram of watchdog timer
With X
CIN
chosen for BCLK
Watchdog timer period =
prescaler dividing ratio (2) X watchdog timer count (32768)
BCLK
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
66
Watchdog timer control register
Symbol
Address
When reset
WDC
000F
16
000XXXXX
2
Function
Bit symbol
W
R
b7
b6
b5
b4
b3
b2
b1
b0
High-order bit of watchdog timer
WDC7
Bit name
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
Watchdog timer start register
Symbol
Address
When reset
WDTS
000E
16
Indeterminate
W
R
b7
b0
Function
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to "7FFF
16
"
regardless of whatever value is written.
Reserved bit
Reserved bit
Must always be set to "0"
Must always be set to "0"
0
0
Figure 1.12.2. Watchdog timer control and start registers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
67
DMAC
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to
memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a
higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this
account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16-
bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 1.13.1 shows the block diagram
of the DMAC. Table 1.13.1 shows the DMAC specifications. Figures 1.13.2 to 1.13.4 show the registers
used by the DMAC.
Figure 1.13.1. Block diagram of DMAC
Data bus low-order bits
DMA latch high-order bits
DMA latch low-order bits
DMA0 source pointer SAR0(20)
DMA0 destination pointer DAR0 (20)
DMA0 forward address pointer (20) (Note)
Data bus high-order bits
Address bus
DMA1 destination pointer DAR1 (20)
DMA1 source pointer SAR1 (20)
DMA1 forward address pointer (20) (Note)
DMA0 transfer counter reload register TCR0 (16)
DMA0 transfer counter TCR0 (16)
DMA1 transfer counter reload register TCR1 (16)
DMA1 transfer counter TCR1 (16)
(addresses 0029
16
, 0028
16
)
(addresses 0039
16
, 0038
16
)
(addresses 0022
16
to 0020
16
)
(addresses 0026
16
to 0024
16
)
(addresses 0032
16
to 0030
16
)
(addresses 0036
16
to 0034
16
)
Note: Pointer is incremented by a DMA request.
Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer
request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the
interrupt priority level. The DMA transfer doesn't affect any interrupts either.
If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request
signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA
transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the
number of transfers. For details, see the description of the DMA request bit.
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
68
Item
Specification
No. of channels
2 (cycle steal method)
Transfer memory space
From any address in the 1M bytes space to a fixed address
From a fixed address to any address in the 1M bytes space
From a fixed address to a fixed address
(Note that DMA-related registers [0020
16
to 003F
16
] cannot be accessed)
Maximum No. of bytes transferred
128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
DMA request factors (Note)
________
________
Falling edge of INT0 or INT1 or both edge
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 transfer and reception interrupt requests
UART1 transfer and reception interrupt requests
UART2 transfer and reception interrupt requests
Serial I/O3, 4 interrpt requests
A-D conversion interrupt requests
Software triggers
Channel priority
DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously
Transfer unit
8 bits or 16 bits
Transfer address direction
forward/fixed (forward direction cannot be specified for both source and
destination simultaneously)
Transfer mode
Single transfer mode
After the transfer counter underflows, the DMA enable bit turns to
"0", and the DMAC turns inactive
Repeat transfer mode
After the transfer counter underflows, the value of the transfer counter
reload register is reloaded to the transfer counter.
The DMAC remains active unless a "0" is written to the DMA enable bit.
DMA interrupt request generation timing When an underflow occurs in the transfer counter
Active
When the DMA enable bit is set to "1", the DMAC is active.
When the DMAC is active, data transfer starts every time a DMA
transfer request signal occurs.
Inactive
When the DMA enable bit is set to "0", the DMAC is inactive.
After the transfer counter underflows in single transfer mode
At the time of starting data transfer immediately after turning the DMAC active, the
value of one of source pointer and destination pointer - the one specified for the
forward direction - is reloaded to the forward direction address pointer, and the value
of the transfer counter reload register is reloaded to the transfer counter.
Writing to register
Registers specified for forward direction transfer are always write enabled.
Registers specified for fixed address transfer are write-enabled when
the DMA enable bit is "0".
Reading the register
Can be read at any time.
However, when the DMA enable bit is "1", reading the register set up as the
forward register is the same as reading the value of the forward address pointer.
Table 1.13.1. DMAC specifications
Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable
flag (I flag) nor by the interrupt priority level.
Reload timing for forward ad-
dress pointer and transfer
counter
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
69
DMA0 request cause select register
Symbol
Address
When reset
DM0SL
03B8
16
00
16
Function
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
DMA request cause
select bit
DSEL0
R
W
DSEL1
DSEL2
DSEL3
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
Software DMA
request bit
If software trigger is selected, a
DMA request is generated by
setting this bit to "1" (When read,
the value of this bit is always "0")
DSR
b3 b2 b1 b0
0 0 0 0 : Falling edge of INT0 pin
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3
0 1 1 0 : Timer A4 (DMS=0)
/two edges of INT0 pin (DMS=1)
0 1 1 1 : Timer B0 (DMS=0)
Timer B3 (DMS=1)
1 0 0 0 : Timer B1 (DMS=0)
Timer B4 (DMS=1)
1 0 0 1 : Timer B2 (DMS=0)
Timer B5 (DMS=1)
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART2 transmit
1 1 0 1 : UART2 receive
1 1 1 0 : A-D conversion
1 1 1 1 : UART1 transmit
Bit name
DMA request cause
expansion select bit
DMS
0 : Normal
1 : Expanded cause
Figure 1.13.2. DMAC register (1)
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
70
DMAi control register
Symbol
Address
When reset
DMiCON(i=0,1)
002C
16
, 003C
16
00000X00
2
Bit name
Function
Bit symbol
Transfer unit bit select bit
b7
b6
b5
b4
b3
b2
b1
b0
0 : 16 bits
1 : 8 bits
DMBIT
R
W
DMASL
DMAS
DMAE
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
DMA request bit (Note 1)
0 : DMA not requested
1 : DMA requested
0 : Disabled
1 : Enabled
0 : Fixed
1 : Forward
DMA enable bit
Source address direction
select bit (Note 3)
Destination address
direction select bit (Note 3)
0 : Fixed
1 : Forward
DSD
DAD
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
Note 1: DMA request can be cleared by resetting the bit.
Note 2: This bit can only be set to "0".
Note 3: Source address direction select bit and destination address direction select bit
cannot be set to "1" simultaneously.
(Note 2)
DMA1 request cause select register
Symbol
Address
When reset
DM1SL
03BA
16
00
16
Function
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
DMA request cause
select bit
DSEL0
R
W
DSEL1
DSEL2
DSEL3
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
Software DMA
request bit
If software trigger is selected, a
DMA request is generated by
setting this bit to "1" (When read,
the value of this bit is always "0")
DSR
b3 b2 b1 b0
0 0 0 0 : Falling edge of INT1 pin
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3(DMS=0)
/serial I/O3 (DMS=1)
0 1 1 0 : Timer A4 (DMS=0)
/serial I/O4 (DMS=1)
0 1 1 1 : Timer B0 (DMS=0)
/two edges of INT1 (DMS=1)
1 0 0 0 : Timer B1
1 0 0 1 : Timer B2
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART2 transmit
1 1 0 1 : UART2 receive
1 1 1 0 : A-D conversion
1 1 1 1 : UART1 receive
Bit name
DMA request cause
expansion select bit
DMS
0 : Normal
1 : Expanded cause
Figure 1.13.3. DMAC register (2)
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
71
b7
b0
b7
b0
(b8)
(b15)
Function
R W
Transfer counter
Set a value one less than the transfer count
Symbol
Address
When reset
TCR0
0029
16
, 0028
16
Indeterminate
TCR1
0039
16
, 0038
16
Indeterminate
DMAi transfer counter (i = 0, 1)
Transfer count
specification
0000
16
to FFFF
16
b7
(b23)
b3
b0
b7
b0
b7
b0
(b8)
(b16)(b15)
(b19)
Function
R W
Source pointer
Stores the source address
Symbol
Address
When reset
SAR0
0022
16
to 0020
16
Indeterminate
SAR1
0032
16
to 0030
16
Indeterminate
DMAi source pointer (i = 0, 1)
Transfer address
specification
00000
16
to FFFFF
16
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
Symbol
Address
When reset
DAR0
0026
16
to 0024
16
Indeterminate
DAR1
0036
16
to 0034
16
Indeterminate
b3
b0
b7
b0
b7
b0
(b8)
(b15)
(b16)
(b19)
Function
R W
Destination pointer
Stores the destination address
DMAi destination pointer (i = 0, 1)
Transfer address
specification
00000
16
to FFFFF
16
b7
(b23)
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
Figure 1.13.4. DMAC register (3)
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
72
(1) Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area
(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination
write). The number of read and write bus cycles depends on the source and destination addresses. In
memory expansion mode and microprocessor mode, the number of read and write bus cycles also de-
pends on the level of the BYTE pin. Also, the bus cycle itself is longer when software waits are inserted.
(a) Effect of source and destination addresses
When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd
addresses, there are one more source read cycle and destination write cycle than when the source
and destination both start at even addresses.
(b) Effect of BYTE pin level
When transferring 16-bit data over an 8-bit data bus (BYTE pin = "H") in memory expansion mode and
microprocessor mode, the 16 bits of data are sent in two 8-bit blocks. Therefore, two bus cycles are
required for reading the data and two are required for writing the data. Also, in contrast to when the
CPU accesses internal memory, when the DMAC accesses internal memory (internal ROM, internal
RAM, and SFR), these areas are accessed using the data size selected by the BYTE pin.
(c) Effect of software wait
When the SFR area or a memory area with a software wait is accessed, the number of cycles is
increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK.
Figure 1.13.5 shows the example of the transfer cycles for a source read. For convenience, the destina-
tion write cycle is shown as one cycle and the source read cycles for the different conditions are shown.
In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the
transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respec-
tive conditions to both the destination write cycle and the source read cycle. For example (2) in Figure
1.13.5, if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the
source read cycle and the destination write cycle.
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
73
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use
CPU use
CPU use
Source
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
(1) 8-bit transfers
16-bit transfers and the source address is even.
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use
CPU use
CPU use
Source
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
(3) One wait is inserted into the source read under the conditions in (1)
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use
CPU use
CPU use
Source
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
Source + 1
Source + 1
(2) 16-bit transfers and the source address is odd
Transferring 16-bit data on an 8-bit data bus (In this case, there are also two destination cycles).
BCLK
Address
bus
RD signal
WR signal
Data
bus
CPU use
CPU use
CPU use
CPU use
Source
Source
Destination
Destination
Dummy
cycle
Dummy
cycle
Source + 1
Source + 1
(4) One wait is inserted into the source read under the conditions in (2)
(When 16-bit data is transferred on an 8-bit data bus, there are two destination cycles).
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 1.13.5. Example of the transfer cycles for a source read
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
74
Single-chip mode
Memory expansion mode
Transfer unit
Bus width
Access address
Microprocessor mode
No. of read
No. of write
No. of read No. of write
cycles
cycles
cycles
cycles
16-bit
Even
1
1
1
1
8-bit transfers
(BYTE= "L")
Odd
1
1
1
1
(DMBIT= "1")
8-bit
Even
--
--
1
1
(BYTE = "H")
Odd
--
--
1
1
16-bit
Even
1
1
1
1
16-bit transfers
(BYTE = "L")
Odd
2
2
2
2
(DMBIT= "0")
8-bit
Even
--
--
2
2
(BYTE = "H")
Odd
--
--
2
2
Table 1.13.2. No. of DMAC transfer cycles
Internal memory
External memory
Internal ROM/RAM
Internal ROM/RAM
SFR area
Separate bus
Separate bus
Multiplex
No wait
With wait
No wait
With wait
bus
1
2
2
1
2
3
Coefficient j, k
(2) DMAC transfer cycles
Any combination of even or odd transfer read and write addresses is possible. Table 1.13.2 shows the
number of DMAC transfer cycles.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
75
DMA enable bit
Setting the DMA enable bit to "1" makes the DMAC active. The DMAC carries out the following operations
at the time data transfer starts immediately after DMAC is turned active.
(1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the
forward direction - to the forward direction address pointer.
(2) Reloads the value of the transfer counter reload register to the transfer counter.
Thus overwriting "1" to the DMA enable bit with the DMAC being active carries out the operations given
above, so the DMAC operates again from the initial state at the instant "1" is overwritten to the DMA
enable bit.
DMA request bit
The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of
DMA request factors for each channel.
DMA request factors include the following.
* Factors effected by using the interrupt request signals from the built-in peripheral functions and software
DMA factors (internal factors) effected by a program.
* External factors effected by utilizing the input from external interrupt signals.
For the selection of DMA request factors, see the descriptions of the DMAi factor selection register.
The DMA request bit turns to "1" if the DMA transfer request signal occurs regardless of the DMAC's state
(regardless of whether the DMA enable bit is set to "1" or "0"). It turns to "0" immediately before data
transfer starts.
In addition, it can be set to "0" by use of a program, but cannot be set to "1".
There can be instances in which a change in DMA request factor selection bit causes the DMA request bit
to turn to "1". So be sure to set the DMA request bit to "0" after the DMA request factor selection bit is
changed.
The DMA request bit turns to "1" if a DMA transfer request signal occurs, and turns to "0" immediately
before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the
DMA request bit, if read by use of a program, turns out to be "0" in most cases. To examine whether the
DMAC is active, read the DMA enable bit.
Here follows the timing of changes in the DMA request bit.
(1) Internal factors
Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to "1" due
to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to
turn to "1" due to several factors.
Turning the DMA request bit to "0" due to an internal factor is timed to be effected immediately before the
transfer starts.
(2) External factors
_______
An external factor is a factor caused to occur by the leading edge of input from the INTi pin (i depends on
which DMAC channel is used).
_______
Selecting the INTi pins as external factors using the DMA request factor selection bit causes input from
these pins to become the DMA transfer request signals.
The timing for the DMA request bit to turn to "1" when an external factor is selected synchronizes with the
signal's edge applicable to the function specified by the DMA request factor selection bit (synchronizes
_______
with the trailing edge of the input signal to each INTi pin, for example).
With an external factor selected, the DMA request bit is timed to turn to "0" immediately before data
transfer starts similarly to the state in which an internal factor is selected.
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
76
(3) The priorities of channels and DMA transfer timing
If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period from
the leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels concurrently
turn to "1". If the channels are active at that moment, DMA0 is given a high priority to start data transfer.
When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU finishes single bus
access, then DMA1 starts data transfer and gives the bus right to the CPU.
An example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer
request signals due to external factors concurrently occur.
Figure 1.13.6 An example of DMA transfer effected by external factors.
BCLK
DMA0
DMA1
DMA0
request bit
DMA1
request bit
CPU
INT0
INT1
Obtainment
of the bus
right
An example in which DMA transmission is carried out in minimum
cycles at the time when DMA transmission request signals due to
external factors concurrently occur.
Figure 1.13.6. An example of DMA transfer effected by external factors
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer
77
Timer
There are eleven 16-bit timers. These timers can be classified by function into timers A (five) and timers B
(six). All these timers function independently. Figures 1.14.1 and 1.14.2 show the block diagram of timers.
Timer mode
One-shot timer mode
PWM mode
Timer mode
One-shot timer mode
PWM mode
Timer mode
One-shot timer mode
PWM mode
Timer mode
One-shot timer mode
PWM mode
Timer mode
One-shot timer mode
PWM mode
Event counter mode
Event counter mode
Event counter mode
Event counter mode
Event counter mode
TA0
IN
TA1
IN
TA2
IN
TA3
IN
TA4
IN
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
f
1
f
8
f
32
f
C32
Timer A0 interrupt
Timer A1 interrupt
Timer A2 interrupt
Timer A3 interrupt
Timer A4 interrupt
Noise
filter
Noise
filter
Noise
filter
Noise
filter
Noise
filter
1/32
f
C32
1/8
1/4
f
1
f
8
f
32
X
IN
X
CIN
Clock prescaler reset flag (bit 7
at address 0381
16
) set to "1"
Reset
Clock prescaler
Timer B2 overflow
Note 1: The TA0
IN
pin (P7
1
) is shared with RxD
2
and the TB5
IN
pin, so be careful.
Figure 1.14.1. Timer A block diagram
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer
78
Figure 1.14.2. Timer B block diagram
Event counter mode
Event counter mode
Event counter mode
Timer mode
Pulse width measuring mode
Timer mode
Pulse width measuring mode
Timer mode
Pulse width measuring mode
TB0
IN
TB1
IN
TB2
IN
Timer B0
Timer B1
Timer B2
f
1
f
8
f
32
f
C32
Timer B0 interrupt
Noise
filter
Noise
filter
Noise
filter
1/32
f
C32
1/8
1/4
f
1
f
8
f
32
X
IN
X
CIN
Clock prescaler reset flag (bit 7
at address 0381
16
) set to "1"
Reset
Clock prescaler
Timer A
Event counter mode
Event counter mode
Event counter mode
Timer mode
Pulse width measuring mode
Timer mode
Pulse width measuring mode
Timer mode
Pulse width measuring mode
TB3
IN
TB4
IN
TB5
IN
Timer B3
Timer B4
Timer B5
Timer B3 interrupt
Noise
filter
Noise
filter
Noise
filter
Timer B1 interrupt
Timer B2 interrupt
Timer B4 interrupt
Timer B5 interrupt
Note 1: The TB5
IN
pin (P7
1
) is shared with RxD
2
and the TA0
IN
pin, so be careful.
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
79
Timer A
Figure 1.14.3 shows the block diagram of timer A. Figures 1.14.4 to 1.14.6 show the timer A-related
registers.
Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode
register (i = 0 to 4) bits 0 and 1 to choose the desired mode.
Timer A has the four operation modes listed as follows:
Timer mode: The timer counts an internal count source.
Event counter mode: The timer counts pulses from an external source or a timer over flow.
One-shot timer mode: The timer stops counting when the count reaches "0000
16
".
Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
Figure 1.14.4. Timer A-related registers (1)
Count start flag
(Address 0380
16
)
Up count/down count
TAi
Addresses
TAj
TAk
Timer A0
0387
16
0386
16
Timer A4
Timer A1
Timer A1
0389
16
0388
16
Timer A0
Timer A2
Timer A2
038B
16
038A
16
Timer A1
Timer A3
Timer A3
038D
16
038C
16
Timer A2
Timer A4
Timer A4 038F
16
038E
16
Timer A3
Timer A0
Always down count except
in event counter mode
Reload register (16)
Counter (16)
Low-order
8 bits
High-order
8 bits
Clock source
selection
Timer
(gate function)
Timer
One shot
PWM
f
1
f
8
f
32
External
trigger
TAi
IN
(i = 0 to 4)
TB2 overflow
Event counter
f
C32
Clock selection
TAj overflow
(j = i 1. Note, however, that j = 4 when i = 0)
Pulse output
Toggle flip-flop
TAi
OUT
(i = 0 to 4)
Data bus low-order bits
Data bus high-order bits
Up/down flag
Down count
(Address 0384
16
)
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
Polarity
selection
Timer Ai mode register
Symbol
Address
When reset
TAiMR(i=0 to 4)
0396
16
to 039A
16
00
16
Bit name
Function
Bit symbol
W
R
b7
b6
b5
b4
b3
b2
b1
b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
b1 b0
TCK1
MR3
MR2
MR1
TMOD1
MR0
TMOD0
TCK0
Function varies with each operation mode
Count source select bit
(Function varies with each operation mode)
Operation mode select bit
Figure 1.14.3. Block diagram of timer A
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
80
Figure 1.14.5. Timer A-related registers (2)
Timer A4 up/down flag
Timer A3 up/down flag
Timer A2 up/down flag
Timer A1 up/down flag
Timer A0 up/down flag
Timer A2 two-phase pulse
signal processing select bit
Timer A3 two-phase pulse
signal processing select bit
Timer A4 two-phase pulse
signal processing select bit
Symbol
Address
When reset
UDF
0384
16
00
16
TA4P
TA3P
TA2P
Up/down flag (Note 1)
Bit name
Function
Bit symbol
W
R
b7
b6
b5
b4
b3
b2
b1
b0
TA4UD
TA3UD
TA2UD
TA1UD
TA0UD
0 : Down count
1 : Up count
This specification becomes valid
when the up/down flag content is
selected for up/down switching
cause
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled (Note 2)
When not using the two-phase
pulse signal processing function,
set the select bit to "0"
Symbol
Address
When reset
TABSR
0380
16
00
16
Count start flag
Bit name
Function
Bit symbol
W
R
b7
b6
b5
b4
b3
b2
b1
b0
Timer B2 count start flag
Timer B1 count start flag
Timer B0 count start flag
Timer A4 count start flag
Timer A3 count start flag
Timer A2 count start flag
Timer A1 count start flag
Timer A0 count start flag
0 : Stops counting
1 : Starts counting
TB2S
TB1S
TB0S
TA4S
TA3S
TA2S
TA1S
TA0S
Symbol
Address
When reset
TA0
0387
16
,0386
16
Indeterminate
TA1
0389
16
,0388
16
Indeterminate
TA2
038B
16
,038A
16
Indeterminate
TA3
038D
16
,038C
16
Indeterminate
TA4
038F
16
,038E
16
Indeterminate
b7
b0 b7
b0
(b15)
(b8)
Timer Ai register (Note 1)
W
R
Timer mode
0000
16
to FFFF
16
Counts an internal count source
Function
Values that can be set
Event counter mode
0000
16
to FFFF
16
Counts pulses from an external source or timer overflow
One-shot timer mode
0000
16
to FFFF
16
Counts a one shot width
(Note 2,4)
Pulse width modulation mode (16-bit PWM)
Functions as a 16-bit pulse width modulator
Pulse width modulation mode (8-bit PWM)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator
0000
16
to FFFE
16
(Note 3,4)
Note 1: Read and write data in 16-bit units.
Note 2: When the timer Ai register is set to "0000
16
", the counter does not
operate and the timer Ai interrupt request is not generated. When
the pulse is set to output, the pulse does not output from the TAi
OUT
pin.
Note 3: When the timer Ai register is set to "0000
16
", the pulse width
modulator does not operate and the output level of the TAi
OUT
pin
remains "L" level, therefore the timer Ai interrupt request is not
generated. This also occurs in the 8-bit pulse width modulator mode
when the significant 8 high-order bits in the timer Ai register are set
to "00
16
".
Note 4: Use MOV instruction to write to this register.<