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Datasheet: LXP604 (Level One)

Low-Jitter Clock Adapters(CLADs)

 

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Level One

Document Outline

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CLKI
SEL
HFO
CLKO
Analog
Phase-Locked
Loop
Feedback
Divider
Frequency
Converter
Output Divider
Frame Sync
Generator
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FSI
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Frame Sync Output. Frame synchronization output at 8 kHz. FSO is synced to CLKO
and to FSI (if FSI is provided).
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2
High Frequency Output
HFO is used to derive CLKO. HFO can also clock external
devices. HFO is always a multiple of CLKO (CLKO x2, x3, or x4).
Actual frequencies are determined by device, CLKI and CLKO frequencies and Mode
Select (SEL) input, as listed in Table 2.
&/.,
,
Clock Input
Input clock (1.544, 2.048 or 4.096 MHz) to be converted.
&/.2
2
Clock Output
Output clock (1.544, 2.048 or 4.096 MHz) derived from CLKI.
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Mode Select. controls frequency conversion as listed in Table 2.
When SEL = High, higher frequency CLKI (2.048 for LXP600A and LXP602, or 4.096
MHz for LXP604) is converted to 1.544 MHz CLKO.
When SEL = Low, 1.544 MHz CLKI is converted to higher frequency CLKO (2.048 for
LXP600A and LXP602, or 4.096 MHz for LXP604).
FSI
,
Frame Sync Input
8 kHz frame synchronization pulse. Tie High or Low if not used.
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Power Supply
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Standard CMOS device precautions apply to the CLAD.
Inputs must be applied either simultaneously with or after
the power supply VCC. CLAD input signals include
CLKI, FSI and SEL.
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Frame Sync (FSI) Generation Circuit
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System Frame
Sync Output
FSI to CLAD
2.048 MHz
System
Clock
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