HTML datasheet archive (search documentation on electronic components) Search datasheet (1.687.043 components)
Search field

Datasheet: L29C525 (Logic Devices Incorporated)

Dual Pipeline Register

 

Download: PDF   ZIP
Logic Devices Incorporated
DEVICES INCORPORATED
L29C525
Dual Pipeline Register
Pipeline Registers
03/
23/2000LDS.29C525-G
1
u
u
u
u
u Dual 8-Deep Pipeline Register
u
u
u
u
u Configurable to Single 16-Deep
u
u
u
u
u Low Power CMOS Technology
u
u
u
u
u Replaces AMD Am29525
u
u
u
u
u Load, Shift, and Hold Instructions
u
u
u
u
u Separate Data In and Data Out Pins
u
u
u
u
u Three-State Outputs
u
u
u
u
u Package Styles Available:
28-pin Plastic DIP
28-pin Plastic LCC, J-Lead
FEATURES
DESCRIPTION
L29C525
Dual Pipeline Register
DEVICES INCORPORATED
The L29C525 is a high-speed, low
power CMOS pipeline register. It is
pin-for-pin compatible with the AMD
Am29525. The L29C525 can be
configured as two independent 8-level
pipelines or as a single 16-level
pipeline. The configuration imple-
mented is determined by the instruc-
tion code (I
1-0
) as shown in Table 2.
The I
1-0
instruction code controls the
internal routing of data and loading of
each register. For instruction I
1-0
= 00
(Push A and B), data applied at the
D
7-0
inputs is latched into register A0
on the rising edge of CLK. The
contents of A0 simultaneously move
to register A1, A1 moves to A2, and so
on. The contents of register A7 are
wrapped back to register B0. The
registers on the B side are similarly
shifted, with the contents of register
B7 lost.
Instruction I
1-0
= 01 (Push B) acts
similarly to the Push A and B
instruction, except that only the B side
registers are shifted. The input data is
applied to register B0, and the
contents of register B7 are lost. The
contents of the A side registers are
unaffected. Instruction I
1-0
= 10 (Push
A) is identical to the Push B
instruction, except that the A side
registers are shifted and the B side
registers are unaffected.
Instruction I
1-0
= 11 (Hold) causes no
internal data movement. It is equiva-
lent to preventing the application of a
clock edge to any internal register.
The contents of any of the registers is
selectable at the output through the
use of the S
3-0
control inputs. The
independence of the I and S control
lines allows simultaneous reading and
writing. Encoding for the S
3-0
controls
is given in Table 3.
L29C525 B
LOCK
D
IAGRAM
8
OE
Y
7-0
D
7-0
I
1-0
CLK
MUX
4
MUX
2
S
3-0
REGISTER A0
REGISTER A1
REGISTER A2
REGISTER A3
REGISTER A4
REGISTER A5
REGISTER A6
REGISTER A7
REGISTER B0
REGISTER B1
REGISTER B2
REGISTER B3
REGISTER B4
REGISTER B5
REGISTER B6
REGISTER B7
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
8
DEVICES INCORPORATED
L29C525
Dual Pipeline Register
Pipeline Registers
03/27/2000LDS.29C525-G
2
T
ABLE
1.
R
EGISTER
L
OAD
O
PERATIONS
Single 16 Level
Dual 8 Level
Push A and B
Push A
Hold All Registers
Push B
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
HOLD
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
HOLD
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
HOLD
HOLD
T
ABLE
2.
I
NSTRUCTION
S
ET
T
ABLE
3.
O
UTPUT
S
ELECT
Inputs
Mnemonics
I
1
I
0
Description
Shift
0
0
Push A and B
LDB
0
1
Push B
LDA
1
0
Push A
HLD
1
1
Hold All Registers
S
3
S
2
S
1
S
0
Y
7-0
0
0
0
0
A0
0
0
0
1
A1
0
0
1
0
A2
0
0
1
1
A3
0
1
0
0
A4
0
1
0
1
A5
0
1
1
0
A6
0
1
1
1
A7
1
0
0
0
B0
1
0
0
1
B1
1
0
1
0
B2
1
0
1
1
B3
1
1
0
0
B4
1
1
0
1
B5
1
1
1
0
B6
1
1
1
1
B7
DEVICES INCORPORATED
L29C525
Dual Pipeline Register
Pipeline Registers
03/32/2000LDS.29C525-G
3
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
V
OH
Output High Voltage
V
CC
= Min., I
OH
= 12 mA
2.4
V
V
OL
Output Low Voltage
V
CC
= Min., I
OL
= 24 mA
0.5
V
V
IH
Input High Voltage
2.0
V
CC
V
V
IL
Input Low Voltage
(Note 3)
0.0
0.8
V
I
IX
Input Current
Ground
V
IN
V
CC
(Note 12)
20
A
I
OZ
Output Leakage Current
Ground
V
OUT
V
CC
(Note 12)
20
A
I
CC1
V
CC
Current, Dynamic
(Notes 5, 6)
10
35
mA
I
CC2
V
CC
Current, Quiescent
(Note 7)
1.0
mA
Storage temperature ........................................................................................................... 65C to +150C
Operating ambient temperature ........................................................................................... 55C to +125C
V
CC
supply voltage with respect to ground ............................................................................ 0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ 3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... 3.0 V to +7.0 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
M
AXIMUM
R
ATINGS
Above which useful life may be impaired (Notes 1, 2, 3, 8)
O
PERATING
C
ONDITIONS
To meet specified electrical and switching characteristics
E
LECTRICAL
C
HARACTERISTICS
Over Operating Conditions (Note 4)
Mode
Temperature Range (Ambient)
Supply
Voltage
Active Operation, Commercial
0C to +70C
4.75 V
V
CC
5.25 V
Active Operation, Military
55C to +125C
4.50 V
V
CC
5.50 V
DEVICES INCORPORATED
L29C525
Dual Pipeline Register
Pipeline Registers
03/27/2000LDS.29C525-G
4
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
1234567890123456789012345678901
L29C525
20
15
Symbol
Parameter
Min
Max
Min
Max
t
PD
Clock to Output Delay
20
15
t
SEL
Select to Output Delay
20
15
t
PW
Clock Pulse Width
12
10
t
SD
Data Setup Time
7
5
t
HD
Data Hold Time
0
0
t
SI
Instruction Setup Time
7
5
t
HI
Instruction Hold Time
2
2
t
ENA
Three-State Output Enable Delay
(Note 11)
15
15
t
DIS
Three-State Output Disable Delay
(Note 11)
13
13
C
OMMERCIAL
O
PERATING
R
ANGE
(0C to +70C)
Notes 9, 10 (ns)
SWITCHING CHARACTERISTICS
M
ILITARY
O
PERATING
R
ANGE
(55C to +125C)
Notes 9, 10 (ns)
L29C525
25*
20*
Symbol
Parameter
Min
Max
Min
Max
t
PD
Clock to Output Delay
25
20
t
SEL
Select to Output Delay
25
20
t
PW
Clock Pulse Width
12
12
t
SD
Data Setup Time
7
7
t
HD
Data Hold Time
2
2
t
SI
Instruction Setup Time
7
7
t
HI
Instruction Hold Time
2
2
t
ENA
Three-State Output Enable Delay
(Note 11)
15
15
t
DIS
Three-State Output Disable Delay
(Note 11)
13
13
S
WITCHING
W
AVEFORMS
HIGH IMPEDANCE
t
SD
CLK
OE
t
HI
Y
7-0
D
7-0
I
1-0
S
3-0
t
SI
t
HD
t
PW
t
PW
t
SEL
t
PD
t
DIS
t
ENA
1234567890123456789
1234567890123456789
1234567890123456789
*D
ISCONTINUED
S
PEED
G
RADE
DEVICES INCORPORATED
L29C525
Dual Pipeline Register
Pipeline Registers
03/32/2000LDS.29C525-G
5
1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values beyond
those indicated in the Operating Condi-
tions table is not implied. Exposure to
maximum rating conditions for ex-
tended periods may affect reliability.
2. The products described by this spec-
ification include internal circuitry de-
signed to protect the chip from damag-
ing substrate injection currents and ac-
cumulations of static charge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. This device provides hard clamping of
transient undershoot and overshoot. In-
put levels below ground or above V
CC
will be clamped beginning at 0.6 V and
V
CC
+ 0.6 V. The device can withstand
indefinite operation with inputs in the
range of 0.5 V to +7.0 V. Device opera-
tion will not be adversely affected, how-
ever, input current levels will be well in
excess of 100 mA.
4. Actual test conditions may vary from
those designated but operation is guar-
anteed as specified.
5. Supply current for a given applica-
tion can be accurately approximated by:
where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 5 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
V
CC
or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
NCV F
4
2
NOTES
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
t
DIS
test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified I
OH
and I
OL
at an output
voltage of V
OH
min and V
OL
max
respectively. Alternatively, a diode
bridge with upper and lower current
sources of I
OH
and I
OL
respectively,
and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.
This device has high-speed outputs ca-
pable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:
a. A 0.1 F ceramic capacitor should be
installed between V
CC
and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device V
CC
and the tester common, and device
ground and tester common.
b. Ground and V
CC
supply planes
must be brought directly to the DUT
socket or contactor fingers.
c. Input voltages should be adjusted to
compensate for inductive ground and V
CC
noise to maintain required DUT input
levels relative to the DUT ground pin.
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. For the t
ENA
test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the t
DIS
test,
the transition is measured to the
200mV level from the measured
steady-state output voltage with
10mA loads. The balancing volt-
age, V
TH
, is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Z-
to-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
S1
I
OH
I
OL
V
TH
C
L
DUT
OE
0.2 V
t
DIS
t
ENA
0.2 V
1.5 V
1.5 V
3.5V Vth
1
Z
0
Z
Z
1
Z
0
1.5 V
1.5 V
0V Vth
V
OL
*
V
OH
*
V
OL
*
V
OH
*
Measured V
OL
with I
OH
= 10mA and I
OL
= 10mA
Measured V
OH
with I
OH
= 10mA and I
OL
= 10mA
F
IGURE
B. T
HRESHOLD
L
EVELS
F
IGURE
A. O
UTPUT
L
OADING
C
IRCUIT
© 2019 • ICSheet
Contact form
Main page