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Datasheet: L29C521PC22 (Logic Devices Incorporated)

4 x 8-bit Multilevel Pipeline Register

 

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Logic Devices Incorporated
DEVICES INCORPORATED
L29C520/521
4 x 8-bit Multilevel Pipeline Register
Pipeline Registers
08/02/2000LDS.520/1-P
1
u
u
u
u
u Four 8-bit Registers
u
u
u
u
u Implements Double 2-Stage Pipeline
or Single 4-Stage Pipeline Register
u
u
u
u
u Hold, Shift, and Load Instructions
u
u
u
u
u Separate Data In and Data Out Pins
u
u
u
u
u High-Speed, Low Power CMOS
Technology
u
u
u
u
u Three-State Outputs
u
u
u
u
u Replaces IDT29FCT520/IDT29FCT521
and AMD Am29520/Am29521
u
u
u
u
u Package Styles Available:
24-pin PDIP
28-pin PLCC, J-Lead
FEATURES
DESCRIPTION
L29C520/521
4 x 8-bit Multilevel Pipeline Register
DEVICES INCORPORATED
The L29C520 and L29C521 are pin-
for-pin compatible with the
IDT29FCT520/IDT29FCT521 and
AMD Am29520/Am29521, imple-
mented in low power CMOS.
The L29C520 and L29C521 contain
four registers which can be configured
as two independent, 2-level pipelines
or as one 4-level pipeline.
The Instruction pins, I
1-0
, control the
loading of the registers. For either
device, the registers may be config-
ured as a four-stage delay line, with
data loaded into R1 and shifted
sequentially through R2, R3, and R4.
Also, for the L29C520, data may be
loaded from the inputs into either R1
or R3 with only R2 or R4 shifting. The
L29C521 differs from the L29C520 in
that R2 and R4 remain unchanged
during this type of data load, as
shown in Tables 1 and 2. Finally, I
1-0
may be set to prevent any register
from changing.
The S
1-0
select lines control a 4-to-1
multiplexer which routes the contents
of any of the registers to the Y output
pins. The independence of the I and S
controls allows simultaneous write
and read operations on different
registers.
S
1
S
0
Register Selected
L
L
Register 4
L
H
Register 3
H
L
Register 2
H
H
Register 1
T
ABLE
3.
O
UTPUT
S
ELECT
I
1
I
0
Description
L
L
D
R1
R1
R2
R2
R3
R3
R4
L
H
HOLD
HOLD
D
R3
HOLD
H
L
D
R1
HOLD
HOLD
HOLD
H
H
ALL REGISTERS ON HOLD
T
ABLE
2.
L29C521 I
NSTRUCTION
T
ABLE
I
1
I
0
Description
L
L
D
R1
R1
R2
R2
R3
R3
R4
L
H
HOLD
HOLD
D
R3
R3
R4
H
L
D
R1
R1
R2
HOLD
HOLD
H
H
ALL REGISTERS ON HOLD
T
ABLE
1.
L29C520 I
NSTRUCTION
T
ABLE
L29C520/521 B
LOCK
D
IAGRAM
MUX
REG 1
REG 2
REG 3
REG 4
REGISTER 1
REGISTER 2
REGISTER 3
REGISTER 4
MUX
D
8-0
8
8
OE
Y
7-0
S
1-0
I
1-0
CLK
2
2
DEVICES INCORPORATED
L29C520/521
4 x 8-bit Multilevel Pipeline Register
Pipeline Registers
08/02/2000LDS.520/1-P
2
Storage temperature ........................................................................................................... 65C to +150C
Operating ambient temperature ........................................................................................... 55C to +125C
V
CC
supply voltage with respect to ground ............................................................................ 0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ 3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... 3.0 V to +7.0 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
M
AXIMUM
R
ATINGS
Above which useful life may be impaired (Notes 1, 2, 3, 8)
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
V
OH
Output High Voltage
V
CC
= Min., I
OH
= 15.0 mA
2.4
V
V
OL
Output Low Voltage
V
CC
= Min., I
OL
= 24.0 mA
0.5
V
V
IH
Input High Voltage
2.0
V
CC
V
V
IL
Input Low Voltage
(Note 3)
0.0
0.8
V
I
IX
Input Current
Ground
V
IN
V
CC
(Note 12)
20
A
I
OZ
Output Leakage Current
Ground
V
OUT
V
CC
(Note 12)
20
A
I
CC1
V
CC
Current, Dynamic
(Notes 5, 6)
30
mA
I
CC2
V
CC
Current, Quiescent
(Note 7)
1.5
mA
E
LECTRICAL
C
HARACTERISTICS
Over Operating Conditions (Note 4)
O
PERATING
C
ONDITIONS
To meet specified electrical and switching characteristics
Mode
Temperature Range (Ambient)
Supply
Voltage
Active Operation, Commercial
0C to +70C
4.75 V
V
CC
5.25 V
Active Operation, Military
55C to +125C
4.50 V
V
CC
5.50 V
DEVICES INCORPORATED
L29C520/521
4 x 8-bit Multilevel Pipeline Register
Pipeline Registers
08/02/2000LDS.520/1-P
3
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L29C520/521
22
14*
Symbol
Parameter
Min
Max
Min
Max
t
PD
Clock to Output Delay
22
14
t
SEL
Select to Output Delay
20
13
t
PW
Clock Pulse Width
10
7
t
SI
Instruction Setup Time
10
5
t
HI
Instruction Hold Time
3
1
t
SD
Data Setup Time
10
5
t
HD
Data Hold Time
3
1
t
ENA
Three-State Output Enable Delay
(Note 11)
21
15
t
DIS
Three-State Output Disable Delay
(Note 11)
15
12
C
OMMERCIAL
O
PERATING
R
ANGE
(0C to +70C)
Notes 9, 10 (ns)
SWITCHING CHARACTERISTICS
L29C520/521
30*
24*
16*
Symbol
Parameter
Min
Max
Min
Max
Min
Max
t
PD
Clock to Output Delay
30
24
16
t
SEL
Select to Output Delay
30
22
15
t
PW
Clock Pulse Width
15
10
8
t
SI
Instruction Setup Time
15
10
6
t
HI
Instruction Hold Time
5
3
2
t
SD
Data Setup Time
15
10
6
t
HD
Data Hold Time
5
3
2
t
ENA
Three-State Output Enable Delay
(Note 11)
25
22
16
t
DIS
Three-State Output Disable Delay
(Note 11)
20
16
13
M
ILITARY
O
PERATING
R
ANGE
(55C to +125C)
Notes 9, 10 (ns)
S
WITCHING
W
AVEFORMS
HIGH IMPEDANCE
t
ENA
t
DIS
t
PW
t
SI
t
SD
D
7-0
CLK
OE
t
PD
t
HD
t
HI
t
PW
t
SEL
I
1-0
S
1-0
Y
7-0
1234567890123456789
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*D
ISCONTINUED
S
PEED
G
RADE
DEVICES INCORPORATED
L29C520/521
4 x 8-bit Multilevel Pipeline Register
Pipeline Registers
08/02/2000LDS.520/1-P
4
1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values beyond
those indicated in the Operating Condi-
tions table is not implied. Exposure to
maximum rating conditions for ex-
tended periods may affect reliability.
2. The products described by this spec-
ification include internal circuitry de-
signed to protect the chip from damag-
ing substrate injection currents and ac-
cumulations of static charge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
3. This device provides hard clamping of
transient undershoot and overshoot. In-
put levels below ground or above V
CC
will be clamped beginning at 0.6 V and
V
CC
+ 0.6 V. The device can withstand
indefinite operation with inputs in the
range of 0.5 V to +7.0 V. Device opera-
tion will not be adversely affected, how-
ever, input current levels will be well in
excess of 100 mA.
4. Actual test conditions may vary from
those designated but operation is guar-
anteed as specified.
5. Supply current for a given applica-
tion can be accurately approximated by:
where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 5 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
V
CC
or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
NCV F
4
2
NOTES
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
t
DIS
test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified I
OH
and I
OL
at an output
voltage of V
OH
min and V
OL
max
respectively. Alternatively, a diode
bridge with upper and lower current
sources of I
OH
and I
OL
respectively,
and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.
This device has high-speed outputs ca-
pable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:
a. A 0.1 F ceramic capacitor should be
installed between V
CC
and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device V
CC
and the tester common, and device
ground and tester common.
b. Ground and V
CC
supply planes
must be brought directly to the DUT
socket or contactor fingers.
c. Input voltages should be adjusted to
compensate for inductive ground and V
CC
noise to maintain required DUT input
levels relative to the DUT ground pin.
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
11. For the t
ENA
test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the t
DIS
test,
the transition is measured to the
200mV level from the measured
steady-state output voltage with
10mA loads. The balancing volt-
age, V
TH
, is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Z-
to-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
S1
I
OH
I
OL
V
TH
C
L
DUT
OE
0.2 V
t
DIS
t
ENA
0.2 V
1.5 V
1.5 V
3.5V Vth
1
Z
0
Z
Z
1
Z
0
1.5 V
1.5 V
0V Vth
V
OL
*
V
OH
*
V
OL
*
V
OH
*
Measured V
OL
with I
OH
= 10mA and I
OL
= 10mA
Measured V
OH
with I
OH
= 10mA and I
OL
= 10mA
F
IGURE
B. T
HRESHOLD
L
EVELS
F
IGURE
A. O
UTPUT
L
OADING
C
IRCUIT
DEVICES INCORPORATED
L29C520/521
4 x 8-bit Multilevel Pipeline Register
Pipeline Registers
08/02/2000LDS.520/1-P
5
0C to +70C -- C
OMMERCIAL
S
CREENING
55C to +125C -- MIL-STD-883 C
OMPLIANT
55C to +125C -- C
OMMERCIAL
S
CREENING
24-pin -- 0.3" wide
28-pin
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
I
0
I
1
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CLK
GND
V
CC
S
0
S
1
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
OE
5
6
7
8
9
10
11
25
24
23
22
21
20
19
26
Top
View
27
12
17 18
4
28
3
1
2
13 14 15 16
NC
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
D
1
D
2
D
3
D
4
D
5
D
6
NC
D
7
CLK
GND
OE
Y
7
Y
6
NC
NC
D
0
I
1
I
0
V
CC
S
0
S
1
L29C520 -- ORDERING INFORMATION
Plastic DIP
(P2)
L29C520PC22
Plastic J-Lead Chip Carrier
(J4)
L29C520JC22
Speed
22 ns
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