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Datasheet: L2340 (Logic Devices Incorporated)

Digital Synthesizer

 

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Logic Devices Incorporated
DEVICES INCORPORATED
Special Arithmetic Functions
1
L2340
Digital Synthesizer
08/16/2000­LDS.2340-E
u
u
u
u
u
Digital Waveform Synthesis at
50 MHz
u
u
u
u
u 24-Bit Polar Phase Angle Accuracy
u
u
u
u
u User-selectable Waveform Synthesis,
Frequency Modulation, or Phase
Modulation.
u
u
u
u
u Amplitude Input for Amplitude
Modulation and Gain Adjustment.
u
u
u
u
u Replaces TRW/Raytheon/Fairchild
TMC2340A
u
u
u
u
u 120-pin PQFP
FEATURES
DESCRIPTION
L2340
Digital Synthesizer
DEVICES INCORPORATED
L2340 B
LOCK
D
IAGRAM
The L2340 is a digital synthesizer that
performs waveform synthesis, modu-
lation, and demodulation.
The L2340 automatically generates
quadrature matched pairs of 16-bit
sine and cosine waves in DAC-
compatible 16-bit offset binary format
with15-bit amplitude and 32-bit phase
inputs.
Output waveforms can be phase or
frequency modulated. Digital output
frequencies are restricted to the
Nyquist limit.
Functional Description
The L2340 converts Polar (Phase and
Magnitude) data into Rectangular
(Cartesian) coordinates. The user
selects the numeric format. A valid
transformed result is seen at the
output after 22 clock cycles and will
continue upon every clock cycle
thereafter.
15-bit amplitude and 32-bit phase data
are input into the L2340 to produce an
output of 16-bit rectangular data. The
user may select the data format to
either 16-bit offset binary or 15-bit
unsigned magnitude format. High
accuracy phase increment values with
minimal accumulation error is accom-
plished by use of a 32-bit phase
accumulator.
The phase accumulator structure
supports frequency or phase modula-
tion and is selected by ENP
1-0
and
accumulator controls FM and PM.
CLK
16
OEI
Q
15-0
15
2
32
ENA
AM
14-0
ENP
1-0
PH
31-0
FM
PM
OBIQ
I
15-0
OEQ
16
Digital
Synthesizer
DEVICES INCORPORATED
L2340
Digital Synthesizer
2
Special Arithmetic Functions
08/16/2000­LDS.2340-E
FM PM Configuration
0
0
No accumulation (normal operation)
0
1
PM accumulator path enabled
1
0
FM accumulator path enabled
1
1
Logical OR of PM and FM (Nonsensical)
T
ABLE
2. A
CCUMULATOR
C
ONTROL
SIGNAL DEFINITIONS
Power
Vcc and GND
+5V power supply. All pins must be
connected.
Clock
CLK -- Master Clock
The rising edge of CLK strobes all
enabled registers.
Inputs
AM
14-0
-- Amplitude Modulation Data
Input
AM
14-0
is the 15-bit Amplitude
Modulation Data input port. AM
14-0
is latched on the rising edge of CLK.
PH
31-0
-- Phase Angle Data Input
PH
31-0
is the 32-bit Phase Angle Data
input port. Input phase accumulators
are loaded through this port into
registers enabled by ENP
1-0
. PH
31-0
is
latched on the rising edge of CLK.
Outputs
I
15-0
-- x-coordinate Data Output
I
15-0
is the 16-bit Cartesian x-coordi-
nate Data output port. When OEI is
HIGH, I
15-0
is forced into the high-
impedance state. I
15
is forced HIGH if
OBIQ is LOW.
Q
15-0
-- y-coordinate Data Output
Q
15-0
is the 16-bit Cartesian y-coordi-
nate Data output port. When OEQ is
HIGH, Q
15-0
is forced into the high-
impedance state. Q
15
is forced HIGH
if OBIQ is LOW.
Controls
ENA -- Amplitude Modulation Data
Input Enable
When ENA is HIGH, AM is latched
into the input register on the rising
edge of clock. When ENA is LOW, the
value stored in the register is un-
changed.
ENP
1-0
-- Phase Modulation Data Input
Control
ENP
1-0
is the 2-bit Phase Modulation
Data Input Control that determines
one of the four modes shown in Table
1. `M' is the Modulation Register and
`C' is the Carrier Register as shown in
the Functional Block Diagram.
T
ABLE
1. R
EGISTER
O
PERATION
L2340 F
UNCTIONAL
B
LOCK
D
IAGRAM
I
15-0
Q
15-0
16
16
15
16
16
24
24
15
15
TRANSFORM
PROCESSOR
OEI
OEQ
OBIQ
32
32
32
AM
14-0
32
PH
31-0
32
FM
PM
ENA
ENP
1-0
2
*
REQUIRES 18 CYCLES TO COMPLETE AND IS FULLY PIPELINED
*
AM
PM
FM
M
C
ENP
1-0
Configuration
0 0
No registers enabled, current data held
0 1
M register input enabled, C data held
1 0
C register input enabled, M data held
1 1
M register = 0, C register input enabled
DEVICES INCORPORATED
Special Arithmetic Functions
3
L2340
Digital Synthesizer
08/16/2000­LDS.2340-E
F
IGURE
1
A
.
I
NPUT
F
ORMATS
14 13 12
2
1
0
2
14
2
13
2
12
2
2
2
1
2
0
31 30 29
2
1
0
*±2
0
2
­1
2
­2
2
­29
2
­30
2
­31
AM
PH
*±2
0
denotes two's complement sign or highest magnitude bit. Since phase angles are modulo 2
and phase accumulator is modulo 2
32
, this bit may be regarded as ±
.
Fract. Unsigned Mag./Two's Comp.
Integer Unsigned Magnitude
(RTP = 0)
FM, PM -- Frequency Modulation,
Phase Modulation Control
FM and PM is the 2-bit Frequency
Modulation/Phase Modulation
Control that determines one of the
four modes shown in Table 2. When
full-scale is exceeded, the accumulator
will roll over correctly allowing
continuous phase accumulation
through 2
radians.
OBIQ -- Data Input/Output Format
Select
When OBIQ is HIGH, offset binary
format is selected. When OBIQ is
LOW, unsigned format is selected.
OEI -- x-coordinate Data Output
Enable
When OEI is LOW, I
15-0
is enabled for
data output. When OEI is HIGH, I
15-0
is placed in a high-impedance state.
F
IGURE
1
B
.
O
UTPUT
F
ORMATS
14 13 12
2
1
0
2
14
2
13
2
12
2
2
2
1
2
0
14 13 12
2
1
0
2
14
2
13
2
12
2
2
2
1
2
0
Integer Unsigned Magnitude (OBIQ = 0)
15 14 13
2
1
0
NS 2
14
2
13
2
2
2
1
2
0
15 14 13
2
1
0
NS 2
14
2
13
2
2
2
1
2
0
Offset Binary (OBIQ = 1)
I
Q
NS denotes negative sign. (i.e. '1' negates the number)
OEQ -- y-coordinate Data Output
Enable
When OEQ is LOW, Q
15-0
is enabled
for data output. When OEQ is HIGH,
Q
15-0
is placed in a high-impedance
state.
DEVICES INCORPORATED
L2340
Digital Synthesizer
4
Special Arithmetic Functions
08/16/2000­LDS.2340-E
23140
23150
23160
23170
23180
23190
23200
23140
23150
23160
23170
23180
23190
23200
X
Y
23140
23150
23160
23170
23180
23190
23200
23140
23150
23160
23170
23180
23190
23200
X
Y
Circle Test
When performing a coordinate
transformation, inaccuracies are
introduced by a combination of
quantization and approximation
errors. The accuracy of a coordinate
transformer is dependent on the
word length used for the input
variables, the word length used for
internal calculations, as well as the
number of iterations or steps per-
formed. Truncation errors are due
to the finite word length and ap-
proximation errors are due to the
finite number of iterations. For
example, in the case of performing a
polar-to-rectangular transformation,
the accuracy of the rotation will be
determined by how closely the input
rotation angle was approximated by
the summation of sub-rotation
angles.
In this study, we compare how
accurately a coordinate transformer
with a 16-bit internal processor
versus a 24-bit internal processor
can calculate all the coordinates of a
circle. By setting the radius to
7FFFH,
is incremented using the
accumulator of the L2340 in steps of
0000 4000H until all the points of a
full circle are calculated into rectan-
gular coordinates.
The resulting rectangular coordi-
nates were plotted and graphed. A
graphical representation of the
resulting vectors for both 16-bit and
24-bit internal processors are com-
pared at 45°. Theoretically, a
perfect circle is the desired output
but when the resulting vectors from
a coordinate transformer with 16-bit
internal processor are graphed and
displayed as shown in Figure 2, we
see significant errors due to the
inherent properties of a digital
synthesizer. In comparison, the 24-
bit internal processor proves to be
significantly more accurate than a
16-bit internal processor due to
minimization of truncation errors.
In many applications, this margin of
F
IGURE
2.
C
IRCLE
T
EST
R
ESULT
N
EAR
45° (16-B
IT
I
NTERNAL
P
ROCES
-
SOR
)
F
IGURE
3.
C
IRCLE
T
EST
R
ESULT
N
EAR
45° (24-B
IT
I
NTERNAL
P
ROCES
-
SOR
)
error will introduce noise when
performing waveform sythesis,
modulation, and demodulation.
Data values for Figure 2 and Figure
3 are shown in Table 3. By looking
at these values, we observe the step
resolution on a 16-bit internal
processor is not 1 unit in the x and
y. In most cases, the minimum step
resolution is 2 units in the x and y.
On the other hand, step resolution
on a 24-bit internal processor is 1
unit in the x and y thus resulting in
greater accuracy.
The minimum theoretical angle
resolution that could be produced is
0.00175° when x = 7FFFH and y = 1H.
A 16-bit internal processor can
produce a minimum angle resolu-
tion of only 0.00549° and will not be
able to properly calculate the
theoretical minimum angle resolu-
tion. On the other hand, a 24-bit
internal processor can produce a
minimum angle resolution of
0.00002° and could therefore prop-
erly calculate the theoretical mini-
mum angle resolution.
DEVICES INCORPORATED
Special Arithmetic Functions
5
L2340
Digital Synthesizer
08/16/2000­LDS.2340-E
16-bit Internal Processor
24-bit Internal Processor
x
x (HEX)
y
y (HEX)
x
x (HEX)
y
y (HEX)
23201
5AA1
23139
5A63
23199
5A9F
23140
5A64
23199
5A9F
23141
5A65
23198
5A9E
23141
5A65
23199
5A9F
23141
5A65
23198
5A9E
23141
5A65
23199
5A9F
23141
5A65
23197
5A9D
23142
5A66
23199
5A9F
23141
5A65
23197
5A9D
23142
5A66
23197
5A9D
23143
5A67
23196
5A9C
23143
5A67
23197
5A9D
23143
5A67
23196
5A9C
23143
5A67
23197
5A9D
23143
5A67
23195
5A9B
23144
5A68
23197
5A9D
23143
5A67
23194
5A9A
23145
5A69
23195
5A9B
23145
5A69
23194
5A9A
23145
5A69
23195
5A9B
23145
5A69
23194
5A9A
23145
5A69
23195
5A9B
23145
5A69
23193
5A99
23146
5A6A
23195
5A9B
23145
5A69
23192
5A98
23147
5A6B
23192
5A98
23148
5A6C
23191
5A97
23148
5A6C
23192
5A98
03148
5A6C
23191
5A97
23148
5A6C
23192
5A98
23148
5A6C
23191
5A97
23148
5A6C
23192
5A98
23148
5A6C
23190
5A96
23149
5A6D
23190
5A96
23150
5A6E
23189
5A95
23150
5A6E
23190
5A96
23150
5A6E
23189
5A95
23150
5A6E
23190
5A96
23150
5A6E
23189
5A95
23150
5A6E
23190
5A96
23150
5A6E
23188
5A94
23151
5A6F
23187
5A93
23152
5A70
23187
5A93
23152
5A70
23187
5A93
23152
5A70
23186
5A92
23153
5A71
23187
5A93
23152
5A70
23186
5A92
23153
5A71
23187
5A93
23152
5A70
23186
5A92
23153
5A71
23185
5A91
23154
5A72
23185
5A91
23154
5A72
23185
5A91
23154
5A72
23184
5A90
23155
5A73
23185
5A91
23154
5A72
23184
5A90
23155
5A73
23185
5A91
23154
5A72
23184
5A90
23155
5A73
23183
5A8F
23156
5A74
23183
5A8F
23156
5A74
T
ABLE
3.
R
ESULTANT
D
ATA
V
ALUES
O
F
C
IRCLE
T
EST
N
EAR
45°
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