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Datasheet: KT12872SRN0R (Kentron Technologies, Inc.)

 

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Kentron Technologies, Inc.
155 West Street
Wilmington, MA 01887
Phone: (978) 988-9100
Fax (978) 988-5550
www.kentrontech.com
128M X 72 REGISTERED SDRAM DIMM
SDRAM FEMMA MODULE
1GByte (128M x 72) SDRAM
Registered 168 Pin DIMM


General Description:
This memory module is a high performance 1024 Megabyte Registered synchronous dynamic
RAM module organized as 128M x 72 in a 168 pin Dual In-Line Memory Module (DIMM)
package. The module utilizes thirty-six (36) 16Mx4X4 SDRAM devices in a TSOP II 400 mil
package. A 256 Byte Serial EEPROM contains the module configuration information. The
EEPROM can be configured to a customer's specifications.
These modules offer substantial advances in DRAM operating performance, including the ability
to synchronously burst data at a high rate with automatic column-address generation, interleave
between internal banks in order to hide precharge time, and the capability to randomly change
column address on each clock cycle during burst.

Features:
High density: 1024 MB (128M x 72)
Cycle time: 10ns (100 MHz)
JEDEC Standard 168 Pin Registered SDRAM DIMM
Single power supply of 3.3V 10%
Serial Presence Detect
LVTTL Compatible I/O and Clock
Registered Control Lines
On-board PLL Clock Driver
Program Burst Lengths and CAS Latency
Auto Precharge and Auto Refresh Modes
Programmable Burst Type, Burst Length and CAS Latency
Internal Pipeline Operation
Fully Synchronous all signals registered on positive edge of system clock
Module Standard: FEMMA
TM
Packaging Technology (Patented)
Package Height: 1.50 inches



Kentron Technologies, Inc. (978) 988-9100 Page 2
Rev. 03/02
128M X 72 REGISTERED SDRAM DIMM
Operating Features:
The SDRAM DIMM utilizes a clock input for the synchronization. Each operation of the SDRAM
is determined by commands and all operations are referenced to a positive clock edge. CAS
Latency defines the delay from when a Read Command is registered on a rising clock edge to
when the data from the Read Command becomes available at the outputs. The CAS latency is
expressed in terms of clock cycles. This specific DIMM supports 3 and 2 clock cycles.
The burst mode is a very high-speed access mode utilizing an internal column address
generator. Once a column address for the first access is set, following addresses are
automatically generated by the internal column address counter.
All control and address signals are registered on-board and hence delayed by one cycle in
arriving at the SDRAMs. The clock signal is distributed to all SDRAMs via a zero delay PLL
driver. Note that the PLL must be given enough clock cycles to stabilize before any operation
can be given (minimum stabilization time equal to 1 ms).
Absolute Maximum Ratings*:
Item
Symbol
Rating
Unit
Supply voltage (V
CC
Relative to V
SS
)
V
CC
-1.0 to +4.6
V
Input/Output Voltage
V
I/O
-1.0 to +4.6
V
Operating temperature
T
opr
0 to +70
C
Storage temperature
T
stg
-55 to +125
C
Short circuit output current
I
out
50
mA
* Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation
should be restricted to the conditions as detailed in the sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions:
(Voltage referenced to V
CC
. T
A
= 0 to 70 C)
Item
Symbol
Min.
Typ.
Max.
Unit
Supply voltage
V
CC
3.0
3.3
3.6
V
Input high voltage
V
IH
2.0
-
V
CC
+0.3
V
Input low voltage
V
IL
-0.3
-
0.8
V
Operating Temperature
T
A
0
+25
+70
C
Capacitance:
(TA=25C, Vcc=3.3V0.3V)
Parameter
Symbol
Max.
Unit
Input capacitance (Address/ WE, CKE0, /CAS, /CS0~/CS3)
C
IN
10
pF
Input capacitance (/DQMBs)
C
IN
5
pF
Input capacitance (CK0)
C
IN
4
pF
Input capacitance (/RAS)
C
IN
20
pF
Input/Output capacitance (DQ0~DQ63, CB0~CB7)
C
I/O
13
pF
Kentron Technologies, Inc. (978) 988-9100 Page 3
Rev. 03/02
128M X 72 REGISTERED SDRAM DIMM

Pin Names:
CK0-CK3
Clock Inputs
DQ0-DQ63
Data Inputs/Outputs
CKE0, CKE1
Clock Enables
CB0-CB7
ECC Data Input/Output
RAS*
Row Address Strobe
DQMB0-DQMB7
Data Mask Enables
CAS*
Column Address Strobe
V
CC
Power supply
WE*
Write Enable
V
SS
Ground
CS0*-CS3*
Chip Select
SCL
Serial Clock
A0-A11
Address Inputs
SDA
Serial Data Input/Output
BA0, BA1
SDRAM Bank Select
SA0-SA2
Decode Input
REGE
Register Enable
WP
Write Protect for SPD
NC or DU
No Connect
REGE is the Register Enable pin which permits the DIMM to operate in buffered mode (inputs re-driven asynchronously) and "registered" mode (signals
re-driven to SDRAMs when clock rises, and held valid until next rising clock). To conform to this specification, motherboards must pull this pin to a high
state ("registered mode").
SDRAM DIMM Pinout:
No.
Designation
No.
Designation
No.
Designation
No.
Designation
1
V
SS
43
V
SS
85
Vss
127
Vss
2
DQ0
44
DU
86
DQ32
128
CKE0
3
DQ1
45
CS2
87
DQ33
129
CS3*
4
DQ2
46
DQMB2
88
DQ34
130
DQMB6
5
DQ3
47
DQMB3
89
DQ35
131
DQMB7
6
V
CC
48
DU
90
Vcc
132
A13
7
DQ4
49
V
CC
91
DQ36
133
Vcc
8
DQ5
50
NC
92
DQ37
134
NC
9
DQ6
51
NC
93
DQ38
135
NC
10
DQ7
52
CB2
94
DQ39
136
CB6
11
DQ8
53
CB3
95
DQ40
137
CB7
12
V
SS
54
Vss
96
Vss
138
Vss
13
DQ9
55
DQ16
97
DQ41
139
DQ48
14
DQ10
56
DQ17
98
DQ42
140
DQ49
15
DQ11
57
DQ18
99
DQ43
141
DQ50
16
DQ12
58
DQ19
100
DQ44
142
DQ51
17
DQ13
59
Vcc
101
DQ45
143
Vcc
18
V
CC
60
DQ20
102
Vcc
144
DQ52
19
DQ14
61
NC
103
DQ46
145
NC
20
DQ15
62
NC
104
DQ47
146
NC
21
CB0
63
CKE1
105
CB4
147
REGE
22
CB1
64
Vss
106
CB5
148
Vss
23
V
SS
65
DQ21
107
Vss
149
DQ53
24
NC
66
DQ22
108
NC
150
DQ54
25
NC
67
DQ23
109
NC
151
DQ55
26
V
CC
68
Vss
110
Vcc
152
Vss
27
WE*
69
DQ24
111
CAS*
153
DQ56
28
DQMB0
70
DQ25
112
DQMB4
154
DQ57
29
DQMB1
71
DQ26
113
DQMB5
155
DQ58
30
S0*
72
DQ27
114
CS1*
156
DQ59
31
DU
73
Vcc
115
RAS*
157
Vcc
32
V
SS
74
DQ28
116
Vss
158
DQ60
33
A0
75
DQ29
117
A1
159
DQ61
34
A2
76
DQ30
118
A3
160
DQ62
35
A4
77
DQ31
119
A5
161
DQ63
36
A6
78
Vss
120
A7
162
Vss
37
A8
79
CK2
121
A9
163
CK3
38
A10/AP
80
NC
122
BA0
164
NC
39
BA1
81
WP
123
A11
165
SA0
40
V
CC
82
SDA
124
Vcc
166
SA1
41
V
CC
83
SCL
125
CK1
167
SA2
42
CK0
84
Vcc
126
A12
168
Vcc
Kentron Technologies, Inc. (978) 988-9100 Page 4
Rev. 03/02
128M X 72 REGISTERED SDRAM DIMM
DC Characteristics:
(V
CC
= 3.3V.3V, V
SS
=0V, T
A
=0 to + 70C)
Parameter
1
Symbol
100MHz
Max.
Unit
Operating current
(No Burst, T
CK
=min. T
RC
=min. Single Bank)
I
CC1
2750
mA
Precharge Standby Current
(CKE=V
IL
, T
CK
= min. All banks idle)
(CKE=V
IH
, T
CK
= min. All banks idle)
I
CC2
38
546
mA
Active Standby Current
(CKE=V
IL
, T
CK
= min. One bank active)
(CKE=V
IH
, T
CK
= min. One bank active)
I
CC3
36
360
mA
Burst Mode Current (t
CK
=min.)
I
CC4
2360
mA
Refresh Current (per DIMM bank)
(t
CK
=min., t
RC
=min., t
RRD
=min., Auto Refresh)
I
CC5
3700
mA
Self Refresh Current (all DIMM banks, CKE=V
IL
)
I
CC6
36
mA
AC Electrical Characteristics:
(TA=0C to +70C, V
CC
=3.3V0.3V, V
SS
=0V)
Parameter
Symbol
100MHz
Min.
100MHz
Max.
Unit
Row to row active delay
t
RRD
20
ns
RAS to CAS delay
t
RCD
20
ns
Row precharge time
t
RP
20
ns
Row active time
t
RAS
50
120K
ns
Row cycle time
t
RC
70
ns
Last data in to row precharge
t
RDL
10
ns
Last data in to new Col. Address delay
t
CDL
1
clk
Last data in to burst stop
t
BDL
1
clk
Column address to column address delay
t
CCD
1
clk
Number of valid output data (CL=3)
(CL=2)

2
1
Ea
Clock Cycle Time (CL=3)
(CL=2)
t
CC
10
10
2
ns
Clock to Valid Output Delay (CL=3)
(CL=2)
t
AC
6
6
ns
Output Data Hold Time (CL=3)
(CL=2)
t
OH
3
3
ns
Clock High Pulse Width
t
CH
3
ns
Clock Low Pulse Width
t
CL
3
ns
Input Setup Time
t
SS
2
ns
Input Hold Time
t
SH
1
ns
Clock to Output in Low-Z
T
SLZ
1
ns
Clock to Output in High-Z
t
SHZ
6
ns
1
Typical Actual values run lower than Max Spec'ed Values.
2
Available for select SDRAM devices/part numbers.
Kentron Technologies, Inc. (978) 988-9100 Page 5
Rev. 03/02
128M X 72 REGISTERED SDRAM DIMM
Functional Block Diagram:
RS1
RDQMB0
RDQMB4
DQ0
IO0
DQM
CS
IO0
DQM
CS
DQ32
IO0
DQM
CS
IO0
DQM
CS
DQ1
IO1
IO1
DQ33
IO1
IO1
DQ2
IO2
IO2
DQ34
IO2
IO2
DQ3
IO3
IO3
DQ35
IO3
IO3
DQ4
IO0
DQM
CS
IO0
DQM
CS
DQ36
IO0
DQM
CS
IO0
DQM
CS
DQ5
IO1
IO1
DQ37
IO1
IO1
DQ6
IO2
IO2
DQ38
IO2
IO2
DQ7
IO3
IO3
DQ39
IO3
IO3
RDQMB1
RDQMB5
DQ8
IO0
DQM
CS
IO0
DQM
CS
DQ40
IO0
DQM
CS
IO0
DQM
CS
DQ9
IO1
IO1
DQ41
IO1
IO1
DQ10
IO2
IO2
DQ42
IO2
IO2
DQ11
IO3
IO3
DQ43
IO3
IO3
DQ12
IO0
DQM
CS
IO0
DQM
CS
DQ44
IO0
DQM
CS
IO0
DQM
CS
DQ13
IO1
IO1
DQ45
IO1
IO1
DQ14
IO2
IO2
DQ46
IO2
IO2
DQ15
IO3
IO3
DQ47
IO3
IO3
CB0
IO0
DQM
CS
IO0
DQM
CS
CB4
IO0
DQM
CS
IO0
DQM
CS
CB1
IO1
IO1
CB5
IO1
IO1
CB2
IO2
IO2
CB6
IO2
IO2
CB3
IO3
IO3
CB7
IO3
IO3
RS2
RS3
RDQMB2
RDQMB6
DQ16
IO0
DQM
CS
IO0
DQM
CS
DQ48
IO0
DQM
CS
IO0
DQM
CS
DQ17
IO1
IO1
DQ49
IO1
IO1
DQ18
IO2
IO2
DQ50
IO2
IO2
DQ19
IO3
IO3
DQ51
IO3
IO3
DQ20
IO0
DQM
CS
IO0
DQM
CS
DQ52
IO0
DQM
CS
IO0
DQM
CS
DQ21
IO1
IO1
DQ53
IO1
IO1
DQ22
IO2
IO2
DQ54
IO2
IO2
DQ23
IO3
IO3
DQ55
IO3
IO3
RDQMB3
RDQMB7
DQ24
IO0
DQM
CS
IO0
DQM
CS
DQ56
IO0
DQM
CS
IO0
DQM
CS
DQ25
IO1
IO1
DQ57
IO1
IO1
DQ26
IO2
IO2
DQ58
IO2
IO2
DQ27
IO3
IO3
DQ59
IO3
IO3
DQ28
IO0
DQM
CS
IO0
DQM
CS
DQ60
IO0
DQM
CS
IO0
DQM
CS
DQ29
IO1
IO1
DQ61
IO1
IO1
DQ30
IO2
IO2
DQ62
IO2
IO2
DQ31
IO3
IO3
DQ63
IO3
IO3
All resistor values are 10 ohms.
=10K
S0-S3
R
RS0-RS3
CK0
PLL
DQMB0-DQMB7
E
RDQMB0-RDQMB7
CK1,CK2,CK3
Termination
BA0,BA1
G
RBA0 BAO,RBA1
BA1:SDRAMSD0-D35
A0-A12
I
RA0-RA11 A0-A12:SDRAMS D0-D35
SCL
SDA
RAS
S
RRAS RAS:SDRAMS D0-D35
WP
A0
A1
A2
CAS
T
RCAS CAS:SDRAMS D0-D35
CKE0
E
RCKE0 CKE:SDRAMS D0-D35
SA0 SA1 SA2
WE
R
RWE WE:SDRAMS D0-D35
VDD
V
DD
D0-D35
REGE
All Driver outputs go thru 10ohm Termination.
V
SS
D0-D35
PLL CLK
SERIAL PD
D8
D26
D17
D35
D7
D25
D16
D34
D6
D24
D15
D33
D5
D23
D14
D32
D11
D29
D12
D30
D9
D27
D10
D28
D18
D19
D20
D21
D0
D1
D2
D3
D4
D22
D13
D31
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R1
R
WP
R1
Kentron Technologies, Inc. (978) 988-9100 Page 6
Rev. 03/02
128M X 72 REGISTERED SDRAM DIMM
Part Numbers:
Part number*
Configuration
Clock Speed
Fold
KT12872SRN0R-XXV3
128M x 72
10ns (100 MHz)
Reverse

* The "XX" designation relates to the SDRAM manufacturer's device used in production.
Please contact Kentron Technologies for more information.

Package Description:




Kentron Technologies, Inc. (978) 988-9100 Page 7
Rev. 03/02
128M X 72 REGISTERED SDRAM DIMM
The information set forth herein is considered proprietary information owned by Kentron
Technologies, Inc.

The information may contain preliminary information and is subject to change by Kentron
Technologies, Inc. without notice. Kentron Technologies assumes no responsibility or liability
for any use of the information contained herein. The products described in this document are
not intended for use in implantation or direct life support applications where malfunction may
result in direct physical harm or injury to persons.
NO WARRANTIES OF ANY KIND, INCLUDING NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR PARTICULAR PURPOSE, ARE
OFFERED IN THIS DOCUMENT.
Kentron Technologies, Inc. All Rights Reserved
FEMMA
TM
is a Registered Trademark of Kentron Technologies, Inc.


For further information on this product, please contact:
Kentron Technologies, Inc.
155 West Street
Wilmington, MA 01887
Phone: 978/988-9100
Fax 978/988-5550
http://www.kentrontech.com
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