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Datasheet: X1205S8IT1 (Intersil Corporation)

2-Wire RTC Real Time Clock/Calendar

 

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Intersil Corporation
1
FN8097.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X1205
2-WireTM RTC Real Time Clock/Calendar
FEATURES
Real Time Clock/Calendar
--Tracks time in Hours, Minutes, and Seconds
--Day of the Week, Day, Month, and Year
2 Polled Alarms (Non-volatile)
--Settable on the Second, Minute, Hour, Day of
the Week, Day, or Month
--Repeat Mode (periodic interrupts)
Oscillator Compensation on chip
--Internal feedback resistor and compensation
capacitors
--64 position Digitally Controlled Trim Capacitor
--6 digital frequency adjustment settings to
30ppm
Battery Switch or Super Cap Input
2-WireTM Interface interoperable with I2C*
--400kHz data transfer rate
Low Power CMOS
--1.25A Operating Current (Typical)
Small Package Options
--8-Lead SOIC and 8-Lead TSSOP
Repetitive Alarms
Temperature Compensation
Pb-Free Plus Anneal Available (RoHS Compliant)
APPLICATIONS
Utility Meters
HVAC Equipment
Audio/Video Components
Set Top Box/Television
Modems
Network Routers, Hubs, Switches, Bridges
Cellular Infrastructure Equipment
Fixed Broadband Wireless Equipment
Pagers/PDA
POS Equipment
Test Meters/Fixtures
Office Automation (Copiers, Fax)
Home Appliances
Computer Products
Other Industrial/Medical/Automotive
DESCRIPTION
The X1205 device is a Real Time Clock with
clock/calendar, two polled alarms, oscillator
compensation, and battery backup switch.
The oscillator uses an external, low-cost 32.768kHz
crystal. All compensation and trim components are
integrated on the chip. This eliminates several external
discrete components and a trim capacitor, saving
board area and component cost.
The Real-Time Clock keeps track of time with
separate registers for Hours, Minutes, and Seconds.
The Calendar has separate registers for Date, Month,
Year and Day-of-week. The calendar is correct
through 2099, with automatic leap year correction.
BLOCK DIAGRAM
X1
X2
Oscillator
Frequency
Timer
Logic
Divider
Calendar
8
32.768kHz
Control
Registers
1Hz
Time
Keeping
Registers
Alarm Regs
Compare
Mask
IRQ
Control
Decode
Logic
Alarm
(EEPROM)
(EEPROM)
SCL
SDA
Serial
Interface
Decoder
Interrupt Enable
Registers
Status
(SRAM)
Alarm
Alarm
(SRAM)
OSC
Compensation
Data Sheet
September 23, 2005
2
FN8097.2
September 23, 2005
PIN DESCRIPTIONS
PIN ASSIGNMENTS
NC = No internal connection
X1
X2
V
BACK
V
CC
IRQ
SCL
SDA
V
SS
1
2
3
4
7
8
6
5
8 Ld TSSOP
X1205
X1
X2
V
BACK
V
CC
IRQ
SCL
SDA
V
SS
1
2
3
4
7
8
6
5
8 Ld SOIC
Ordering Information
PART NUMBER
PART MARKING
V
CC
RANGE (V)
TEMP RANGE (C)
PACKAGE
X1205S8*
X1205
2.7 to 5.5
0 to 70
8 Ld SOIC (150 mil)
X1205S8Z* (Note)
X1205 Z
0 to 70
8 Ld SOIC (150 mil) (Pb Free)
X1205S8I*
X1205 I
-40 to 85
8 Ld SOIC (150 mil)
X1205S8IZ* (Note)
X1205 Z I
-40 to 85
8 Ld SOIC (150 mil) (Pb Free)
X1205V8*
1205
0 to 70
8 Ld TSSOP (4.4mm)
X1205V8Z* (Note)
1205 Z
0 to 70
8 Ld TSSOP (4.4mm) (Pb-free)
X1205V8I*
1205I
-40 to 85
8 Ld TSSOP (4.4mm)
X1205V8IZ* (Note)
1205I Z
-40 to 85
8 Ld TSSOP (4.4mm) (Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pin Number
Symbol
Brief Description
SOIC
TSSOP
1
3
X1
X1. The X1 pin is the input of an inverting amplifier and should be connected to one pin
of a 32.768kHz quartz crystal.
2
4
X2
X2. The X2 pin is the output of an inverting amplifier and should be connected to one pin
of a 32.768kHz quartz crystal.
3
5
IRQ
Interrupt Output IRQ. This is an interrupt signal output. This signal notifies a host proces-
sor that an alarm has occurred and requests action. It is an open drain active low output.
4
6
V
SS
V
SS
.
5
7
SDA
Serial Data (SDA). SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain or open
collector outputs.
6
8
SCL
Serial Clock (SCL). The SCL input is used to clock all data into and out of the device.
7
1
V
BACK
V
BACK
. This input provides a backup supply voltage to the device. V
BACK
supplies power
to the device in the event the V
CC
supply fails. This pin can be connected to a battery, a
Supercap or tied to ground if not used.
8
2
V
CC
V
CC
.
X1205
3
FN8097.2
September 23, 2005
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ................... -65C to +135C
Storage Temperature ........................ -65C to +150C
Voltage on V
CC
, V
BACK
and IRQ
pin (respect to ground) ............................-0.5V to 7.0V
Voltage on SCL, SDA, X1 and X2
pin (respect to ground) ............... -0.5V to 7.0V or 0.5V
above V
CC
or V
BACK
(whichever is higher)
DC Output Current .............................................. 5 mA
Lead Temperature (Soldering, 10 sec).............. 300C
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute max-
imum rating conditions for extended periods may
affect device reliability.
DC OPERATING CHARACTERISTICS (Temperature = -40C to +85C, unless otherwise stated.)
OPERATING CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Notes
V
CC
Main Power Supply
2.7
5.5
V
V
BACK
Backup Power Supply
1.8
5.5
V
V
CB
Switch to Backup Supply
V
BACK
-0.2
V
BACK
-0.1
V
V
BC
Switch to Main Supply
V
BACK
V
BACK
+0.2
V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Notes
I
CC1
Read Active Supply
Current
V
CC
= 2.7V
400
A
1, 5, 7, 14
V
CC
= 5.0V
800
A
I
CC2
Program Supply Current
(nonvolatile)
V
CC
= 2.7V
2.5
mA
2, 5, 7, 14
V
CC
= 5.0V
3.0
mA
I
CC3
Main Timekeeping
Current
V
CC
= 2.7V
10
A
3, 7, 8, 14, 15
V
CC
= 5.0V
20
A
I
BACK
Timekeeping Current
V
BACK
= 1.8V
1.25
A
3, 6, 9, 14, 15
"See Perfor-
mance Data"
V
BACK
= 3.3V
1.5
A
I
LI
Input Leakage Current
10
A
10
I
LO
Output Leakage Current
10
A
10
V
IL
Input LOW Voltage
-0.5
V
CC
x 0.2 or
V
BACK
x 0.2
V
13
V
IH
Input HIGH Voltage
V
CC
x 0.7 or
V
BACK
x 0.7
V
CC
+ 0.5 or
V
BACK
+ 0.5
V
13
V
HYS
Schmitt Trigger Input
Hysteresis
V
CC
related level
.05 x V
CC
or
.05 x V
BACK
V
13
V
OL
Output LOW Voltage for
SDA/IRQ
V
CC
= 2.7V
0.4
V
11
V
CC
= 5.5V
0.4
X1205
4
FN8097.2
September 23, 2005
Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave Address
Byte are incorrect or until 200nS after a stop ending a read or write operation.
(2) The device enters the Program state 200nS after a stop ending a write operation and continues for t
WC
.
(3) The device goes into the Timekeeping state 200nS after any stop, except those that initiate a nonvolatile write cycle; t
WC
after a stop
that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave
Address Byte.
(4) For reference only and not tested.
(5) V
IL
= V
CC
x 0.1, V
IH
= V
CC
x 0.9, f
SCL
= 400KHz
(6) V
CC
= 0V
(7) V
BACK
= 0V
(8) V
SDA
= V
SCL
=V
CC
, Others = GND or V
CC
(9) V
SDA
=V
SCL
=V
BACK
, Others = GND or V
BACK
(10)V
SDA
= GND or V
CC
, V
SCL
= GND or V
CC
(11)I
OL
= 3.0mA at 5V, 1mA at 2.7V
(13)Threshold voltages based on the higher of Vcc or Vback.
(14)Using recommended crystal and oscillator network applied to X1 and X2 (25C).
(15)Typical values are for T
A
= 25C
Capacitance T
A
= 25C, f = 1.0 MHz, V
CC
= 5V
Notes: (1) This parameter is not 100% tested.
(2) The input capacitance between x1 and x2 pins can be varied between 5pF and 19.75pF by using analog trimming registers
AC CHARACTERISTICS
AC Test Conditions
Figure 1. Standard Output Load for testing the device with V
CC
= 5.0V
Symbol
Parameter
Max.
Units
Test Conditions
C
OUT
(1)
Output Capacitance (SDA, IRQ)
10
pF
V
OUT
= 0V
C
IN
(1)
Input Capacitance (SCL)
10
pF
V
IN
= 0V
Input Pulse Levels
V
CC
x 0.1 to V
CC
x 0.9
Input Rise and Fall Times
10ns
Input and Output Timing
Levels
V
CC
x 0.5
Output Load
Standard Output Load
SDA
1533
100pF
5.0V
For V
OL
= 0.4V
and I
OL
= 3 mA
Equivalent AC Output Load Circuit for V
CC
= 5V
1316
5.0V
IRQ
100pF
806
X1205
5
FN8097.2
September 23, 2005
AC Specifications (T
A
= -40C to +85C, VCC = +2.7V to +5.5V, unless otherwise specified.)
Notes: (1) This parameter is not 100% tested.
(2) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
Symbol
Parameter
Min.
Max. Units
f
SCL
SCL Clock Frequency
400
kHz
t
IN
Pulse width Suppression Time at inputs
50
(1)
ns
t
AA
SCL LOW to SDA Data Out Valid
0.9
s
t
BUF
Time the bus must be free before a new transmission can start
1.3
s
t
LOW
Clock LOW Time
1.3
s
t
HIGH
Clock HIGH Time
0.6
s
t
SU:STA
Start Condition Setup Time
0.6
s
t
HD:STA
Start Condition Hold Time
0.6
s
t
SU:DAT
Data In Setup Time
100
ns
t
HD:DAT
Data In Hold Time
0
s
t
SU:STO
Stop Condition Setup Time
0.6
s
t
DH
Data Output Hold Time
50
ns
t
R
SDA and SCL Rise Time
20 +.1Cb
(1)(2)
300
ns
t
F
SDA and SCL Fall Time
20 +.1Cb
(1)(2)
300
ns
Cb
Capacitive load for each bus line
400
pF
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA IN
SDA
OUT
t
F
t
LOW
t
BUF
t
AA
t
R
X1205
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