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Datasheet: IA59032-CPGA100I (InnovASIC, Inc.)

32-Bit High Speed Microprocessor Slice

 

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InnovASIC, Inc.
Page 1 of 17
IA59032
Data Sheet
32-Bit High Speed Microprocessor Slice
Copyright
2000
innov
ASIC
[_________The End of Obsolescence
TM
FEATURES
Eight CMOS 2901 Type Devices in a Single Package
32 x 32 Dual Port RAM
High Speed Operation
-
23MHz Read-Modify-Write Cycle
Fully Firmware Compatible with the 2901
The IA59032 is a "plug-and-play" drop-in replacement for the original WSITM WS59032. This
replacement IC has been developed using innovASIC's MILES
TM
, or Managed IC Lifetime
Extension System, cloning technology. This technology produces replacement ICs far more complex
than "emulation" while ensuring they are compatible with the original IC. MILES
TM
captures the
design of a clone so it can be produced even as silicon technology advances. MILES
TM
also verifies
the clone against the original IC so that even the "undocumented features" are duplicated. This data
sheet documents all necessary engineering information about the IA59032 including functional and
I/O descriptions, electrical characteristics, and applicable timing.
WSI is a trademark of Waferscale Integration, Inc.
100 PIN PGA PACKAGE:
11
12
13
TOP VIEW
BOTTOM VIEW
N M L K J H G F E D C B A
N M L K J H G F E D C B A
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A B C D E F G H J K L M N
A B C D E F G H J K L M N
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Page 2 of 17
IA59032
Data Sheet
32-Bit High Speed Microprocessor Slice
Copyright
2000
innov
ASIC
[_________The End of Obsolescence
TM
PIN DESIGNATOR:
VCC
N1
B3
N2
D23
B1
Y7
K12
VCC
A1
B4
M3
D24
B2
Y8
K13
GND
N7
D0
N6
D25
B3
Y9
J12
GND
G13
D1
M6
D26
A2
Y10
J13
GND
A12
D2
L6
D27
A3
Y11
H11
GND
C6
D3
N5
D28
B4
Y12
H12
RAM0
M7
D4
M5
D29
A4
Y13
H13
RAM31
B6
D5
N4
D30
B5
Y14
G12
Q0
L7
D6
M4
D31
A5
Y15
G11
Q31
A6
D7
N3
I0
N8
Y16
F13
CLK
A7
D8
H3
I1
M8
Y17
F12
CIN
N13
D9
H2
I2
L8
Y18
F11
CN-32
A9
D10
H1
I3
N9
Y19
E13
OVR
C8
D11
G1
I4
M9
Y20
E12
F-0
C13
D12
G3
I5
N10
Y21
D13
F31
B8
D13
G2
I6
A8
Y22
D12
OEN
M12
D14
F1
I7
B7
Y23
B13
A0
J1
D15
F2
I8
C7
Y24
C12
A1
J2
D16
F3
Y0
M10
Y25
A13
A2
K1
D17
E1
Y1
N11
Y26
B12
A3
K2
D18
E2
Y2
N12
Y27
B11
A4
L1
D19
D1
Y3
M11
Y28
A11
B0
M1
D20
D2
Y4
M13
Y29
B10
B1
L2
D21
C1
Y5
L12
Y30
A10
B2
M2
D22
C2
Y6
L13
Y31
B9
PIN
NAME
PGA
GRID #
PIN
NAME
PGA
GRID #
PIN
NAME
PGA
GRID #
PIN
NAME
PGA
GRID #
Page 3 of 17
IA59032
Data Sheet
32-Bit High Speed Microprocessor Slice
Copyright
2000
innov
ASIC
[_________The End of Obsolescence
TM
The IA59032 is a 32-bit high-speed microprocessor that combines the functions of eight 2901 4-bit
slice processors and distributed look-ahead carry generation on a single high performance CMOS
device. The IA59032 dual port RAM is 32-bits wide and 32 words deep. This architecture provides
grater flexibility and eases the task of generating new microcode while maintaining 100%
compatibility with existing 2901 based microcode.
BLOCK DIAGRAM
Figure 1
ALU SOURCE
DESTINATION
CONTROL
ALU FUNCTION
0
8
7
6
5
4
3
2
1
MICROINSTRUCTION DECODE
I(8:0)
INSTRUCTION BUS
Page 4 of 17
IA59032
Data Sheet
32-Bit High Speed Microprocessor Slice
Copyright
2000
innov
ASIC
[_________The End of Obsolescence
TM
RAM SHIFT
32X32 2 PORT RAM
ALU SOURCE MUX
Q-SHIFT
Q REGISTER
OUTPUT DATA MUX
8 FUNCTION 32-BIT ALU
LOGIC
"0"
A
F
Y(31:0)
OEn
Cn
D(31:0)
B(READ/WRITE)
ADDRESS
A(READ)
ADDRESS
CP
FZERO
F31
OVR
Cn32
F
A
Q
0
B
S
R
A
OUT
B
B
OUT
WE
Q31
Q0
F
RAM0
RAM31
FIGURE 1 (CONT):
Page 5 of 17
IA59032
Data Sheet
32-Bit High Speed Microprocessor Slice
Copyright
2000
innov
ASIC
[_________The End of Obsolescence
TM
A detailed block diagram for the IA59032 is shown in
Figure 1
. The two key elements in the block diagram
are the 32 word by 32-bit 2-port RAM and the high-speed ALU.
Data in any of the 32 words of the RAM can be read from the A-port of the RAM as controlled by the 4-bit
A address field input. Likewise, data in any of the 32 words of the RAM as defined by the B address field
input can be simultaneously read from the B-port of the RAM. The same code can be applied to the A select
field and B select field in which case the identical file data will appear at both the RAM A-port and B-port
outputs simultaneously.
When enabled by the RAM write enable (CP low), new data is always written into the file (word) defined by
the B address field of the RAM. The RAM data input field is driven by a 3-input mux. This configuration is
used to shift the ALU output data F if desired. This three-input mux scheme allows the data to be shifted up
one bit position, shifted down one bit position, or not shifted in either direction.
The high speed ALU can perform three binary arithmetic and five logic operations on the two 32-bit input
words R and S. The R input field is driven from a 2-input mux, while the S input field is driven by a 3-input
mux. Both muxes also have an inhibit capability; that is, no data is passed. This is equivalent to a "zero"
source operand.
Referring to
Figure 1
, the ALU R-input mux has the RAM A-port and the direct data inputs (D) connected as
inputs. Likewise, the ALU S-input mux has the RAM A-port, B-port, and the Q register connected as inputs.
This muxing scheme provides the capability of selecting various pairs of the A, B, D, Q, and zero inputs as
source operands to the ALU. These five inputs, when taken two at a time, result in ten possible
combinations of source operand pairs. The I(2:0) inputs are the microinstruction inputs used to select the
ALU source operands.
The two source operands not fully described as yet are the D input and the Q input. The D input is the 32-
bit wide direct data field input. This port is used to insert all data into the working registers inside the device.
Likewise, this input can be used in the ALU to modify any of the internal data files. The Q register is a
separate 32-bit file intended primarily for multiplication and division routines but it can also be used as an
accumulator or holding register for some applications.
The ALU itself is capable of performing three binary arithmetic and five logic functions. The I(5:3) inputs
are used to select the ALU function.
The ALU has three status-oriented outputs. These are F31, FZERO, and OVR. The F31 output is the most
significant (sign) bit of the ALU and can be used to determine positive or negative results without enabling
the three-state data outputs. F31 is non-inverted with respect to the sign bit output Y(31). The FZERO
output is used for zero detect. It is an open-collector output. FZERO is HIGH when all F outputs are
LOW. The overflow output (OVR) is used to flag arithmetic operations that exceed the available two's
complement number range. The OVR output is HIGH when overflow exists.
The ALU data output is routed to several destinations. It can be a data output of the device and it can also
be stored in the RAM or the Q register. Eight possible combinations of ALU destination functions are
available, as defined by the I(8:6) inputs.
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