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Datasheet: IA188EM-PTQ100I (InnovASIC, Inc.)

8-bit 5VDC Microcontroller

 

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InnovASIC, Inc.
innov
ASIC
Copyright
2003







IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
IA186EM/IA188EM
Data Sheet
8/16-BIT MICROCONTROLLERS As of Production Version -01
Copyright
2003 ENG21 1 030617-03 www.innovasic.com
innovASIC Customer Support:
The End of Obsolescence
Page 2 of 129 1.888.824.4184
Data Sheet Contents
FEATURES
.............................................................................................................................................3
Description
...............................................................................................................................................4
Bus Interface and Control
.................................................................................................................6
Peripheral Control and Registers
..................................................................................................6
Clock and Power Management
....................................................................................................50
System Clocks. .....................................................................................................................................50
Power-Save Mode. ...............................................................................................................................51
Initialization and Reset. ........................................................................................................................51
Reset Configuration Register. ..............................................................................................................51
Chip-Selects .........................................................................................................................................51
Chip-Select Timing ..............................................................................................................................51
Ready and Wait-State Programming ....................................................................................................52
Chip-Select Overlap .............................................................................................................................52
Upper Memory Chip Select..................................................................................................................53
Low Memory Chip Select ....................................................................................................................53
Midrange Memory Chip Selects ..........................................................................................................53
Peripheral Chip Selects ........................................................................................................................53
Refresh Control ....................................................................................................................................54
Interrupt Control...................................................................................................................................54
Timer Control.......................................................................................................................................56
Direct Memory Access (DMA) ............................................................................................................57
DMA Operation....................................................................................................................................57
Asynchronous Serial Port
...............................................................................................................59
Synchronous Serial Port
..................................................................................................................59
Programmable I/O (PIO)
.................................................................................................................60
Pin Descriptions
..................................................................................................................................61
Instruction Set Summary
(Key to abbreviations appears at the end of the table)...........................73
Absolute Maximum Ratings
.........................................................................................................89
DC Characteristics Over Commercial Operating Ranges
..............................................89
AC Characteristics Over Commercial Operating Ranges (At 40 MHz) ......................................................90
Waveforms
.............................................................................................................................................93
Physical Dimensions
...............................................................................................................124
Ordering Information
......................................................................................................................127
IA186EM-PQF100I................................................................................................................................127
IA186EM-PTQ100I ...............................................................................................................................127
IA188EM-PQF100I................................................................................................................................127
IA188EM-PTQ100I ...............................................................................................................................127
Cross Reference to OEM Part Numbers ....................................................................................................127
Errata ..........................................................................................................................................................128
IA186EM/IA188EM
Data Sheet
8/16-BIT MICROCONTROLLERS As of Production Version -01
Copyright
2003 ENG21 1 030617-03 www.innovasic.com
innovASIC Customer Support:
The End of Obsolescence
Page 3 of 129 1.888.824.4184
FEATURES
Pin-for-Pin compatible with AMD
Am186EM/188EM devices
All features are retained, including:
PLL allowing same crystal/system clock frequency
8086/8088 instruction set with additional 186 instruction set extensions
Programmable interrupt controller
Two DMA channels
Three 16-bit timers
Programmable chip select logic and wait-state generator
Dedicated watch dog timer
Two independent asynchronous serial ports (UARTs)
o
DMA capability
o
Hardware flow control
o
7, 8, or 9-bit data capability
Pulse Width Demodulator feature
Up to 32 programmable I/O pins (PIO)
Pseudo-static/dynamic RAM controller
Fully static CMOS design
40 MHz operation at industrial operating conditions
+5 VDC power supply
Available packages:
o
100-pin Thin Quad Flat Pack (TQFP)
o
100-pin Plastic Quad Flat Pack (PQFP)


The IA186EM/188EM is a form, fit, and function replacement for the original Advanced Micro Devices
Am186EM/188EM family of microcontrollers. InnovASIC produces replacement ICs using its MILES
T M
,
or Managed IC Lifetime Extensio n System, cloning technology. This technology produces replacement
ICs far more complex than "emulation" while ensuring they are compatible with the original IC.
MILES
T M
captures the design of a clone so it can be produced even as silicon technology advances.
MILES
T M
also verifies the clone against the original IC so that even the "undocumented features" are
duplicated.

This Data Sheet contains preliminary information for the IA186EM/188EM. The complete data sheet
which documents all necessary engineering information about the IA186EM/188EM including functional
and I/O descriptions, electrical characteristics, and applicable timing will be available when the device
nears completion.
IA186EM/IA188EM
Data Sheet
8/16-BIT MICROCONTROLLERS As of Production Version -01
Copyright
2003 ENG21 1 030617-03 www.innovasic.com
innovASIC Customer Support:
The End of Obsolescence
Page 4 of 129 1.888.824.4184
Description
The IA186EM/188EM family of microcontrollers replaces obsolete AMD
Am186EM/188EM devices,
allowing customers to retain existing board designs, software compilers/assemblers, and emulation tools,
thereby avoiding expensive redesign efforts.

The IA186EM/188EM microcontrollers are an upgrade for the 80C186/188 microcontroller designs, with
integrated peripherals to provide increased functionality and reduce system costs. The InnovASIC devices
are designed to satisfy requirements of embedded products designed for telecommunications, office
automation and storage, and industrial controls.

A block diagram of the IA186EM/188EM microcontroller is depicted in Figure 1. The IA186EM/188EM
microcontroller consists of the following functional blocks:
Bus Interface and Control
Peripheral Control and Registers
Chip Selects and Control
Programmable I/O
Clock and Power Management
Direct Memory Access (DMA)
Interrupt Controller
Timers
Asynchronous Serial Ports
Synchronous Serial Interface.
IA186EM/IA188EM
Data Sheet
8/16-BIT MICROCONTROLLERS As of Production Version -01
Copyright
2003 ENG21 1 030617-03 www.innovasic.com
innovASIC Customer Support:
The End of Obsolescence
Page 5 of 129 1.888.824.4184
Instruction Decode
and Execution
Clock and
Power Management
Direct Memory Access
Interrupt Controller
Timers
Asynchronous Serial
Port
Synchronous Serial Port
Bus Interface & Control
Chip Selects and Control
Peripheral Control and
Registers
Programmable I/O
ad[15:0]
ale
den_n
wr_n
wlb_n
whb_n
rd_n
uzi_n
s6/clkdiv2_n
hold
hlda
den_n/ds_n
dt/r_n
srdy
ardy
s2_n - s0_n
lcs_n/once0_n
ucs_n/once1_n
pcs5_n/a1
mcs3_n/rfsh_n
pcs6_n/a2
a[19:0]
mcs2_n - mcs0_n
pcs3_n - pcs0_n
pio[31:0]
clkouta
clkoutb
drq0
drq1
int4
int3/inta1_n/irq
int2/inta0_n
int1/select_n
int0
nmi
txd0
rxd0
cts0_n/enrx0_n
rts0_n/rtr0_n
sclk
sden0
sden1
sdata
tmrin0
tmrout0
tmrin1
tmrout1
V
cc
gnd
res_n


Figure 1. IA186/88EM Block Diagram
Note: See pin descriptions for pins that share other functions with PIO pins.
pwd, int5, int6, rts1_n/rtr1_n, and cts1_n/enrx1_n are multiplexed with int2_n/inta0_n, drq0_n, drq0_n,
pcs3_n, and pcs2_n respectively.
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