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Datasheet: IA16450 (InnovASIC, Inc.)

Universal Asynchronous Receiver/transmitter

 

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InnovASIC, Inc.
Page 1 of 10
IA16450
Preliminary Data Sheet
Universal Asynchronous Receiver/Transmitter
Copyright
1999, InnovASIC Inc.
Customer Specific IC Solutions
FEATURES
Form, Fit, and Function Compatible with the National
NS16450
Packaging options available: 40 Pin Plastic or 44 Pin Plastic Leaded Chip
Carrier
Programmable Word Length, Stop Bits, and Parity
Full Duplex Operation
Programmable Baud Rate Generator
-
Division of any input clock by 1 to (2
16
1)
-
Generates Internal 16 x clock
Programmable Serial-Interface
-
5-, 6-, 7- or 8-bit characters
-
Even, Odd, or No-Parity Bit Generation and Detection
-
1-, 1 -, or 2-Stop Bit Generation
-
Baud Generation of DC to 56k
Prioritized Interrupt Control
Internal Diagnostic/Loopback Capabilities
The IA16450 uses innov
ASIC
's innovative new f
3
Program to provide industry with parts that
other vendors have declared obsolete. By specifying parts through this program a customer is
assured of never having a component become obsolete again. This advanced information sheet
assumes the original part has been designed in, and so provides a summary of capabilities only. For
new designs contact innov
ASIC
for more detailed information.
National is a copyright trademark of National Semiconductor Corporation
Package Pinout
44 Pin LCC
IA16450
(12)
N. C.
(7)
D5
(8)
D6
(9)
D7
(10)
RCLK
(11)
SIN
(13)
SOUT
(14)
CS0
(15)
CS1
(16)
CS2_n
(17)
BAUDOUT_n
MR
INTR
N. C.
OUT2_n
DTR_n
OUT1_n
WR_n
XIN
XOUT
(6)
(5)
(4)
(3)
(2)
(1)
(44)
(43)
(42)
DCD_n
(41)
DSR_n
(40)
CTS_n
D3
D4
(34)
(39)
(38)
(37)
(36)
(35)
(33)
(32)
(31)
(30)
(29)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
VCC
RI_n
D0
N. C.
D2
D1
VSS
WR
RD_n
N. C.
DDIS
RD
ADS_n
CSOUT
A2
A1
A0
N. C.
RTS_n
(6)
(1)
(2)
(3)
(4)
(5)
(7)
(8)
(9)
RCLK
(10)
SIN
(11)
SOUT
(12)
CS0
(13)
CS1
(14)
40 Pin DIP
IA16450
RTS_n
OUT2_n
INTR
N. C.
(20)
VSS
(15)
BAUDOUT_n
(16)
XIN
(17)
XOUT
(18)
WR_n
(19)
WR
(21)
(22)
(23)
(24)
RD
RD_n
(40)
(39)
(38)
(37)
(36)
(35)
(34)
(33)
(32)
(31)
(30)
(29)
(28)
(27)
(26)
(25)
CS2_n
CSOUT
DDIS
A2
ADS_n
A0
A1
OUT1_n
DTR_n
CTS_n
MR
DCD_n
DSR_n
VCC
RI_n
D5
D0
D1
D2
D3
D4
D6
D7
Page 2 of 10
IA16450
Preliminary Data Sheet
Universal Asynchronous Receiver/Transmitter
Copyright
1999, InnovASIC Inc.
Customer Specific IC Solutions
The IA16450 is a form, fit and function compatible part to the National NS16450 Univeral
Asynchronous Receiver/Transmitter. The IA16450 function receives and transmits data in a variety
of configurations including 5, 6, 7 or 8 bit data words, odd, even or no parity, and 1, 1.5, and 2 stop
bits. This megafunction includes an internal Baud Rate Generator and Interrupt Control. A block
diagram is shown in Figure 1.
Functional Block Diagram
Figure 1
DATA BUS
BUFFER
RECEIVER
BUFFER
REGISTER
LINE CONTROL
REGISTER
DIVISOR LATCH
(LSB)
DIVISOR LATCH
(MSB)
LINE STATUS
REGISTER
TRANSMITTER
HOLDING
REGISTER
MODEM
CONTROL
REGISTER
MODEM STATUS
REGISTER
INTERRUPT
ENABLE
REGISTER
INTERRUPT ID
REGISTER
INTERNAL DATA
BUS
RECEIVER
SHIFT
REGISTER
RECEIVER
TIMING
&
CONTROL
TRANSMITTER
TIMING
&
CONTROL
TRANSMITTER
SHIFT
REGISTER
INTERRUPT
CONTROL
LOGIC
MODEM
CONTROL
LOGIC
BAUD
GENERATOR
SIN
RCLK
BAUDOUT_n
SOUT
RTS_n
CTS_n
DTR_n
DSR_n
DCD_n
RI
OUT1_n
OUT2_n
INTR
DECODE
AND
CONTROL
LOGIC
A0
A1
A2
CS0
CS1
CS2_n
ADS_n
MR
RD
RD_n
WR
WR_n
DDIS
CSOUT
XIN
XOUT
D7:D0
Page 3 of 10
IA16450
Preliminary Data Sheet
Universal Asynchronous Receiver/Transmitter
Copyright
1999, InnovASIC Inc.
Customer Specific IC Solutions
I/O Signal Description
Table 1 below describes the I/O characteristics for each signal on the IC. The signal names
correspond to the signal names on the pinout diagrams provided. Table 2 refers to the address
register map. Table 3 refers to the Preliminary A. C. Characteristics. Figure 2 illustrates the
Preliminary Timing Waveforms for this device. Environmental/Qualification Levels are listed in
Table 4.
Table 1
Name
Type
Description
MR
I
Master Reset - Active high - Clears all registers (except the
receiver buffer, transmitter holding and divisor latches) to their
initial state. Resets internal control logic to its initial state
A(2:0)
I
Register Address - Active high - This bus selects one of the
internal UART registers (refer to table 1). Note the state of the
divisor latch access bit (DLAB - the msb of the line control
register) must be set high to access the divisor latches and low
to access the receiver buffer or the interrupt enable register.
DIN(7:0)
I
Data Input Bus - Active high - Serves as input data when
writing to internal UART registers.
CS0
I
Chip Select 0 - Active high - When CS0, CS1 and CS2 are active
the megafunction is selected. Read and write transactions to
internal UART registers are then possible.
CS1
I
Chip Select 1 - Active high - When CS0, CS1 and CS2 are active
the megafunction is selected. Read and write transactions to
internal UART registers are then possible.
CS2_n
I
Chip Select 2 - Active low - When CS0, CS1 and CS2 are active
the megafunction is selected. Read and write transactions to
internal UART registers are then possible.
ADS_n
I
Address Strobe - Active low - Gating signal to the Address
input latch. The positive edge of ADS_n latches the state of the
register address bus into the Address input latch. If address
signals are guaranteed to be stable for the duration of a read or
write cycle, ADS_n may be tied low thus forcing the Address
input latch to be transparent.
RD
I
Read Control - Active High - when RD is high or RD_n is low
and the UART is selected, read transactions from internal
UART registers are possible.
Page 4 of 10
IA16450
Preliminary Data Sheet
Universal Asynchronous Receiver/Transmitter
Copyright
1999, InnovASIC Inc.
Customer Specific IC Solutions
Name
Type
Description
RD_n
I
Read Control - Active low - when RD is high or RD_n is low
and the UART is selected, read transactions from internal
UART registers are possible.
WR
I
Write Control - Active High - when WR is high or WR_n is low
and the UART is selected, write transactions to internal UART
registers are possible.
WR_n
I
Write Control - Active low - when WR is high or WR_n is low
and the UART is selected, write transactions to internal UART
registers are possible.
SIN
I
Serial Data Input - Active High - Receive data to the UART
RCLK
I
Receive Clock - The 16x baud rate clock used by the receiver
section of the UART.
CTS_n
I
Clear To Send - Active Low - Active state indicates that the
MODEM or data set is ready to exchange data. A change in
state of this input is recorded in the DCTS bit (bit 0) of the
MODEM Status register. Whenever CTS_n changes state, an
interrupt is generated if the MODEM Status interrupt is
enabled. The complement of this input is recorded in the CTS
(bit 4) bit of the MODEM Status register
DSR_n
I
Data Set Ready - Active Low - Active state indicates that the
MODEM or data set is ready to establish the communications
link with the UART. A change in state of this input is recorded
in the DDSR bit (bit 1) of the MODEM Status register.
Whenever DSR_n changes state, an interrupt is generated if the
MODEM Status interrupt is enabled. The complement of this
input is recorded in the DSR (bit 5) bit of the MODEM Status
register
DCD_n
I
Data Carrier Detect - Active Low - Active state indicates that
the data carrier has been detected by the MODEM or data set.
A change in state of this input is recorded in the DDCD bit (bit
3) of the MODEM Status register. Whenever DCD_n changes
state, an interrupt is generated if the MODEM Status interrupt
is enabled. The complement of this input is recorded in the
DCD (bit 7) bit of the MODEM Status register
Page 5 of 10
IA16450
Preliminary Data Sheet
Universal Asynchronous Receiver/Transmitter
Copyright
1999, InnovASIC Inc.
Customer Specific IC Solutions
Name
Type
Description
RI_n
I
Ring Indicator - Active Low - Active state indicates that the ring
signal has been detected by the MODEM or data set. A change
in state of this input is recorded in the TERI bit (bit 2) of the
MODEM Status register. Whenever DSR_n changes state, an
interrupt is generated if the MODEM Status interrupt is
enabled. The complement of this input is recorded in the RI
(bit 6) bit of the MODEM Status register
DOUT(7:0)
O
Data Output Bus - Active high - Serves as output data when
reading from internal UART registers.
DDIS
O
Driver Disable - Active High - Active State indicates that the
CPU is reading data from the UART. This output is intended as
a disable or direction control between the UART and CPU.
CSOUT
O
Chip Select Output - Active High - Active State indicates that
the megafunction has been selected by use of the CS0, CS1 and
CS2_n inputs.
SOUT
O
Serial Data Out - Active High - Serial (transmit) data out. This
signal is set to the marking (logic 1) state upon master reset.
BAUDOUT_n
O
Baud Out - Active Low - The 16x baud rate clock used by the
transmitter section of the UART. This output is controlled by
the programmable baud rate generator.
RTS_n
O
Request to Send - Active Low - This output indicates that the
UART is ready to exchange data. This output is controlled by
writing to the RTS (bit 1) bit of the control register.
DTR_n
O
Data Terminal Ready - Active Low - This output indicates that
the UART is ready to establish a communications link. This
output is controlled by writing to the DTR (bit 0) bit of the
control register.
OUT1_n
O
Discrete Output - Active Low - One of two user-programmable
discrete outputs. This output is controlled by writing to the
OUT1 (bit 2) bit of the control register.
OUT2_n
O
Discrete Output - Active Low - One of two user-programmable
discrete outputs. This output is controlled by writing to the
OUT2 (bit 3) bit of the control register.
INTR
O
Interrupt - Active High - Indicates that an enabled interrupt has
had its interrupt condition met.
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