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Datasheet: M2006-12AI669.6429 (Integrated Circuit Systems)

VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING

 

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Integrated Circuit Systems
M2006-12A Datasheet Rev 1.0
Revised 28Jul2004
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
N e t w o r k i n g & C o m m u n i c a t i o n s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
M2006-12A
VCSO B
ASED
FEC C
LOCK
PLL
WITH
H
ITLESS
S
WITCHING
Integrated
Circuit
Systems, Inc.
P r o d u c t D a t a S h e e t
G
ENERAL
D
ESCRIPTION
The M2006-12A is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator
PLL designed for clock frequency
translation and jitter attenuation.
Clock multiplication ratios (including
forward and inverse FEC) are
pin-selected from pre-programming
look-up tables. Includes Hitless
Switching and Phase Build-out to
enable SONET (GR-253) / SDH (G.813) MTIE and
TDEV compliance during reference clock reselection.
Hitless Switching (HS) engages when a 4ns or greater
clock phase change is detected.
This phase-change triggered implementation of HS is
not recommended when using an unstable reference
(more than 1ns jitter pk-to-pk) or when the resulting
phase detector frequency is less than 5MHz.
F
EATURES
Reduced intrinsic output jitter and improved power
supply noise rejection compared to
M2006-12
Similar to the
M2006-02A
- and pin-compatible - but
adds Hitless Switching and Phase Build-out functions
Includes APC pin for Phase Build-out function (for
absorption of the input phase change)
Pin-selectable PLL divider ratios support forward and
inverse FEC ratio translation
Input reference and VCSO frequencies up to 700MHz
(Specify VCSO frequency at time of order)
Low phase jitter of 0.25 ps rms typical
(12kHz to 20MHz or 50kHz to 80MHz)
Commercial and Industrial temperature grades
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
Figure 1: Pin Assignment
Example I/O Clock Combinations
S
IMPLIFIED
B
LOCK
D
IAGRAM
Figure 2: Simplified Block Diagram
Using M2006-12A-622.0800
PLL Ratio
Input Clock (MHz)
Output Clock (MHz)
1/1
622.08, 155.52,
77.76, or 19.44
622.08
or
155.52
237/255
(inverse FEC)
669.3266, 167.3316,
83.6658, or 20.9165
Table 1: Example I/O Clock Combinations Using M2006-12A-622.0800
Using M2006-12A-669.3266
PLL Ratio
Input Clock (MHz)
Output Clock (MHz)
237/255
(FEC rate)
622.08, 155.52,
77.76, or 19.44
669.3266
or
167.3316
1/1
669.3266, 167.3316,
83.6658, or 20.9165
Table 2: Example I/O Clock Combinations Using M2006-12A-669.3266
M 2 0 0 6 - 1 2
( T o p V i e w )
18
17
16
15
14
13
12
11
10
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
F
I
N
_
SEL
1
GN
D
AP
C
DI
F
_RE
F
0
n
D
I
F
_RE
F
0
RE
F
_
S
E
L
DI
F
_RE
F
1
n
D
I
F
_RE
F
1
VC
C
P0_SEL
P1_SEL
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
FIN_SEL0
FEC_SEL0
FEC_SEL1
FEC_SEL2
FEC_SEL3
VCC
DNC
DNC
DNC
nOP
_
I
N
O
P
_O
UT
VC
nV
C
nOP
_
OU
T
OP
_
I
N
GN
D
GN
D
GN
D
19
20
21
22
23
24
25
26
27
A
Rfec Div
Mfec Div
Mfec / Rfec
Divider LUT
Mfin Divider
LUT
FIN_SEL1:0
REF_SEL
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
P0_SEL
P1_SEL
VCSO
0
1
M2006-12
FOUT0
nFOUT0
FOUT1
nFOUT1
FEC_SEL3:0
4
2
APC
P0 Div
(1 or 4)
Mfin Div
(1, 4, 8, or 32)
P1 Div
(1 or 4)
Loop
Filter
A
M2006-12A VCSO Based FEC Clock PLL with Hitless Switching
M2006-12A Datasheet Rev 1.0
2 of 10
Revised 28Jul2004
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
N e t w o r k i n g & C o m m u n i c a t i o n s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
Integrated
Circuit
Systems, Inc.
M2006-12A
VCSO B
ASED
FEC C
LOCK
PLL
WITH
H
ITLESS
D
ETAILED
B
LOCK
D
IAGRAM
Figure 3: Detailed Block Diagram
P
IN
D
ESCRIPTIONS
Number
Name
I/O
Configuration
Description
1, 2, 3, 10, 14, 26 GND
Ground
Power supply ground connections.
4
9
OP_IN
nOP_IN
Input
External loop filter connections. See Figure 4.
5
8
nOP_OUT
OP_OUT
Output
6
7
nVC
VC
Input
11, 19, 33
VCC
Power
Power supply connection, connect to +
3.3
V.
12, 13
FOUT1, nFOUT1
Output
No internal terminator
Clock output pairs. Differential LVPECL.
15, 16
FOUT0, nFOUT0
17
18
P1_SEL
P0_SEL
Input
Internal pull-down resistor
1
P Divider controls. LVCMOS/LVTTL.
(For
P0_SEL, P1_SEL
, see
Table 6
on
pg. 3.
20
21
nDIF_REF1
Input
Internal pull-UP resistor
1
Reference clock input pair 1.
Differential LVPECL or LVDS.
DIF_REF1
Internal pull-down resistor
1
22
REF_SEL
Input
Internal pull-down resistor
1
Reference clock input selection. LVCMOS/LVTTL:
Logic
1
selects
DIF_REF1, nDIF_REF1.
Logic
0
selects
DIF_REF0, nDIF_REF0
.
23
24
nDIF_REF0
Input
Internal pull-UP resistor
1
Reference clock input pair 0.
Differential LVPECL or LVDS.
DIF_REF0
Internal pull-down resistor
1
25
APC
Input
Internal pull-down resistor
1
Automatic Phase Compensation (phase
build-out). LVCMOS/LVTTL:
Logic
1
- Device absorbs input phase transients
.
Logic
0
- Device doesn't absorb transients.
27
28
FIN_SEL1
FIN_SEL0
Input
Internal pull-down resistor
1
I
nput clock frequency selection. LVCMOS/LVTTL.
(For
FIN_SEL1:0
, see
Table 4
on
pg. 3.
29
30
31
32
FEC_SEL0
FEC_SEL1
FEC_SEL2
FEC_SEL3
Input
Internal pull-UP resistor
1
FEC PLL divider ratio selection. LVCMOS/ LVTTL.
(For
FEC_SEL3:0
, see
Table 5
on
pg. 3.)
34, 35, 36
DNC
Do Not Connect.
Internal nodes. Connection to these pins can
cause erratic device operation.
Table 3: Pin Descriptions
Phase
Locked
Loop
(PLL)
M2006-12
SAW Delay Line
Phase
Shifter
VCSO
C
POST
C
POST
VC
nVC
R
POST
nOP_OUT
OP_OUT
R
POST
R
LOOP
R
LOOP
C
LOOP
C
LOOP
R
IN
R
IN
OP_IN
nOP_IN
Phase
Detector
Loop Filter
Amplifier
External
Loop Filter
Components
FOUT0
nFOUT0
FEC_SEL3:0
P0_SEL
FIN_SEL1:0
Rfec
Divider
MUX
0
REF_SEL
APC
DIF_REF1
nDIF_REF1
DIF_REF0
nDIF_REF0
1
FOUT1
nFOUT1
P1_SEL
2
Mfec / Rfec
Divider LUT
4
Mfin Divider
LUT
Mfin Divider
Mfec Divider
P1 Divider
P = 1 ( P1_SEL = 0 )
or 4 ( P1_SEL = 1 )
P0 Divider
P = 1 ( P0_SEL = 0 )
or 4 ( P0_SEL = 1 )
A
M2006-12A Datasheet Rev 1.0
3 of 10
Revised 28Jul2004
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
N e t w o r k i n g & C o m m u n i c a t i o n s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
M2006-12A
VCSO B
ASED
FEC C
LOCK
PLL
WITH
H
ITLESS
Integrated
Circuit
Systems, Inc.
PLL D
IVIDER
L
OOK
-U
P
T
ABLES
Mfin Divider Look-Up Table (LUT)
The
FIN_SEL1:0
pins select the feedback divider value
"Mfin" (for Frequency Input).
Note
*: Do not use with FEC_SEL3:0=1100 or 1101 or an excessive
phase detector frequency will result.
Note
: Example with M2006-12A-622.0800 and "Non-FEC ratio"
selection made from Table 5 (FEC_SEL2=1).
FEC PLL Ratio Dividers Look-up Table (LUT)
The
FEC_SEL3:0
pins select the FEC feedback and
reference divider values Mfec and Rfec.
Post-PLL Dividers
The M2006-12A also features two post-PLL dividers,
one for each output pair. The "P1" divider is for
FOUT1
and
nFOUT1
; the "P0" divider is for
FOUT0
and
nFOUT0
.
Each divides the VCSO frequency to produce one of
two output frequencies (1/4 or 1/1 of the VCSO
frequency). The
P1_SEL
and
P0_SEL
pins each select the
value for their corresponding divider.
F
UNCTIONAL
D
ESCRIPTION
The M2006-12A is a PLL (Phase Locked Loop) based
clock generator that generates output clocks synchro-
nized to one of two selectable input reference clocks.
An internal high "Q" SAW filter provides low jitter signal
performance and controls the output frequency of the
VCSO (Voltage Controlled SAW Oscillator).
Configurable FEC feedback and reference dividers (the
"Mfec Divider" and "Rfec Divider") provide the
multiplication ratios necessary to accomodate clock
translation for both forward and inverse Forward Error
Correction.
In addition, a configurable feedback divider (labeled
"Mfin Divider") provides the broader division options
needed to accomodate various reference clock
frequencies.
For example, the
M2006-12A-622.0800
(see "Ordering
Information"
on pg. 10
)
has a
622.08
MHz VCSO
frequency:
The inverse FEC PLL ratios (at top of Table 5) enable
the
M2006-12A-622.0800
to accept "base" input reference
frequencies of:
663.7255
,
666.5143
,
669.3266
,
672.1627
, and
622.08
MHz.
The Mfin feedback divider enables the actual input
reference clock to be the "base" input frequency
divided by
1
,
4
,
8
, or
32
. Therefore, for the base input
frequency of
622.08
MHz, the actual input reference
clock frequencies can be:
622.08
,
155.52
,
77.76
, and
19.44
MHz. (See Table 4 on pg. 3.)
FIN_SEL1:0
Mfin Value
M2006-12A-622.0800
Sample Ref. Freq. (MHz)
1
1
1 *
622.08
1
0
4
155.52
0
1
8
77.76
0
0
32
19.44
Table 4: Mfin Divider Look-Up Table (LUT)
FEC_SEL3:0
Mfec Rfec
1
Note 1: The phase detector frequency (Fpd, which is calculated as
Fref/Rfec) should be above 1.5 MHz to prevent spurs on the
output clock. To ensure the PLL remains locked when using a
recovered clock (such as in loop timing mode), the phase
detector frequency should ideally be about 20MHz, or at least
less than 50 MHz.
Description
0 0 0 0
236
255 Inverse FEC ratio
0 0 0 1
79
85
Inverse FEC ratio, equivalent to
237/255
0 0 1 0
14
15
Inverse FEC ratio, equivalent to
238/255
0 0 1 1
239
255 Inverse FEC ratio
0 1 0 0
236
236 Non-FEC ratio, complements
0000 or 1000
2
Note 2: These table selections use the same or similar Mfec divider
values as the complementary selections noted. This allows the
use of the same loop filter component values and yields the
same PLL loop bandwidth and damping factor values for
complementary selections. Complementary selections can be
actively switched in a given application.
0 1 0 1
79
79
Non-FEC ratio, complements
0001
or 1001
2
0 1 1 0
14
14
Non-FEC ratio, complements
0010
or 1010
2
0 1 1 1
239
239 Non-FEC ratio, complements
0011 or 1011
2
1 0 0 0
255
236 FEC ratio (OTU3)
1 0 0 1
85
79
FEC ratio, equivalent to 255/237 (OTU2)
1 0 1 0
15
14
FEC ratio, equivalent to 255/238 (OTU1)
1 0 1 1
255
239 FEC ratio
1 1 0 0
1
1
Non-FEC ratio
3
Do not use these two settings
with
FIN_SEL1:0=11
Note 3: In non-FEC applications, these settings can be used to
optimize phase detector frequency or to actively change PLL
loop bandwidth.
1 1 0 1
2
2
1 1 1 0
4
4
Non-FEC ratio
3
1 1 1 1
8
8
Table 5: FEC PLL Ratio Dividers Look-up Table (LUT)
P1_SEL, P0_SEL
P Value
M2006-12A-622.0800
Sample Output
Frequency (MHz)
1
4
155.52
0
1
622.08
Table 6: P Divider Selector, Values, and Frequencies
M2006-12A Datasheet Rev 1.0
4 of 10
Revised 28Jul2004
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
N e t w o r k i n g & C o m m u n i c a t i o n s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
Integrated
Circuit
Systems, Inc.
M2006-12A
VCSO B
ASED
FEC C
LOCK
PLL
WITH
H
ITLESS
The PLL
The PLL uses a phase detector and configurable
dividers to synchronize the output of the VCSO with
selected reference clock.
The "Mfin Divider" and "Mfec Divider" divide the VCSO
frequency, feeding the result into the phase detector.
The selected input reference clock is divided by the
"Rfec Divider". The result is fed into the other input of
the phase detector.
The phase detector compares its two inputs. It then
outputs pulses to the loop filter as needed to increase or
decrease the VCSO frequency and thereby match and
lock the divider output's frequency and phase to those
of the input reference clock.
Due to the narrow tuning range of the VCSO
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
See also
"Maintaining PLL Lock:"
on pg. 4.
Relationship Among Frequencies and Dividers
The VCSO center frequency must be specified at time
of order. The relationship between the VCSO (Fvcso)
frequency, the Mfin divider, the Mfec divider, the Rfec
divider, and the input reference frequency (Fin) is:
As an example, for the
M2006-12A-622.0800
, the non-FEC
and inverse-FEC PLL ratios in Table 5 enable use with
these corresponding input reference frequencies:
Maintaining PLL Lock:
The narrow tuning range of the VCSO requires that the
input reference frequency must remain suitable for the
current look-up table selection. For example, when
switching between "Inverse FEC ratio" and "Non-FEC
ratio" look-up table selections (see Table 5 on pg. 3), the
input reference frequency must change accordingly in
order for the PLL to lock.
An out-of-lock condition due to an inappropriate
configuration will typically result in the VCSO
operating at its lower or upper frequency rail,
which is approximately 200ppm above or below
the nominal VCSO center frequency.
See also
"Hitless Switching (HS)" (next) for an
additional issue with regard to phase locking.
Hitless Switching (HS)
The M2006-12A includes a proprietary Hitless
Switching (HS) feature that prevents an excessive
phase transient of the output clocks upon input
reference rearrangement. Upon the occurance of an
input reference phase change, or phase transient, PLL
bandwidth is lowered by the HS function. This limits the
rate of phase change in the output clocks. With proper
configuration of the external loop filter, the output clocks
will comply with MTIE (maximum time interval error)
specifications for GR-253 (SONET) and ITU G.813
(SDH) during input reference clock change, depending
on the magnitude of the resulting phase change.
The HS function uses a phase error detector at the
phase detector to detect a clock phase change. During
normal operation with a stable reference clock, the PLL
will be frequency locked and phase locked, resulting in
very little error at the phase detector (<1 ns). Upon the
selection of a new input reference clock at a different
clock phase, a phase error will occur at the phase
detector. The HS function is triggered with a phase error
greater than 4 ns, upon which a narrow PLL bandwidth
is applied. When the PLL locks to within 2 ns error at the
phase detector, wide bandwidth (normal) operation is
resumed.
The HS function is not suitable for situations in which an
unstable reference is used. Under normal conditions
the reference clock jitter should not induce phase jitter
at the phase detector beyond 2 ns. (This includes when
subjecting the system to jitter tolerance compliance
testing.) Because of this, the M2006-12A is not
recommended for use with some Stratum DPLL clock
sources, or with unstable recovered network clocks
intended for loop timing configuration. It is also not
recommended for complex FEC ratios where the phase
detector is operated at less 1 MHz. For these
applications the
M2006-02A
is suggested. The
M2006-02A is identical to the M2006-12A except that it
does not include the HS function (nor the APC pin and
phase build-out function, which are discussed in the
following section).
M2006-12A-622.0800
M2006-12A-622.0800
VCSO Clock
Frequency (MHz)
FEC Ratio
=
Base Input Ref.
Frequency (MHz)
1
Note 1: Input reference clock ("Fin") can be the base frequency
shown divided by "Mfin" (as shown in Table 4 on pg. 3).
622.08
1
/
1
622.0800
238
/ 255
666.5143
237
/ 255
669.3266
236
/ 255
672.1627
Table 7: Example FEC PLL Rations and Input Reference Frequencies
Fvcso
Fin Mfin
Mfec
Rfec
--------------
=
M2006-12A Datasheet Rev 1.0
5 of 10
Revised 28Jul2004
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
N e t w o r k i n g & C o m m u n i c a t i o n s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
M2006-12A
VCSO B
ASED
FEC C
LOCK
PLL
WITH
H
ITLESS
Integrated
Circuit
Systems, Inc.
Automatic Phase Compensation (APC) Pin
The M2006-12A also includes a phase build-out
function that can be selectively enabled by asserting the
APC input (pin
25
) to logic
1
. The phase build-out
function works in conjunction with the HS function.
When the APC pin is asserted, the phase build-out
function enables the PLL to absorb most of the phase
change of the input clock which reduces re-lock time
and the generation of wander. (Wander is created in this
case by the generation of extra output clock cycles.)
When the APC pin is asserted, the phase build-out
function is triggered by same >4 ns phase transient (at
the phase detector) that triggers the HS function. Once
triggered, a new VCSO clock edge is selected for the
phase comparator feedback input. (The clock edge
selected is the one closest in phase to the new input
clock phase.) The residual phase detector phase error
following reselection is approximately 3-to-4 ns. The
narrow bandwidth selected by HS minimizes VCSO
drifting and switch transients during the process.
It is recommended that the APC pin remain low when
the phase detector frequency is less than 4 MHz.
Otherwise, the M2006-12A may have difficulty locking
to reference upon power-up.
Outputs
The M2006-12A provides a total of two differential
LVPECL output pairs:
FOUT1
and
FOUT0.
Because each
output pair has its own P divider, the
FOUT1
pair and the
FOUT0
can output the two different frequencies at the
same time. For example,
FOUT1
can output
155.52
MHz
while
FOUT0
outputs
622.08
MHz.
Any unused output should be left unconnected
(floating) in the system application. This will
minimize output switching current and therefore
minimize noise modulation of the VCSO.
External Loop Filter
To provide stable PLL operation, and thereby a low jitter
output clock, the M2006-12A requires the use of an
external loop filter. This is provided via the provided
filter pins (see Figure 4).
Due to the differential signal path design, the
implementation requires two identical complementary
RC filters as shown here.
Figure 4: External Loop Filter
See Example External Loop Filter Component Values table.
PLL bandwidth is affected by loop filter component
values, "Mfec" and "Mfin" values, and the "PLL Loop
Constants" listed in AC Characteristics on pg. 8.
The various "Non-FEC ratio" settings can be used to
actively change PLL loop bandwidth in a given
application. See "FEC PLL Ratio Dividers Look-up
Table (LUT)" on pg. 3.
PLL Simulator Tool Available
A free PC software utility is available on the ICS website
(www.icst.com). The M2000 Timing Modules PLL
Simulator is a downloadable application that simulates
PLL jitter and wander transfer characteristics. This
enables the user to set appropriate external loop
component values in a given application.
Go to the SAW PLL Simulator Software web page at
www.icst.com/products/calculators/m2000filterSWdesc.htm
C
POST
C
POST
VC
nVC
R
POST
nOP_OUT
OP_OUT
R
POST
R
LOOP
R
LOOP
C
LOOP
C
LOOP
OP_IN
nOP_IN
6
7
5
4
9
8
Example External Loop Filter Component Values
1
VCSO Parameters: K
VCO
= 800kHz/V, R
IN
= 50k
, VCSO Bandwidth = 700kHz.
Device Configuration
Example External Loop Filter Component Values
Nominal Performance Using These Values
F
Ref
(MHz)
F
VCSO
(MHz) FIN_SEL1:0
pins
FEC_ SEL3:0
pins
R loop
C loop
R post
C post
PLL Loop
Bandwidth
Damping
Factor
Passband
Peaking
(dB)
19.44
622.08
0 0
1 1 0 0
11.5
k
2.2
F
34
k
470
pF
1k
Hz
6.0
0.05
77.76
0 1
1 1 1 0
155.52
1 0
1 1 1 1
622.08
1 1
0 1 1 0
5.11
k
4.7
F
6.0
0.06
167.3317
1 0
0 0 0 1
113.0
k
0.22
F
6.0
0.06
669.3266
1 1
28.0
k
1.0
F
6.3
0.05
155.52
669.3266
1 0
1 0 0 1
121.0
k
0.22
F
6.0
0.05
622.08
1 1
30.1
k
1.0
F
6.5
0.05
Table 8: Example External Loop Filter Component Values
Note 1: K
VCO
, VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor, and
Passband Peaking. For PLL Simulator software, go to www.icst.com.
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