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Datasheet: M2004-11 (Integrated Circuit Systems)

Frequencytranslation PLL

 

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Integrated Circuit Systems
Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com
M2004-11
Preliminary Specifications
1
Micro Networks
An Integrated Circuit Systems Company
ISO 9001
Registered
ISO 9001
Registered
M2004-11
Frequency Synthesizer
DESCRIPTION
The M2004-11 integrates a high performance Phase
Locked Loop (PLL) with a Voltage Controlled SAW
Oscillator (VCSO) to provide a low jitter Frequency
Translator in a 9mm x 9mm surface mount package.
The M2004-11 is pin and function compatible with
the M2004-01 and in addition includes a phase
slope limiting circuit. This provides phase build-out
protection when reselecting the input clock.
The internal high "Q" SAW filter provides low jitter
signal performance and determines the maximum
output frequency of the VCSO. A programmable
output divider can divide the VCSO frequency to
achieve an output as low as 38.88MHz.
The input to the Frequency Translator is provided by
selecting between one of two output reference
clocks. The output frequency is an integer multiple
of the input reference frequency.
Parallel and serial control of the output and
feedback dividers is provided via the configuration
logic. An external loop filter sets the PLL bandwidth
which can be optimized to provide jitter attenuation
of the input reference clock.
The M2004-11 is available at SONET/SDH and
10GbE frequencies up to 700MHz.
Pin Compatible with the M2004-01
Build-in phase slope limiter for phase
build-out protection
Meets Bellcore GR-253-CORE MTIE
Output Clock Frequency up to 700MHz
Differential LVPECL Outputs
Internal Low-jitter SAW-based Oscillator
Intrinsic Jitter <1ps rms (12kHz - 20MHz)
Jitter Attenuation of Input Reference Clock
Dual Input MUX
Parallel Programming
Tunable Loop Filter Response
3.3V Operation
Small 9mm x 9mm SMT Package
Inputs, V
I
:
................................................. -0.5 to V
CC
+0.5V
Output, V
O
:
................................................. -0.5 to V
CC
+0.5V
Supply Voltage, V
DD
: ......................................................... 4.6 V
Storage Temperature, T
STO
: ............................ -45C to +100C
Stresses beyond those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These ratings are stress specifications
only. Functional operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
ABSOLUTE MAX RATINGS
FEATURES
APPLICATIONS
SONET / SDH / 10GbE System
Synchronization
Add / Drop Muxes, Access and Edge
Switches
Line Card System Clock Cleaner /
Translator
Optical Module Clock Cleaner / Translator
Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com
M2004-11
Preliminary Specifications
2
Micro Networks
An Integrated Circuit Systems Company
The internal PLL will adjust the VCSO output
frequency to be M times the selected input
reference clock frequency. Note that the product of
M x input frequency must be such that it falls within
the "lock" range of the VCSO. The N output divider
can be programmed to divide the VCSO output
frequency by 1, 2, 4, or 8 and provide a 50% output
duty cycle.
The M2004-01 supports both parallel and serial
operating modes for programming the M divider
and N output divider. Figure 1 shows the timing
diagram for each mode. In the parallel mode the
nP_LOAD input is initially LOW. The data on inputs
M0 through M5 and N0 and N1 is passed directly to
the M divider. On the LOW-to-HIGH transition of
the nP_LOAD input, the data is latched and the M
divider remains loaded until the next LOW transition
on nP_LOAD or until a serial event occurs. As a
result, the M and N bits can be hardwired to set the
M divider and N output divider to a specific default
state that will automatically occur during power-up.
The relationship between the VCSO frequency, the
input REF_CLK , and the M divider is defined as
follows:
F VCSO = F REF_CLK x M
When the N output divider is included, the
complete relationship for the output frequency is
defined as:
FOUT= F VCSO = F REF_CLK x M
N
N
The M value and the required logic states of M0
through M5 are shown in Table 5B, Programmable
VCSO Frequency Function Table. (i.e. For an output
frequency of 622.08MHz and an input frequency of
19.44MHz the M value would be 32 and the N value
would be 1.
Similarly, for an output frequency of 311.04 MHz
and an input frequency of 19.44MHz the M value
would be 32 and the N value would be 2.) Serial
operation occurs when nP_LOAD is HIGH and
S_LOAD is LOW. The shift register is loaded by
sampling the S_DATA bits with the rising edge of
S_CLOCK. The contents of the shift register are
loaded into the M divider and N output divider
when S_LOAD transitions from LOW-to-HIGH. The
M divider and N output divide values are latched on
the HIGH-to- LOW transition of S_LOAD. If
S_LOAD is held HIGH, data at the S_DATA input is
passed directly to the M divider and N output
divider on each rising edge of S_CLOCK.
FUNCTIONAL BLOCK DIAGRAM
FIGURE 1
Low Low Null
Null Null Null
N1
N0
M5
M4
M3
M2
M1
M0
S_DATA
S_CLK
S_LOAD
M2004-11
SAW Delay Line
Phase
Shifter
VCSO
CPOST
CPOST
VC
nVC
RPOST
nOP_OUT
OP_OUT
RPOST
RLOOP CLOOP
RLOOP CLOOP
RIN
RIN
OP_IN
nOP_IN
M Divider
M = 3-1023
MUX
0
1
N Divider
N = 1,2,4,8
Serial / Parallel
Configuration Register
6
M5:0
N1:0
Phase
Detector
Loop Filter
Amplifier
External
Loop Filter
Components
REF_SEL
REF_CLK0
REF_CLK1
FOUT
nFOUT
MR
S_DATA
S_CLK
S_LOAD
nP_LOAD
2
Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com
M2004-11
Preliminary Specifications
3
Micro Networks
An Integrated Circuit Systems Company
FUNCTIONAL DESCRIPTION
LOOP FILTER
FIGURE 2
TABLE 1. RECOMMENDED LOOP FILTER VALUES
The M2004-01 requires the use of an external loop
filter via the provided filter pins. Due to the
differential design, the implementation requires two
identical RC filters as shown in Figure 2.
Ref Clk
VCSO
M
N
Fout
Rloop
Cloop
Rpost
Cpost
Frequency
Frequency
19.44MHz
622.0800MHz
32
1
622.0800MHz
5k
1MF
50k
100pf
Vc
nVc
OP_OUT
nOP_OUT
OP_IN
nOP_IN
Rloop
Rloop
Cloop
Cloop
Rpost
Rpost
Cpost
Cpost
Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com
M2004-11
Preliminary Specifications
4
Micro Networks
An Integrated Circuit Systems Company
PIN DESCRIPTIONS
TABLE 2
Pin Number
Name
I/O
Configuration
Description
1, 2, 3
GND
GND
Power Supply Ground
4, 9
OP_IN, nOP_IN
Analog I/O
Used for external loop filter. See Figure 2.
5, 8
nOP_OUT, OP_OUT
Analog I/O
Used for external loop filter. See Figure 2
6, 7
nVC, VC
Input
VCSO
Differential Control Voltage Input Pair
10, 14, 26
GND
GND
Power Supply Ground
11, 19, 33
VDD
Power
Positive Supply Pins
12, 13
N0, N1
Input
Pull - down
Determines the output divider value as defined in
table 3C. LVCMOS / LVTTL interface levels.
15, 16
FOUT, nFOUT
Output
Unterminated
Differential output, 3.3V LVPECL levels.
17
MR
Input
Pull - down
Logic HIGH resets the reference frequency and N
output dividers. Logic LOW enables the outputs.
LVCMOS / LVTTL interface levels.
18
S_CLOCK
Input
Pull - down
Clocks in serial data present at S_DATA input
into the shift register on the rising edge of
S_CLOCK.
20
S_DATA
Input
Pull - down
Shift register serial input. Data is sampled on the
rising edge of S_CLOCK.
21
S_LOAD
Input
Pull - down
Controls transition of data from shift register into
the dividers. LVCMOS / LVTTL interface levels
22
nP_LOAD
Input
Pull - down
Parallel load input. Determines when data
present at M5:M0 is loaded into Mdivider, and
when data present at N1:N0 sets the N output
divider value. LVCMOS / LVTTL interface levels.
23
REF_CLK1
Input
Pull - down
Input reference clock. LVCMOS / LVTTL interface
levels.
24
REF_CLK0
Input
Pull - down
Input reference clock. LVCMOS / LVTTL interface
levels.
25
REF_SEL
Input
Pull - down
Selects between the different reference clock
inputs as the PLL reference source. See table 3D.
LVCMOS / LVTTL interface levels.
27, 28, 29, 30, 31
M0, M1, M2, M3, M4 Input
Pull - down
M divider inputs. Data is latched on LOW-to-HIGH
transition of nP_LOAD input. LVCMOS/ LVTTL
interface levels.
32
M5
input
Pull - down
34, 35, 36
DNC
Do not connect. Internal test pins must be left
floating.
Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com
M2004-11
Preliminary Specifications
5
Micro Networks
An Integrated Circuit Systems Company
TABLE 4
PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
Typical
Max
Units
C
IN
Input Capacitance
4
pF
R
PULLUP
Input Pullup Resistor
51
k
R
PULLDOWN
Input Pulldown Resistor
51
k
TABLE 5B
PROGRAMMABLE VCSO FREQUENCY FUNCTION
VCSO Frequency
32
16
8
4
2
1
(MHz)
M Divide
M5
M4
M3
M2
M1
M0
325
13
0
0
1
1
0
1
350
14
0
0
1
1
1
0
375
15
0
0
1
1
1
1
400
16
0
1
0
0
0
0
600
24
0
1
1
0
0
0
625
25
0
1
1
0
0
1
650
26
0
1
1
0
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to a reference frequency of 25MHz.
TABLE 5A
PARALLEL & SERIAL MODES FUNCTION
Inputs
MR
nP Load
M
N
S_Load S_Clock S_Data
Conditions
H
X
X
X
X
X
X
Reset, Forces outputs LOW.
L
L
Data
Data
X
X
X
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
L
Data
Data
L
X
X
Data is latched into input registers and remains
loaded until next LOW transition or until a serial event
occurs.
L
H
X
X
L
Data
Serial input mode. Shift register is loaded with data
on S_DATA on each rising edge of S_CLOCK
L
H
X
X
L
Data
Contents of the shift register are passed to the M
divider and N output divider.
L
H
X
X
L
Data
M divider and N output divider values are latched.
L
H
X
X
L
X
X
Parallel or serial input do not affect shift registers.
L
H
X
X
H
Data
S_DATA passed directly to M divider as it is clocked.
Note: L = Low; H = High; X = Don't care; = Rising Edge Transition; = Falling Edge Transition
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