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Datasheet: M2004-02-622.0800 (Integrated Circuit Systems)

Frequencytranslation PLL

 

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Integrated Circuit Systems
Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com
M2004-02
Preliminary Specifications
1
Micro Networks
An Integrated Circuit Systems Company
ISO 9001
Registered
ISO 9001
Registered
M2004-02
Frequency Synthesizer
DESCRIPTION
The M2004-02 integrates a high performance Phase
Locked Loop (PLL) with a Voltage Controlled SAW
Oscillator (VCSO) to provide a low jitter Frequency
Synthesizer in a 9mm x 9mm surface mount
package.
The internal high "Q" SAW filter provides low jitter
signal performance and determines the maximum
output frequency of the VCSO.
A programmable output divider can divide the VCSO
frequency to achieve an output as low as 38.88MHz.
The input to the Frequency Synthesizer is provided
by selecting between a differential input clock or a
single ended input clock.
The output frequency is an integer multiple of the
input reference frequency. The multiplying factor is
programmed via a 6 bit parallel address.
An external loop filter sets the PLL bandwidth which
can be optimized to provide jitter attenuation of the
input reference clock.
The bandwidth control, low phase noise, and HOLD
features make the M2004-02 ideal for use as a clock
jitter attenuator, frequency translator, and clock
frequency generator in OC-3 through OC-192
applications.
Output Clock Frequency up to 700MHz
Internal Low-jitter SAW-based Oscillator
Intrinsic Jitter <1ps rms (12kHz - 20MHz)
Differential Input Compatible with LVPECL,
LVDS, HSTL, SSTL, etc.
Dual Input MUX
Parallel Programming
Tunable Loop Filter Response
Differential LVPECL Outputs
3.3V Operation
Small 9mm x 9mm SMT Package
FEATURES
APPLICATIONS
SONET / SDH / 10GbE System
Synchronization
Add / Drop Muxes, Access and Edge
Switches
Line Card System Clock Cleaner /
Translator
Optical Module Clock Cleaner / Translator
Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com
M2004-02
Preliminary Specifications
2
Micro Networks
An Integrated Circuit Systems Company
nF OUT
F OUT
Parallel Programming Interface
M5:M0
Mux
REF_CLK
DIF_REF 0
nDIF_REF 0
MR
OP_OUT
nOP_OUT
OP_IN
nOP_IN
+M
Vc
nVc
VCSO
REF_SEL
N1
Phase
Detector &
Active Loop
Filter
Output
Divider
Functional Description:
The internal PLL will adjust the VCSO output
frequency to be M (feedback divider) times the
selected input reference clock frequency. Note that
the product of M x the input reference frequency
must be such that it falls within the "lock" range of
the VCSO. The N output divider can be
programmed to divide the VCSO output frequency
by 1, 2, 4, or 8 and provide a 50% output duty
cycle.
The multiplying factor is programmed via a 6-bit
parallel bus.
The relationship between the VCSO frequency, the
M divider, and the Differential Input reference clock
is defined as follows:
F VCSO = F REF_CLK x M
When the N output divider is included, the
complete relationship for the output frequency is
defined as:
FOUT = F VCSO = F REF_CLK x M
N
N
The N1 input can be hard wired to set the N divider
to a specific state that will automatically occur
during power-up.
FUNCTIONAL BLOCK DIAGRAM
Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com
M2004-02
Preliminary Specifications
3
Micro Networks
An Integrated Circuit Systems Company
FUNCTIONAL DESCRIPTION
LOOP FILTER
FIGURE 2
TABLE 1. RECOMMENDED LOOP FILTER VALUES
The M2004-02 requires the use of an external loop
filter via the provided filter pins. Due to the
differential design, the implementation requires two
identical RC filters as shown in Figure 2.
REF_CLK
VCSO
M
N
FOUT
Rloop
Cloop
Rpost
Cpost
Frequency
Frequency
19.44MHz
622.0800MHz
32
1
622.0800MHz
5k
1MF
20k
250pf
Vc
nVc
OP_OUT
nOP_OUT
OP_IN
nOP_IN
Rloop
Rloop
Cloop
Cloop
Rpost
Rpost
Cpost
Cpost
Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com
M2004-02
Preliminary Specifications
4
Micro Networks
An Integrated Circuit Systems Company
PIN DESCRIPTIONS
TABLE 2
Pin Number
Name
I/O
Configuration
Description
1, 2, 3
GND
GND
Power Supply Ground
4, 9
OP_IN, nOP_IN
Analog I/O
Used for external loop filter. See Figure 2.
5, 8
nOP_OUT, OP_OUT
Analog I/O
Used for external loop filter. See Figure 2
6, 7
nVC, VC
Input
VCSO Differential Control Voltage Input Pair
10, 14, 26
GND
GND
Power Supply Ground
11, 19, 33
V
CC
Power
Positive Supply Pins
12, 13
N0, N1
Input
Pull - down
Determines the output divider value as
defined in Table 3C. LVCMOS / LVTTL
interface levels.
15, 16
FOUT, nFOUT
Output
Unterminated
Differential output, 3.3V LVPECL levels.
17
MR
Input
Pull - down
Logic HIGH resets the reference frequency and N
output dividers. Logic LOW enables the outputs.
LVCMOS / LVTTL interface levels.
18, 20, 21
NC
No Connection
22
REF_SEL
Input
Pull - down
Selects between the different reference clock
inputs as the PLL reference source. See table 3D.
LVCMOS / LVTTL interface levels.
23
NDIF_REF
Input
Pull - down
Inverting differential clock input. Compatible
logic levels include LVCMOS, LVDS, HSTL, etc.
24
DIF_REF
Input
Pull - down
Non-inverting differential clock input. Compatible
logic levels include LVCMOS, LVDS, HSTL, etc.
25
REF_ CLK
Input
Pull - down
Input reference clock. LVCMOS / LVTTL interface
levels.
27, 28, 29, 30, 31
M0, M1, M2, M3, M4 Input
Pull - down
M divider inputs. Data is always transparent. No
latch signal is required.
32
M5
Input
Pull - down
34, 35, 36
DNC
Do not connect. Internal test pins.
Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com
M2004-02
Preliminary Specifications
5
Micro Networks
An Integrated Circuit Systems Company
TABLE 4
PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
Typical
Max
Units
C
IN
Input Capacitance
4
pF
R
PULLUP
Input Pullup Resistor
51
k
R
PULLDOWN
Input Pulldown Resistor
51
k
TABLE 5B
PROGRAMMABLE VCSO FREQUENCY FUNCTION
VCSO Frequency
32
16
8
4
2
1
(MHz)
M Divide
M5
M4
M3
M2
M1
M0
325
13
0
0
1
1
0
1
350
14
0
0
1
1
1
0
375
15
0
0
1
1
1
1
400
16
0
1
0
0
0
0
600
24
0
1
1
0
0
0
625
25
0
1
1
0
0
1
650
26
0
1
1
0
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to a reference frequency of 25MHz.
TABLE 5A
PARALLEL & SERIAL MODES FUNCTION
Inputs
MR
M
N
Conditions
H
X
X
Reset, Forces outputs LOW.
L
Data
Data
Data on M and N inputs passed directly to the M divider and N output divider.
Note: L = Low; H = High; X = Don't care; = Rising Edge Transition; = Falling Edge Transition
Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com
M2004-02
Preliminary Specifications
6
Micro Networks
An Integrated Circuit Systems Company
TABLE 5C
PARALLEL MODE FUNCTION
SERIAL MODE FUNCTION
TABLE 5D
Inputs
N Divider Output Frequency (MHz)
N1
N0
Value
Min
Max
0
0
1
311
700
0
1
2
155.5
350
1
0
4
77.75
175
1
1
8
38.875
87.5
Inputs
REF SEL
Reference
0
DIFF_REF
1
REF_CLK
POWER SUPPLY DC CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
V
DD
Power Supply Voltage
3.135
3.3
3.465
V
I
DD
Power Supply Current
162
mA
V
CC
= 3.3V 5%, T
A
= 0C to 70C
LVCMOS/LVTTL DC CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
Max
Units
V
IH
Input High
REF_SEL, REF_CLK,
2
VCC + 0.3
V
Voltage
N0:N1, M0:M5, MR
V
IL
Input Low
REF_SEL, N0:N1, M0:M5, MR
Voltage
REF_CLK
-0.3
1.3
V
I
IH
Input High
M5
V
DD
= V
IN
= 3.465V
5
A
Current
N0, N1, MR, M0:M4, S_CLOCK,
V
DD
= V
IN
= 3.465V
150
A
REF_SEL, REF_CLK
I
IL
Input Low
M5
V
DD
= 3.465, V
IN
= 0V
-150
A
Current
N0, N1, MR, M0:M4,
V
DD
= 3.465, V
IN
= 0V
-5
A
REF_SEL, REF_CLK
DIFFERENTIAL INPUT DC CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
Max
Units
I
IH
Input High
nDIF_REF
5
A
Current
DIF_REF
150
A
I
IL
Input Low
nDIF_REF
-150
A
Current
DIF_REF
-5
A
V
P-P
Peak to Peak Input Voltage
0.15
V
V
CMR
REF_SEL, REF_CLK
V
CC
+0.3
V
CC
-0.85
V
V
CC
= 3.3V 5%, T
A
= 0C to 70C
Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com
M2004-02
Preliminary Specifications
7
Micro Networks
An Integrated Circuit Systems Company
INPUT FREQUENCY CHARACTERISTICS
LVPECL DC CHARACTERISTICS
Symbol
Parameter
Signal
Min
Max
Units
V
OH
Output High Voltage: Note 1
FOUT, nFOUT
V
DD
1.4
Vcc 1.0
V
V
OL
Output Low Voltage: Note 1
FOUT, nFOUT
V
DD
2.0
Vcc 1.7
V
V
SWING
Peak-to-Peak Output Voltage Swing
FOUT, nFOUT
0.6
0.85
V
Note 1: Output terminated with 50 to V
DD
2.V
Symbol
Parameter
Test Conditions
Min
Max
Units
F
IN
Input Frequency DIF_REF 10 175 MHz
nDIF_REF 10 175 MHz
V
CC
= 3.3V5%, T
A
= 0C to 70C
AC CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
F
OUT
Output Frequency
38.88
667
MHz
NOISE
Single Side Band
1kHz offset
-72
dBc/Hz
Phase Noise
10kHz offset
-94
dBc/Hz
100kHz offset
-123
dBc/Hz
J (t)
Jitter (RMS)
12kHz to 20 MHz
0.69
ps
odc
Output Duty Cycle
50
%
t
R
Output Rise Time
FOUT = 155MHz
20% to 80%, each
350
450
550
ps
(Note 1)
for output pairs
FOUT = 311MHz
output of pair measured
325
425
500
ps
FOUT0, nFOUT0 &
FOUT= 622MHz
is terminated into 50
200
275
350
ps
FOUT1, nFOUT1
load biased at Vcc-2V
t
F
Output Fall Time
FOUT = 155MHz
20% to 80%, each
350
450
550
ps
(Note 1)
for output pairs
FOUT = 311MHz
output of pair measured
325
425
500
ps
FOUT0, nFOUT0 &
FOUT = 622MHz
is terminated into 50
200
275
350
ps
FOUT1, nFOUT1
load biased at Vcc-2V
t
LOCK
PLL Lock Time
1
ms
Note: The output frequencies of 155MHz, 311MHz and 622MHz were chosen for device characterization as these are common optical network clock frequencies.
Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com
M2004-02
Preliminary Specifications
8
Micro Networks
An Integrated Circuit Systems Company
PARAMETER MEASUREMENT INFORMATION
ODC & t
PERIOD
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
Clock Inputs
and Outputs
20%
80%
80%
20%
t
R
t
F
V
S W I N G
INPUT AND OUTPUT RISE AND FALL TIME
Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com
M2004-02
Preliminary Specifications
9
Micro Networks
An Integrated Circuit Systems Company
TEST EVALUATION BOARD
J3 9-PIN D
CONNECTOR
Pin
Signal
1
MR
3
S_CLOCK
5
S_DATA
7
S_LOAD
9
nP_LOAD
SW1
1
2
3
4
5
6
7
8
Position
REF Select
M5
M4
M3
M2
M1
M0
N/C
Off
REF_CLK0
"1"
"0"
"0"
"0"
"0"
"0"
N/C
On
REF_CLK1
"0"
"1"
"1"
"1"
"1"
"1"
N/C
JP1: N0
Logic "1" when installed
JP2: N1
Logic "0" when installed
Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.c
2
M2004-02
Preliminary Specifications
Micro Networks
An Integrated Circuit Systems Company
MECHANICAL DIMENSIONS & PIN CONFIGURATION
Pin# Designation
1 GND
2 GND
3 GND
4 OP_IN
5 nOP_OUT
6 nVC
7
VC
8 OP_OUT
9 nOP_IN
10 GND
11 VCC
12 NO
13 N1
14 GND
15 FOUT
16 nFOUT
17 MR
Pin# Designation
18 N/C
19 VCC
20 N/C
21 N/C
22 REF_SEL
23 nDIF_REF
24 DIF_REF
25 REF_CLK
26 GND
27 M0
28 M1
29 M2
30 M3
31 M4
32 M5
33 VCC
34, 35, 36 DNC
ORDERING INFORMATION
Dimensions are in inches, (dimensions) are in mm.
PART NUMBER M2004-02-622.0800
Series
Model
VCSO Center Frequency
(i.e. 622.0800MHz)
Available VCSO Frequencies
500.0000
666.5143 693.4830
Micro Networks
An Integrated Circuit Systems Company
324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456
European Sales Headquarters Hertogsingel 20 6214 AD Maastricht The Netherlands tel: +31-43-32-70912 fax: +31-43-32-70715
www.micronetworks.com
Rev. 7
.3
Micro Networks makes no assertion or warranty that the circuitry and the uses thereof
disclosed herein are non-infringing on any valid US or foreign patents. Micro Networks
assumes no liability as a result of the use of said specifications and reserves the right to
make changes to specifications without notice. Contact your nearest Micro Networks
sales representative office for the latest specifications.
ORIENTATION TAB
[
]
.354 [9.0]
.200 [5.1]
R.006 [R0.2]
.025 [0.6]
Pin #1
C
#36
L
.041 [1.0]
.007 [0.2]
C
CLL
#10
.354 [9.0]
#28
#27
#19
#18
.110 [2.8]
622.0800 669.1281
625.0000
669.3266
627.3296
672.1600
644.5313
690.5692
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