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Datasheet: M1033-11-156.2500 (Integrated Circuit Systems)

VCSO BASED CLOCK PLL WITH AUTOSWITCH

 

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Integrated Circuit Systems
M1033/34 Datasheet Rev 1.0
Revised 07Apr2005
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
N e t w o r k i n g & C o m m u n i c a t i o n s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
M1033/34
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
Integrated
Circuit
Systems, Inc.
P r o d u c t D a t a S h e e t
G
ENERAL
D
ESCRIPTION
The M1033/34 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting up to 2.5Gb data rates.
It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M1033/34 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
F
EATURES
Integrated SAW delay line; low phase jitter of < 0.5ps
rms, typical (12kHz to 20MHz)
Output frequencies of 62.5 to 175 MHz
(Specify VCSO output frequency at time of order)
LVPECL clock output (CML and LVDS options available)
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
Loss of Reference (LOR) output pin; Narrow Bandwidth
control input (NBW pin)
AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure
Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
Phase Build-out only upon MUX reselection option
(PBOM)
Pin-selectable feedback and reference divider ratios
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
Figure 1: Pin Assignment
S
IMPLIFIED
B
LOCK
D
IAGRAM
Figure 2: Simplified Block Diagram
Example I/O Clock Frequency Combinations
Using
M1033-11-155.5200 or M1034-11-155.5200
Input Reference
Clock (MHz)
PLL Ratio
(Pin Selectable)
Output Clock
(MHz)
(Pin Selectable)
(M1033) (M1034)
19.44 or 38.88
(M1033) (M1034)
8 or 4
155.52
or
77.76
77.76
2
155.52
1
622.08
0.25
Table 1: Example I/O Clock Frequency Combinations
M 1 0 3 3
M 1 0 3 4
( T o p V i e w )
18
17
16
15
14
13
12
11
10
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
MR
_
SEL3
GN
D
NC
D
I
F_
REF0
nD
I
F
_
R
EF0
R
E
F_
SEL
D
I
F_
REF1
nD
I
F
_
R
EF1
VC
C
P_SEL0
P_SEL1
nFOUT
FOUT
GND
REF_ACK
AUTO
VCC
GND
MR_SEL2
MR_SEL0
MR_SEL1
LOR
NBW
VCC
DNC
DNC
DNC
nO
P_IN
OP_OU
T
VC
nVC
nOP_OU
T
OP
_
I
N
GN
D
GN
D
GN
D
19
20
21
22
23
24
25
26
27
FOUT
nFOUT
TriState
Loop Filter
PLL
Phase
Detector
P_SEL1:0
NBW
M1033/34
VCSO
P Divider
LUT
M Divider
P Divider
(1, 2, or TriState)
MR_SEL3:0
R Div
MUX
0
REF_SEL
DIF_REF0
nDIF_REF0
1
M / R Divider
LUT
Auto
Ref Sel
1
0
REF_ACK
AUTO
4
Activity
Detector
DIF_REF1
nDIF_REF1
Activity
Detector
LOR
2
0
1
M1033/34 VCSO Based Clock PLL with AutoSwitch
M1033/34 Datasheet Rev 1.0
2 of 14
Revised 07Apr2005
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
N e t w o r k i n g & C o m m u n i c a t i o n s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
Integrated
Circuit
Systems, Inc.
M1033/34
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
P r o d u c t D a t a S h e e t
P
IN
D
ESCRIPTIONS
Number
Name
I/O
Configuration
Description
1, 2, 3, 10, 14, 26
GND
Ground
Power supply ground connections.
4
9
OP_IN
nOP_IN
Input
External loop filter connections.
See Figure 5, External Loop Filter, on pg. 9.
5
8
nOP_OUT
OP_OUT
Output
6
7
nVC
VC
Input
11, 19, 33
VCC
Power
Power supply connection, connect to +
3.3
V.
12
AUTO
Input
Internal pull-down resistor
1
Automatic/manual reselection mode for clock input:
Logic
1
automatic reselection upon clock failure
(non-revertive)
Logic
0
manual selection only (using
REF_SEL
)
13
REF_ACK
Output
Reference Acknowledgement pin for input mux state; outputs
the currently selected reference input pair:
Logic
1
indicates
nDIF_REF1, DIF_REF1
Logic
0
indicates
nDIF_REF0, DIF_REF0
15
16
FOUT
nFOUT
Output
No internal terminator
Clock output pair. Differential LVPECL (CML, LVDS available).
17
18
P_SEL1
P_SEL0
Internal pull-down resistor
1
Note 1: For typical values of internal pull-down and pull-UP resistors, see
DC Characteristics
on pg. 11.
Post-PLL, P divider selection. LVCMOS/LVTTL. See Table 5, P
Divider Look-Up Table (LUT),
on
pg. 4.
20
nDIF_REF1
Input
Biased to Vcc/2
2
Note 2: Biased to Vcc/2, with 50k
to Vcc and 50k
to ground. See Differential Inputs Biased to VCC/2 on pg. 11.
Note 3: See LVCMOS Output in
DC Characteristics
on pg. 11.
Reference clock input pair 1. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
21
DIF_REF1
Internal pull-down resistor
1
22
REF_SEL
Input
Internal pull-down resistor
1
Reference clock input selection. LVCMOS/LVTTL:
Logic
1
selects
DIF_REF1, nDIF_REF1.
Logic
0
selects
DIF_REF0, nDIF_REF0
.
23
nDIF_REF0
Input
Biased to Vcc/2
2
Reference clock input pair 0. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
24
DIF_REF0
Internal pull-down resistor
1
25
NC
No internal connection
27
28
29
30
MR_SEL3
MR_SEL2
MR_SEL0
MR_SEL1
Input
Internal pull-down resistor
1
M and R divider value selection. LVCMOS/ LVTTL.
See Tables 3 and 4, M and R Divider Look-Up Tables (LUT)
on pg. 3.
31
LOR
Output
Loss of Reference indicator. Asserted when there are no clock
edges at the selected input port for 3 clock edges of the PLL
phase detector.
3
Logic
1
indicates loss of reference.
Logic
0
indicates active reference.
32
NBW
Input
Internal pull-UP resistor
1
Narrow Bandwidth enable. LVCMOS/LVTTL:
Logic
1
- Narrow loop bandwidth
, R
IN
= 2100k
.
Logic
0
- Wide bandwidth
, R
IN
= 100k
.
34, 35, 36
DNC
Do Not Connect.
Table 2: Pin Descriptions
M1033/34 Datasheet Rev 1.0
3 of 14
Revised 07Apr2005
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
N e t w o r k i n g & C o m m u n i c a t i o n s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
M1033/34
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
P r o d u c t D a t a S h e e t
Integrated
Circuit
Systems, Inc.
D
ETAILED
B
LOCK
D
IAGRAM
Figure 3: Detailed Block Diagram
D
IVIDER
S
ELECTION
T
ABLES
M and R Divider Look-Up Tables (LUT)
The
MR_SEL3:0
pins select the feedback and reference
divider values M and R to enable adjustment of loop
bandwidth and jitter tolerance. The look-up tables vary
by device variant. M1033 and M1034 are defined in
Tables 3 and 4 respectively.
M1033 M/R Divider LUT
Tables 3 and 4 provide example Fin and phase
detector frequencies with 155.52MHz VCSO
devices (
M1033-11-155.5200 and M1034-11-155.5200).
See "Ordering Information" on pg. 14
.
M1034 M/R Divider LUT
Phase
Locked
Loop
(PLL)
SAW Delay Line
Phase
Shifter
VCSO
C
POST
C
POST
VC
nVC
R
POST
nOP_OUT
OP_OUT
R
POST
R
LOOP
R
LOOP
C
LOOP
C
LOOP
OP_IN
nOP_IN
PLL
Phase
Detector
Loop Filter
Amplifier
External
Loop Filter
Components
M Divider
R
IN
R
IN
FOUT
nFOUT
P Divider
LUT
P Divider
(1, 2, or TriState)
TriState
P_SEL1:0
NBW
MR_SEL3:0
R Div
MUX
0
REF_SEL
DIF_REF0
nDIF_REF0
1
M / R Divider
LUT
Auto
Ref Sel
1
0
REF_ACK
AUTO
4
Activity
Detector
DIF_REF1
nDIF_REF1
Activity
Detector
LOR
2
0
1
M1033/34
MR_SEL3:0
M Div R Div
Total
PLL
Ratio
Fin for
155.52MHz
VCSO (MHz)
Phase Det.
Freq. for
155.52MHz
VCSO (MHz)
0 0 0 0
8
1
8
19.44
19.44
0 0 0 1
32
4
8
19.44
4.86
0 0 1 0
128
16
8
19.44
1.215
0 0 1 1
512
64
8
19.44
0.30375
0 1 0 0
2
1
2
77.76
77.76
0 1 0 1
8
4
2
77.76
19.44
0 1 1 0
32
16
2
77.76
4.86
0 1 1 1
128
64
2
77.76
1.215
1 0 0 0
1
1
1
155.52
155.52
1 0 0 1
4
4
1
155.52
38.88
1 0 1 0
16
16
1
155.52
9.72
1 0 1 1
64
64
1
155.52
2.43
1 1 0 0
Test Mode
1
Note 1: Factory test mode; do not use.
N/A
N/A
N/A
1 1 0 1
1
4
0.25
622.08
155.52
1 1 1 0
4
16
0.25
622.08
38.88
1 1 1 1
16
64
0.25
622.08
9.72
Table 3: M1033 M/R Divider LUT
MR_SEL3:0
M Div R Div
Total
PLL
Ratio
Fin for
155.52MHz
VCSO (MHz)
Phase Det.
Freq. for
155.52MHz
VCSO (MHz)
0 0 0 0
4
1
4
38.88
38.88
0 0 0 1
16
4
4
38.88
9.72
0 0 1 0
64
16
4
38.88
2.43
0 0 1 1
256
64
4
38.88
0.6075
0 1 0 0
2
1
2
77.76
77.76
0 1 0 1
8
4
2
77.76
19.44
0 1 1 0
32
16
2
77.76
4.86
0 1 1 1
128
64
2
77.76
1.215
1 0 0 0
1
1
1
155.52
155.52
1 0 0 1
4
4
1
155.52
38.88
1 0 1 0
16
16
1
155.52
9.72
1 0 1 1
64
64
1
155.52
2.43
1 1 0 0
Test Mode
1
Note 1: Factory test mode; do not use.
N/A
N/A
N/A
1 1 0 1
1
4
0.25
622.08
155.52
1 1 1 0
4
16
0.25
622.08
38.88
1 1 1 1
16
64
0.25
622.08
9.72
Table 4: M1034 M/R Divider LUT
M1033/34 Datasheet Rev 1.0
4 of 14
Revised 07Apr2005
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
N e t w o r k i n g & C o m m u n i c a t i o n s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
Integrated
Circuit
Systems, Inc.
M1033/34
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
P r o d u c t D a t a S h e e t
General Guidelines for M and R Divider Selection
General guidelines for M/R divider selection (see
following pages for more detail):
A lower phase detector frequency should be used for
loop timing applications to assure PLL tracking,
especially during GR-253 jitter tolerance testing. The
recommended maximum phase detector frequency
for loop timing mode is
19.44MHz
.
P Divider Look-Up Table (LUT)
The
P_SEL1
and
P_SEL0
pins select the post-PLL divider
value P. The output frequency of the SAW can be
divided by
1
or
2
or the output can be TriStated as
specified in Table 5.
F
UNCTIONAL
D
ESCRIPTION
The M1033/34 is a PLL (Phase Locked Loop) based
clock generator that generates an output clock synchro-
nized to one of two selectable input reference clocks.
An internal high `Q' SAW delay line provides low jitter
signal performance.
A pin-selected look-up table is used to select the PLL
feedback divider (M Div) and reference divider (R Div)
as shown in
Tables 3 and 4 on pg. 3
. These look-up
tables provide flexibility in both the overall frequency
multiplication ratio (total PLL ratio) and phase detector
frequency.
The M1033/34 includes a Loss of Reference (
LOR
)
indicator for the currently selected reference input which
can be used to provides status information to system
management software. A Narrow Bandwidth (
NBW
)
control pin is provided as an additional mechanism for
adjusting PLL loop bandwidth without affecting the
phase detector frequency.
An automatic input reselection feature, or "AutoSwitch"
is also included in the M1033/34. When the AutoSwitch
mode is enabled, the device will automatically switch to
the other reference clock input when the currently
selected reference clock fails (when LOR goes high).
Reference selection is non-revertive, meaning that only
one reference reselection will be made each time that
AutoSwitch is re-enabled.
In addition to the AutoSwitch feature, a Phase Build-out
option can be ordered with the device.
P_SEL1:0
P Value
M1033-155.5200 or M1034-155.5200
Output Frequency (MHz)
0 0
2
77.76
0 1
1
155.52
1 0
2
77.76
1 1 TriState
N/A
Table 5: P Divider Look-Up Table (LUT)
M1033/34 Datasheet Rev 1.0
5 of 14
Revised 07Apr2005
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
N e t w o r k i n g & C o m m u n i c a t i o n s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
M1033/34
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
P r o d u c t D a t a S h e e t
Integrated
Circuit
Systems, Inc.
Input Reference Clocks
Two clock reference inputs and a selection mux are
provided. Either reference clock input can accept a
differential clock signal (such as LVPECL or LVDS) or
a single-ended clock input (LVCMOS or LVTTL on the
non-inverting input).
A single-ended reference clock on the unselected
reference input can cause an increase in output
clock jitter. For this reason, differential reference
inputs are preferred; interference from a differential
input on the non-selected input is minimal.
Implementation of single-ended input has been
facilitated by biasing
nDIF_REF0
and
nDEF_REF1
to Vcc/2,
with 50k
to Vcc and 50k to ground. Figure 4 shows
the input clock structure and how it is used with either
LVCMOS / LVTTL inputs or a DC- coupled LVPECL
clock.
Figure 4: Input Reference Clocks
Differential LVPECL Inputs
Differential LVPECL inputs are connected to both
reference input pins in the usual manner. The external
load termination resistors shown in Figure 4 (the
127
and
82
resistors) will work for both AC and DC
coupled LVPECL reference clock lines. These provide
the
50
load termination and the VTT bias voltage.
Single-ended Inputs
Single-ended inputs (LVCMOS or LVTTL) are
connected to the non-inverting reference input pin
(
DIF_REF0
or
DIF_REF1
). The inverting reference input pin
(
nDIF_REF0
or
nDIF_REF1
) must be left unconnected.
In single-ended operation, when the unused inverting
input pin (nDIF_REF0 or nDEF_REF1) is left floating (not
connected), the input will self-bias at VCC/2.
PLL Operation
The M1033/34 is a complete clock PLL. It uses a phase
detector and configurable dividers to synchronize the
output of the VCSO with the selected reference clock.
The "M" divider divides the VCSO output frequency,
feeding the result into the non-inverting input of the
phase detector. The output of the "R" divider is fed into
the inverting input of the phase detector. The phase
detector compares its two inputs. The phase detector
output, filtered externally, causes the VCSO to increase
or decrease in speed as needed to phase- and
frequency-lock the VCSO to the reference input.
The value of the M divider directly affects closed loop
bandwidth.
The relationship between the nominal VCSO center
frequency (Fvcso), the M divider, the R divider, and the
input reference frequency (Fin) is:
For the available M divider and R divider look-up table
combinations,
Tables 3 and 4 on pg. 3
list the Total PLL
Ratio as well as Fin when using the
M1033-11-155.5200
or
the
M1034-11-155.5200
.
("Ordering Information", pg. 14
.
)
Due to the narrow tuning range of the VCSO
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
Post-PLL Divider
The M1033/34 features a post-PLL (P) divider. By using
the P Divider, the device's output frequency (Fout) can
be the VCSO center frequency (Fvcso) or 1/2 Fvcso.
The
P_SEL
pin selects the value for the P divider: logic
1
sets P to
2,
logic
0
sets P to
1
. (See Table 5 on pg. 4.)
When the P divider is included, the complete relation-
ship for the output frequency (Fout) is defined as:
Due to the narrow tuning range of the VCSO
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
MUX
0
REF_SEL
1
VCC
50k
50k
VCC
50k
50k
LVCMOS/
LVTTL
LVPECL
50k
50k
VCC
82
127
VCC
82
127
M1025/26
X
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
Fvcso
Fin
M
R
----
=
Fout
Fvcso
P
-------------------
=
Fin
M
R
P
------------------
=
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