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Datasheet: M2087 (Integrated Circuit Solution)

VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN

 

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Integrated Circuit Solution
M2080/81/82 M2085/86/87 Datasheet Rev 0.4
Revised 30Jul2004
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
N e t w o r k i n g & C o m m u n i c a t i o n s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
M2080/81/82
M2085/86/87
VCSO FEC PLL
WITH
A
UTO
S
WITCH
FOR
SONET/OTN
Integrated
Circuit
Systems, Inc.
P r e l i m i n a r y I n f o r m a t i o n
G
ENERAL
D
ESCRIPTION
The M2080/81/82 and M2085/86/87 are VCSO (Voltage
Controlled SAW Oscillator) based
clock PLLs designed for FEC clock
ratio translation in 10Gb optical
systems such as OC-192 or 10GbE.
They support FEC (Forward Error
Correction) clock multiplication
ratios, both forward (mapping) and
inverse (de-mapping). Multiplication ratios are
pin-selected from pre-programming look-up tables.
F
EATURES
Integrated SAW delay line; Output of 15 to 700 MHz
*
Low phase jitter < 0.5 ps rms typical
(12kHz to 20MHz or 50kHz to 80MHz)
LVPECL clock output (CML and LVDS options available)
Pin-selectable PLL divider ratios support FEC ratios
M2080/85: OTU1 (255/238) and OTU2 (255/237) Mapping
M2081/86: OTU1 (238/255) or OTU2 (237/255) De-mapping
M2082/87: OTU1 (238/255) and OTU2 (237/255) De-mapping
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
Loss of Lock (LOL) output pin; Narrow Bandwidth
control input (NBW pin)
AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure
Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
Options for Hitless Switching (HS) with or without
Phase Build-out (PBO) to enable SONET (GR-253) /SDH
(G.813) MTIE and TDEV compliance during reselection
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
Figure 1: Pin Assignment
* Specify VCSO center frequency at time of order.
S
IMPLIFIED
B
LOCK
D
IAGRAM
Figure 2: Simplified Block Diagram
Example I/O Clock Frequency Combinations
Using M2081-11-622.0800 FEC De-Map Ratios
FEC De-Map
PLL Ratio
Mfec / Rfec
Base Input Rate
1
(MHz)
Note 1: Input reference clock can be the base frequency shown
divided by "Mfin" (as shown in Tables 3 and 4 on pg. 3).
Output Clock
(either output)
MHz
1/1
622.0800
622.08
or
155.52
237/255
666.5143
238/255
669.3266
Table 1: Example I/O Clock Frequency Combinations
M 2 0 8 0
S e r i e s
( T o p V i e w )
18
17
16
15
14
13
12
11
10
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
FIN
_
SEL
1
GND
P_
SEL2
DI
F
_
RE
F0
nD
I
F
_
R
EF0
R
E
F
_
SEL
DI
F
_
RE
F1
nD
I
F
_
R
EF1
VC
C
P_SEL0
P_SEL1
nFOUT
FOUT
GND
REF_ACK
AUTO
VCC
GND
FIN_SEL0
FEC_SEL0
FEC_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
nOP
_
I
N
OP
_OUT
VC
nVC
nO
P_
O
U
T
OP
_I
N
GND
GND
GND
19
20
21
22
23
24
25
26
27
Loop Filter
PLL
Phase
Detector
FEC_SEL1:0
FIN_SEL1:0
Rfec
Div
MUX
0
REF_SEL
DIF_REF0
nDIF_REF0
1
Mfin Divider
LUT
Mfec Div
P_SEL2:0
NBW
Mfec / Rfec Divider
LUT
DIF_REF1
nDIF_REF1
Auto
Ref Sel
0
1
LOL Phase
Detector
REF_ACK
AUTO
M2080 Series
2
VCSO
Mfin Divider
(1, 4, 8, 32 or
1, 4, 8, 16)
P Divider
LUT
LOL
3
2
FOUT
nFOUT
Tri-state
P Divider
(1, 4, 8, 32 or TriState)
M2080/81/82 VCSO FEC PLL with AutoSwitch for SONET/OTN
M2080/81/82 M2085/86/87 Datasheet Rev 0.4
2 of 14
Revised 30Jul2004
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
N e t w o r k i n g & C o m m u n i c a t i o n s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
Integrated
Circuit
Systems, Inc.
M2080/81/82, M2085/86/87
VCSO FEC PLL
WITH
A
UTO
S
WITCH
FOR
SONET/OTN
P r e l i m i n a r y I n f o r m a t i o n
P
IN
D
ESCRIPTIONS
Number
Name
I/O
Configuration
Description
1, 2, 3, 10, 14, 26
GND
Ground
Power supply ground connections.
4
9
OP_IN
nOP_IN
Input
External loop filter connections.
See Figure 5, External Loop Filter, on pg. 9.
5
8
nOP_OUT
OP_OUT
Output
6
7
nVC
VC
Input
11, 19, 33
VCC
Power
Power supply connection, connect to +
3.3
V.
12
AUTO
Input
Internal pull-down resistor
1
Automatic/manual reselection mode for clock input:
Logic
1
automatic reselection upon clock failure
(non-revertive)
Logic
0
manual selection only (using
REF_SEL
)
13
REF_ACK
Output
Reference Acknowledgement pin for input mux state; outputs
the currently selected reference input pair:
Logic
1
indicates
nDIF_REF1, DIF_REF1
Logic
0
indicates
nDIF_REF0, DIF_REF0
15
16
FOUT
nFOUT
Output
No internal terminator
Clock output pair. Differential LVPECL.
17
18
25
P_SEL1
P_SEL0
P_SEL2
Input
Internal pull-down resistor
1
Note 1: For typical values of internal pull-down and pull-UP resistors, see
DC Characteristics on pg. 11.
Post-PLL , P divider selection. LVCMOS/LVTTL. See Table 8,
P Divider Look-Up Table (LUT),
on
pg. 4.
20
nDIF_REF1
Input
Biased to Vcc/2
2
Note 2: Biased toVcc/2, with 50k
to Vcc and 50k
to ground. See Differential Inputs Biased to VCC/2 on pg. 11.
Reference clock input pair 1. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
21
DIF_REF1
Internal pull-down resistor
1
22
REF_SEL
Input
Internal pull-down resistor
1
Reference clock input selection. LVCMOS/LVTTL:
Logic
1
selects
DIF_REF1, nDIF_REF1.
Logic
0
selects
DIF_REF0, nDIF_REF0
.
23
nDIF_REF0
Input
Biased to Vcc/2
2
Reference clock input pair 0. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
24
DIF_REF0
Internal pull-down resistor
1
27
28
FIN_SEL1
FIN_SEL0
Input
Internal pull-down resistor
1
I
nput clock frequency selection. LVCMOS/LVTTL. See
Tables
3
and
4
Mfin Divider Look-Up Tables (LUT)
on
pg. 3.
29
30
FEC_SEL0
FEC_SEL1
Input
Internal pull-down resistor
1
Mfec and Rfec divider value selection. LVCMOS/ LVTTL.
See Tables 5, 6, and
7 on
pg. 3.
31
LOL
Output
Loss of Lock indicator output. Asserted when internal PLL is
not tracking the input reference for frequency and phase.
3
Logic
1
indicates loss of lock.
Logic
0
indicates locked condition.
Note 3: See LVCMOS Outputs in
DC Characteristics on pg. 11.
32
NBW
Input
Internal pull-UP resistor
1
Narrow Bandwidth enable. LVCMOS/LVTTL:
Logic
1
- Narrow loop bandwidth
, R
IN
= 2100k
.
Logic
0
- Wide bandwidth
, R
IN
= 100k
.
34, 35, 36
DNC
Do Not Connect.
Table 2: Pin Descriptions
M2080/81/82 Datasheet Rev 0.4
3 of 14
Revised 30Jul2004
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
N e t w o r k i n g & C o m m u n i c a t i o n s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
M2080/81/82, M2085/86/87
VCSO FEC PLL
WITH
A
UTO
S
WITCH
FOR
SONET/OTN
P r e l i m i n a r y I n f o r m a t i o n
Integrated
Circuit
Systems, Inc.
D
ETAILED
B
LOCK
D
IAGRAM
Figure 3: Detailed Block Diagram
D
IVIDER
S
ELECTION
T
ABLES
Mfin Divider Look-Up Tables (LUT)
The
FIN_SEL1:0
pins select the feedback divider value
("Mfin"), which sets the overall PLL ratio range. Since
the VCSO frequency is fixed, this allows input reference
selection. The look-up tables vary by device variant.
M2080/81/82: Mfin Value LUT (Includes Divide by 32)
M2085/86/87: Mfin Value LUT (Includes Divide by 16)
Mfec and Rfec Divider Look-Up Tables (LUTs)
The
FEC_SEL
pins select the Mfec/Rfec divider ratio. The
look-up tables vary by device variant. The Mfec and
Rfec values also establish phase detector frequency.
A lower phase detector frequency improves jitter
tolerance and lowers loop bandwidth.
M2080/85: FEC Map LUT, OTU1 (255/238) and OTU2 (255/237)
M2081/86: FEC De-map LUT, OTU1 (238/255) or OTU2 (237/255)
Use this option for either OTU1 or OTU2 de-mapping
applications, but not both.
Phase
Locked
Loop
(PLL)
M2080 Series
SAW Delay Line
Phase
Shifter
VCSO
C
POST
C
POST
VC
nVC
R
POST
nOP_OUT
OP_OUT
R
POST
R
LOOP
R
LOOP
C
LOOP
C
LOOP
OP_IN
nOP_IN
PLL
Phase
Detector
Loop Filter
Amplifier
External
Loop Filter
Components
FEC_SEL1:0
FIN_SEL1:0
Rfec
Div
MUX
0
REF_SEL
DIF_REF0
nDIF_REF0
1
Mfin Divider
LUT
Mfin Divider
(1, 4, 8, 32) or
(1, 4, 8, 16)
Mfec Div
NBW
R
IN
R
IN
Mfec / Rfec
Divider LUT
DIF_REF1
nDIF_REF1
Auto
Ref Sel
0
1
LOL
Phase
Detector
REF_ACK
AUTO
LOL
FOUT
nFOUT
CML or PECL
Options
P Divider
(1, 4, 8, 32,
or TriState)
P_SEL2:0
P Divider
LUT
2
2
3
FIN_SEL1:0
Mfin
Value
Sample Input Reference Freq. (MHz) Options
For M2080
1
, M2081 & M2082
2
Note 1: For M2080 with Fvcso = 666.5143 or 669.3266
Note 2: For M2081 and M2082 with Fvcso = 622.0800.
0 0
32
19.44
0 1
8
77.76
1 0
4
155.52
1 1
1
622.08
Table 3: M2080/81/82: Mfin Value LUT (Includes Divide by 32)
FIN_SEL1:0
Mfin
Value
Sample Input Reference Freq. (MHz) Options
For M2085
1
, M2086 & M2087
2
Note 1: For M2085 with Fvcso = 666.5143 or 669.3266
Note 2: For M2086 and M2087 with Fvcso = 622.0800.
0 0
16
38.88
0 1
8
77.76
1 0
4
155.52
1 1
1
622.08
Table 4: M2085/86/87: Mfin Value LUT (Includes Divide by 16)
FEC_SEL1:0
1 0
Mfec Rfec
Description
Base Input
Rate (MHz)
Fvcso =
Base Output
Rate (MHz)
For M2080 or M2085 with Fvcso = 666.5143 (OTU1 FEC rate):
0 0
15 14
255/238 OC-48 to OTU1 encode
622.08
666.5143
0 1
15 15
OTU1 repeater or jitter attenuator
666.5143 666.5143
For M2080 or M2085 with Fvcso = 669.3266 (OTU2 FEC rate):
1 0
85 79
255/237 OC-192 to OTU2 encode
622.08
669.3266
1 1
85 85
OTU2 repeater or jitter attenuator
669.3266 669.3266
Table 5: M2080/85: FEC Map LUT, OTU1 (255/238) and OTU2 (255/237)
FEC_SEL1:0
1 0
Mfec Rfec
Description
Base Input
Rate (MHz)
Fvcso =
Base Output
Rate (MHz)
For M2081 or M2086 with Fvcso = 622.08 (OTU1 or OTU2 FEC rate):
0 0
79 85
237/255 OTU2 to OC-192 decode
669.3266
622.08
0 1
79 79
OC-192 repeater or jitter attenuator
622.08
622.08
1 0
14 15
238/255 OTU1 to OC-48 decode
666.5143
622.08
1 1
14 14
OC-48 repeater or jitter attenuator
622.08
622.08
Table 6: M2081/86: FEC De-map LUT, OTU1 (238/255) or OTU2 (237/255)
M2080/81/82 M2085/86/87 Datasheet Rev 0.4
4 of 14
Revised 30Jul2004
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
N e t w o r k i n g & C o m m u n i c a t i o n s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
Integrated
Circuit
Systems, Inc.
M2080/81/82, M2085/86/87
VCSO FEC PLL
WITH
A
UTO
S
WITCH
FOR
SONET/OTN
P r e l i m i n a r y I n f o r m a t i o n
M2082/87: FEC De-map LUT, Both OTU1 and OTU2
Use this option for both OTU1 or OTU2 de-mapping
applications. The Mfec divider value is kept nearly
constant to maintain similar loop bandwidth using one
set of external filter component values.
P Divider Look-Up Table (LUT)
The
P_SEL2:0
pins select the P divider values, which set
the output clock frequency. A P divider of value of
1
will
provide a
622.08MHz
output when using a
622.08MHz
VCSO, for example. P divider values of
4
,
8
, or
32
are
also available, plus a TriState mode. The output can be
placed into the valid states as listed in Table 8.
General Guidelines for Phase Detector Frequency
The phase detector frequency (Fpd) is equal to the
input reference frequency (Fref) divided by the Rfec
divider value, or:
Fpd = Fref / Rfec
A lower phase detector frequency should be used for
loop timing applications to assure PLL tracking,
especially during GR-253 jitter tolerance testing. The
recommended maximum phase detector frequency
for loop timing mode is
19.44
MHz.
When
LOL
is to be used for system health monitoring,
the phase detector frequency should be 5MHz or
greater. Low phase detector frequencies make
LOL
overly sensitive, and higher phase detector
frequencies make
LOL
less sensitive. The
LOL
pin
should not be used during loop timing mode.
The preceding guideline also applies when using the
AutoSwitch Mode, since AutoSwitch uses the
LOL
output for clock fault detection.
F
UNCTIONAL
D
ESCRIPTION
The M208x Series is a PLL (Phase Locked Loop) based
clock generator that generates output clocks synchro-
nized to one of two selectable input reference clocks.
An internal high "Q" SAW delay line provides low jitter
signal performance and establishes the output
frequency of the VCSO (Voltage Controlled SAW
Oscillator). In a given M208x Series device, the VCSO
center frequency is fixed. A common center frequency
is
622.08MHz,
for SONET or SDH optical network
applications. The VCSO center frequency is specified at
time of order (see "Ordering Information" on pg. 14).
The VCSO has a guaranteed tuning range of
120 ppm
(commercial temperature grade).
Pin selectable dividers are used within the PLL and
for the output clock. This enables tailoring of device
functionality and performance. The FEC feedback and
reference dividers (the "Mfec Divider" and "Rfec
Divider") provide the multiplication ratios necessary to
accomodate clock translation for both forward and
inverse Forward Error Correction. The Mfec and Rfec
dividers also control the phase detector frequency. The
feedback divider (labeled "Mfin Divider") provides the
broader division options needed to accomodate various
reference clock frequencies.
For example, the
M2082-11-622.0800
(see "Ordering
Information"
on pg. 14
)
has a
622.08
MHz VCSO
frequency:
The FEC de-mapper PLL ratios (in Tables 6 and 7)
enable the
M2082-11-622.0800
to accept "base" input
reference frequencies of:
666.5143 (OTU1)
,
669.3266
(OTU2)
, and
622.08
MHz
(OC-192)
.
The Mfin feedback divider enables the actual input
reference clock to be the base input frequency
divided by
1
,
4
,
8
, or
32 or 16
. Therefore, for the base
input frequency of
622.08
MHz, the actual input
reference clock frequencies can be:
622.08
,
155.52
,
77.76
, and
19.44 or 38.88
MHz. (See Tables 3 and 4 on
pg. 3.)
The P divider scales the VCSO output enabling lower
output frequency selections (Table 8).
FEC_SEL1:0
1 0
Mfec Rfec
Description
Base Input
Rate (MHz)
Fvcso =
Base Output
Rate (MHz)
For M2082 or M2087 with Fvcso = 622.08 (OTU1 or OTU2 FEC rate):
0 0
79 85
237/255 OTU2 to OC-192 decode
669.3266
622.08
0 1
79 79
OC-192 repeater or jitter attenuator
622.08
622.08
1 0
84 90
238/255 OTU1 to OC-48 decode
666.5143
622.08
1 1
84 84
OC-48 repeater or jitter attenuator
622.08
622.08
Table 7: M2082/87: FEC De-map LUT, Both OTU1 and OTU2
P_SEL2:0
P Value
M2080-622.0800 or M2085-622.0800
Output Frequency (MHz)
0 0 0
32
19.44
0 0 1
32
19.44
0 1 0
1
622.08
0 1 1
4
155.52
1 0 0
8
77.76
1 0 1
4
155.52
1 1 0
8
77.76
1 1 1
TriState
N/A
Table 8: P Divider Look-Up Table (LUT)
Key to Device Variants and Look-up Table Options
Device
Variant
Look-up Table Option
Mfin Lookup Table is:
Mfec Look-up Table is:
M2080
Table 3
(includes divider value 32)
Table 5
(FEC mapper LUT)
M2081
Table 6
(FEC de-mapper LUT)
M2082
Table 7
(FEC de-mapper LUT)
M2085
Table 4
(includes divider value 16)
Table 5
(FEC mapper LUT)
M2086
Table 6
(FEC de-mapper LUT)
M2087
Table 7
(FEC de-mapper LUT)
Table 9: Key to Device Variants and Look-up Table Options
M2080/81/82 Datasheet Rev 0.4
5 of 14
Revised 30Jul2004
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
N e t w o r k i n g & C o m m u n i c a t i o n s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
M2080/81/82, M2085/86/87
VCSO FEC PLL
WITH
A
UTO
S
WITCH
FOR
SONET/OTN
P r e l i m i n a r y I n f o r m a t i o n
Integrated
Circuit
Systems, Inc.
The M208x Series includes a Loss of Lock (
LOL
)
indicator, which provides status information to system
management software. A Narrow Bandwidth (
NBW
)
control pin is provided as an additional mechanism for
adjusting PLL loop bandwidth without affecting the
phase detector frequency.
Options are available for Hitless Switching (HS) with or
without Phase Build-out (PBO). They provide SONET/
SDH MTIE and TDEV compliance during a reference
clock reselection.
Input Reference Clocks
Two clock reference inputs and a selection mux are
provided. Either reference clock input can accept a
differential clock signal (such as LVPECL or LVDS) or
a single-ended clock input (LVCMOS or LVTTL on the
non-inverting input).
A single-ended reference clock on the unselected
reference input can cause an increase in output
clock jitter. For this reason, differential reference
inputs are preferred; interference from a differential
input on the non-selected input is minimal.
Configuration of a single-ended input has been
facilitated by biasing
nDIF_REF0
and
nDEF_REF1
to Vcc/2,
with 50k
to Vcc and 50k to ground. The input clock
structure, and how it is used with either
LVCMOS/LVTTL inputs or a DC- coupled LVPECL
clock, is shown in Figure 4.
.
Figure 4: Input Reference Clocks
Differential Inputs
Differential LVPECL inputs are connected to both
reference input pins in the usual manner. The external
load termination resistors shown in Figure 4 (the
127
and
82
resistors) is ideally suited for both AC and DC
coupled LVPECL reference clock lines. These provide
the
50
load termination and the VTT bias voltage.
Single-ended Inputs
Single-ended inputs (LVCMOS or LVTTL) are
connected to the non-inverting reference input pin
(
DIF_REF0
or
DIF_REF1
). The inverting reference input pin
(
nDIF_REF0
or
nDIF_REF1
) must be left unconnected.
In single-ended operation, when the unused inverting
input pin (nDIF_REF0 or nDEF_REF1) is left floating (not
connected), the input will self-bias at VCC/2.
PLL Operation
The M2080/81/82 and M2085/86/87 are complete clock
PLLs. They use a phase detector and configurable
dividers to synchronize the output of the VCSO with the
selected reference clock.
The M208x Series components are similar to the
M2060 Series components except that the M208x
Series includes the selectable AutoSwitch feature. The
M208x Series also has only one clock output, as the
AutoSwitch control pins replace of the second output.
The PLL will work correctly, meaning it will phase-lock
the VCSO output to the input reference clock, when the
internal phase detector inputs are able to run at the
same frequency. This means the PLL dividers must be
set appropriately and a suitable reference frequency
must be chosen for the intended output frequency.
When the PLL is not set up appropriately, the VCSO is
forced to its upper or lower operating limit which is typi-
cally about 200 ppm above or below the VCSO center
frequency. See "APR, VCSO Absolute Pull-Range" row,
in the AC Characteristics table on pg. 12.
In normal phase-locked condition, the instantaneous
phase error is measured by the phase detector and is
converted to charge pump current pulses. These
current pulses are then integrated by the external loop
filter to create a VCSO control voltage. The loop filter
acts as a low pass filter to remove unwanted reference
clock jitter above a determined frequency or PLL
bandwidth. For reference phase jitter frequencies within
the loop bandwidth, phase jitter amplitude is passed on
to the output clock according to the PLL loop frequency
response curve.
MUX
0
REF_SEL
1
VCC
50k
50k
VCC
50k
50k
LVCMOS/
LVTTL
LVPECL
50k
50k
VCC
82
127
VCC
82
127
X
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
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