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Datasheet: IBM0418A11QLAA-3 (IBM)

 

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IBM
nrrh3316.01
08/03/2001
ŠIBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 25
IBM0436A11QLAA
IBM0418A11QLAA
Preliminary
1Mb (32Kx36 & 64Kx18) SRAM
Features
ˇ 32Kx36 or 64Kx18 organizations
ˇ 0.25 Micron CMOS technology
ˇ Synchronous Pipeline Mode of Operation with
Self-Timed Late Write
ˇ Single Differential Extended HSTL Clock
ˇ +3.3V Power Supply, Ground, 1.5V V
DDQ
, and
0.75V V
REF or
1.8V V
DDQ
, and 0.9V V
REF
ˇ HSTL Input and Outputs
ˇ Registered Addresses, Write Enables, Synchro-
nous Select, and Data Ins
ˇ Registered Outputs
ˇ Common I/O
ˇ Asynchronous Output Enable and Power Down
Inputs
ˇ Boundary Scan using limited set of JTAG
1149.1 functions
ˇ Byte Write Capability and Global Write Enable
ˇ 7 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
ˇ Programmable Impedance Output Drivers
ˇ Synchronous Sleep Mode
Description
IBM0436A11QLAA and IBM0418A11QLAA are 1Mb
Synchronous Pipeline Mode, high-performance
CMOS Static Random Access Memories (SRAM).
These SRAMs are versatile, have a wide input/out-
put (I/O) interface, and can achieve cycle times as
short as 3ns. Differential K clocks are used to initiate
the read/write operation; all internal operations are
self-timed. At the rising edge of the K clock, all
address, write-enables, sync select, and data input
signals are registered internally. Data outputs are
updated from output registers off the next rising
edge of the K clock. An internal write buffer allows
write data to follow one cycle after addresses and
controls. The device is operated with a single +3.3V
power supply and is compatible with HSTL I/O inter-
faces.
.
IBM0436A11QLAA
IBM0418A11QLAA
1Mb (32Kx36 & 64Kx18) SRAM
Preliminary
ŠIBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 2 of 25
nrrh3316.01
08/03/2001
x36 BGA Pinout (Top View)
1
2
3
4
5
6
7
A
V
DDQ
SA10
SA9
NC
SA3
SA4
V
DDQ
B
NC
NC
NC
NC
NC
NC
NC
C
NC
SA11
SA8
V
DD
SA2
SA5
NC
D
DQ23
DQ18
V
SS
ZQ
V
SS
DQ9
DQ14
E
DQ19
DQ24
V
SS
SS
V
SS
DQ15
DQ10
F
V
DDQ
DQ20
V
SS
G
V
SS
DQ11
V
DDQ
G
DQ21
DQ25
SBWc
C*
SBWb
DQ16
DQ12
H
DQ26
DQ22
V
SS
C*
V
SS
DQ13
DQ17
J
V
DDQ
V
DD
V
REF
V
DD
V
REF
V
DD
V
DDQ
K
DQ35
DQ31
V
SS
K
V
SS
DQ4
DQ8
L
DQ30
DQ34
SBWd
K
SBWa
DQ7
DQ3
M
V
DDQ
DQ29
V
SS
SW
V
SS
DQ2
V
DDQ
N
DQ28
DQ33
V
SS
SA0
V
SS
DQ6
DQ1
P
DQ32
DQ27
V
SS
SA1
V
SS
DQ0
DQ5
R
NC
SA14
M1*
V
DD
M2*
SA6
NC
T
NC
NC
SA13
SA12
SA7
NC
ZZ
U
V
DDQ
TMS
TDI
TCK
TDO
NC
V
DDQ
* M1 and M2 are read protocol mode pins. For this application, M1 and M2 must be connected to V
SS
and V
DD
, respectively.
C-clocks must be left floating for all single-clock read protocols.
x18 BGA Pinout (Top View)
1
2
3
4
5
6
7
A
V
DDQ
SA10
SA9
NC
SA3
SA4
V
DDQ
B
NC
NC
NC
NC
NC
NC
NC
C
NC
SA11
SA8
V
DD
SA2
SA5
NC
D
DQ14
NC
V
SS
ZQ
V
SS
DQ0
NC
E
NC
DQ15
V
SS
SS
V
SS
NC
DQ1
F
V
DDQ
NC
V
SS
G
V
SS
DQ2
V
DDQ
G
NC
DQ16
SBWb
C*
V
ss
,NC
NC
DQ3
H
DQ17
NC
V
SS
C*
V
SS
DQ4
NC
J
V
DDQ
V
DD
V
REF
V
DD
V
REF
V
DD
V
DDQ
K
NC
DQ13
V
SS
K
V
SS
NC
DQ8
L
DQ12
NC
V
ss
,NC
K
SBWa
DQ7
NC
M
V
DDQ
DQ11
V
SS
SW
V
SS
NC
V
DDQ
N
DQ10
NC
V
SS
SA0
V
SS
DQ6
NC
P
NC
DQ9
V
SS
SA1
V
SS
NC
DQ5
R
NC
SA14
M1
V
DD
M2
SA6
NC
T
NC
SA15
SA13
NC
SA7
SA12
ZZ
U
V
DDQ
TMS
TDI
TCK
TDO
NC
V
DDQ
* M1 and M2 are read protocol mode pins. For this application, M1 and M2 must be connected to V
SS
and V
DD
respectively.
C-clocks must be left floating for all single-clock read protocols.
IBM0436A11QLAA
IBM0418A11QLAA
Preliminary
1Mb (32Kx36 & 64Kx18) SRAM
nrrh3316.01
08/03/2001
ŠIBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 25
Pin Description
SA0-SA15
Address Input
G
Asynchronous Output Enable
DQ0-DQ35
Data I/O
SS
Synchronous Select
K, K
Differential Input-Register Clocks
M1, M2
Mode Inputs. Selects Read Protocol Operation.
SW
Write Enable, Global
V
REF
(2)
GTL/HSTL Input Reference Voltage
SBWa
Write Enable, Byte a (DQ0-DQ8)
V
DC
Power Supply (+3.3V)
SBWb
Write Enable, Byte b (DQ9-DQ17)
V
SS
Ground
SBWc
Write Enable, Byte c (DQ18-DQ26)
V
DDQ
Output Power Supply
SBWd
Write Enable, Byte d (DQ27-DQ35)
ZZ
Synchronous Sleep Mode
TMS,TDI,TCK
IEEE
Ž
1149.1 Test Inputs (LVTTL levels)
ZQ
Output Driver Impedance Control
TDO
IEEE 1149.1 Test Output (LVTTL level)
NC
No Connect
Ordering Information
Part Number
Organization
Speed
Leads
IBM0418A11QLAA - 3
64Kx18
1.7ns Access / 3.0ns Cycle
7 x 17 BGA
IBM0418A11QLAA - 3N
64Kx18
1.85ns Access / 3.7ns Cycle
7 x 17 BGA
IBM0418A11QLAA - 4
64Kx18
2.0ns Access / 4.0ns Cycle
7 x 17 BGA
IBM0436A11QLAA - 3
32Kx36
1.7ns Access / 3.0ns Cycle
7 x 17 BGA
IBM0436A11QLAA - 3N
32Kx36
1.85ns Access / 3.7ns Cycle
7 x 17 BGA
IBM0436A11QLAA - 4
32Kx36
2.0ns Access / 4.0ns Cycle
7 x 17 BGA
IBM0436A11QLAA
IBM0418A11QLAA
1Mb (32Kx36 & 64Kx18) SRAM
Preliminary
ŠIBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 4 of 25
nrrh3316.01
08/03/2001
Block Diagram
SBW
Ro
w De
co
d
e
Col Decode
Read/Wr Amp
DOC_Array0
SA0-SA18
K
ZZ
G
SW
SS
DQ0-DQ35
REG
REG
SB
W
2:
1
M
U
X
DOC_MUX0
WRI
T
E1
A
DD REG
WRI
T
E
0
ADD REG
RE
AD
AD
D REG
REA
D
WRI
T
E
MA
TC
H
MA
TC
H
1
LATCH
LATCH0
WR
_
B
U
F
1
WR
_
B
U
F
0
2:1 MUX
DOC_MUX1
2:1 MUX
DOC_MUX2
SB
W0
SW0
SW1
REG
REG
DOC_
DOUT0
REG
REG
SS1
SS0
IBM0436A11QLAA
IBM0418A11QLAA
Preliminary
1Mb (32Kx36 & 64Kx18) SRAM
nrrh3316.01
08/03/2001
ŠIBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 25
SRAM Features
Late Write
The Late Write function allows for write data to be registered one cycle after addresses and controls. This fea-
ture eliminates one bus-turnaround cycle, necessary when going from a read to a write operation. Late Write
is accomplished by buffering write addresses and data so that the write operation occurs during the next write
cycle. When a read cycle occurs after a write cycle, the address and write data information are stored tempo-
rarily in holding registers. During the first write cycle preceded by a read cycle, the SRAM array is updated
with address and data from the holding registers. Read cycle addresses are monitored to determine if read
data is to be supplied from the SRAM array or the write buffer. The bypassing of the SRAM array occurs on a
byte-by-byte basis. When only one byte is written during a write cycle, read data from the last written address
has new byte data from the write buffer and remaining bytes from the SRAM array.
Mode Control
Mode control pins M1 and M2 are used to select four different JEDEC-standard read protocols. This SRAM
supports single clock, pipeline operation (M1 = V
SS
, M2 = V
DD
). This datasheet describes single clock pipe-
line functionality only. Mode control inputs must be set at power up and must not change during SRAM oper-
ation. This SRAM is tested only in the pipeline mode.
Sleep Mode
The sleep mode is enabled by switching the synchronous ZZ signal High. When the SRAM is in the sleep
mode, the outputs go to a High-Z state and the SRAM draws standby current. SRAM data is preserved and a
recovery time (t
ZZR
) is required before the SRAM resumes normal operation.
RQ Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V
SS
to enable the SRAM
to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance
driven by the SRAM; each SRAM requires a dedicated RQ. The allowable range of RQ to ensure impedance
matching is between 175
and 350, with the tolerance described in Programmable Impedance Output
Driver DC Electrical Characteristics on page 9. The RQ resistor should be placed less than two inches away
from the ZQ ball on the SRAM module. The total external capacitance (including wiring) seen by the ZQ ball
should be minimized (less than 7.5 pF).
Programmable Impedance/Power-Up Requirements
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by
drifts in supply voltage and temperature. One evaluation occurs every 64 clock cycles and each evaluation
can only move the output driver impedance level one step at a time towards the optimum level. The output
driver has 32 discrete binary weighted steps. The impedance update of the output driver occurs when the
SRAM is in High-Z. Write and Deselect operations will synchronously switch the SRAM into and out of High-
Z, triggering an update. The user can invoke asynchronous G updates by providing a G setup and hold about
the K clock to ensure the proper update. There are no power-up requirements for programmable impedance
initialization of the SRAM; however, to ensure optimum output driver impedance after power up, the SRAM
needs 4096 clock cycles followed by a Low-Z to High-Z transition.
Power-Up/Power-Down Sequencing
The power supplies must be powered up in the following order: V
DD
, V
DDQ
, V
REF
, and Inputs. The power-
down sequence must be in the reverse order. V
DDQ
may not exceed V
DD
by more than 0.6V at any time.
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