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Datasheet: HI-1574PST (Holt Integrated Circuits)

MIL-STD-1553/1760 Monolithic Dual 3.3V Transceivers

 

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Holt Integrated Circuits
HOLT INTEGRATED CIRCUITS
www.holtic.com
HI-1573, HI-1574
MIL-STD-1553
3.3V Monolithic Dual Transceivers
DESCRIPTION
FEATURES
PIN CONFIGURATIONS
The HI-1573 and HI-1574 are low power CMOS dual
transceivers designed to meet the requirements of the
MIL-STD-1553 specification.
The transmitter section of each channel takes
complementary CMOS / TTL digital input data and converts
it to bi-phase Manchester encoded 1553 signals suitable
for driving the bus isolation transformer. Separate
transmitter inhibit control signals are provided for each
transmitter.
The receiver section of the each channel converts the 1553
bus bi-phase data to complementary CMOS / TTL data
suitable for inputting to a Manchester decoder. Each
receiver has a separate enable input which can be used to
force the output of the receiver to a logic "0" (HI-1573) or
logic 1 (HI-1574).
To minimize the package size for this function, the
transmitter outputs are internally connected to the receiver
inputs, so that only two pins are required for connection to
each coupling transformer. For designs requiring
independent access to transmitter and receiver 1553
signals, please contact your Holt Sales representative.
VDDA 1
BUSA 2
3
RXENA 4
GNDA 5
VDDB 6
BUSB 7
8
RXENB 9
GNDB 10
BUSA
BUSB
!
!
!
!
!
!
!
Compliant to MIL-STD-1553A & B,
ARINC 708A
3.3V single supply operation
Less than 0.5W maximum power dissipation
Also available in DIP and small outline
(ESOIC) package options
Military processing options
Industry standard pin configurations
Smallest footprint available in 44-pin plastic
7 mm x 7 mm chip-scale package with integral
heatsink
20 Pin Ceramic DIP package
20
19 TXA
18 TXINHA
17 RXA
16
15
14 TXB
13 TXINHB
12 RXB
11
TXA
RXA
TXB
RXB
20 Pin Plastic ESOIC - WB package
May 2003
(DS1573 Rev.D)
05/03
1573CDI
1573CDT
1573CDM
1574CDI
1574CDT
1574CDM
1573PSI
1573PST
1573PSM
1574PSI
1574PST
1574PSM
1
BUSA 2
3
RXENA 4
GNDA 5
VDDB 6
BUSB 7
8
RXENB 9
GNDB 10
VDDA
BUSA
BUSB
20
19 TXA
18 TXINHA
17 RXA
16
15
14 TXB
13 TXINHB
12 RXB
11
TXA
RXA
TXB
RXB
PIN CONFIGURATIONS
44
-
43
42
41
BUSA
40
BUSA
39
VDDA
38
VDDA
37
36
TXA
35
-
34
-
BUSA
BUSA
TXA
-
1
RXENA 2
GNDA 3
GNDA 4
GNDA 5
VDDB 6
VDDB 7
BUSB 8
BUSB 9
10
11
BUSB
BUSB
33 -
32 -
31 TXINHA
30 RXA
29
28 -
27 -
26
25 TXB
24 TXINHB
23 -
RXA
TXB
-1
2
-1
3
-1
4
-1
5
RXENB
16
GNDB
17
GNDB
18
GNDB
19
20
RXB
21
-2
2
RXB
1573PCI
1573PCT
1574PCI
1574PCT
44 Pin Plastic 7mm x 7mm
Chip-scale package
HOLT INTEGRATED CIRCUITS
2
PIN
SYMBOL
FUNCTION
DESCRIPTION
(DIP & SOIC)
1
VDDA
power supply
+3.3 volt power for channel A
2
BUSA
analog output
MIL-STD-1533 bus driver A, positive signal
3
analog output
MIL-STD-1553 bus driver A, negative signal
4
RXENA
digital input
Receiver A enable. If low, forces RXA and
low (HI-1573) or High (HI-1574)
5
GNDA
power supply
Ground for channel A
6
VDDB
7
BUSB
9
RXENB
10
GNDB
11
12
RXB
digital output
Receiver B output, non-inverted
13
TXINHB
digital input
Transmit inhibit, channel B. If high BUSB,
disabled
14
TXB
digital input
Transmitter B digital data input, non-inverted
15
digital input
Transmitter B digital data input, inverted
16
digital output
BUSA
RXA
BUSB
TXB
RXA
power supply
+3.3 volt power for channel B
analog output
MIL-STD-1533 bus driver B, positive signal
8
analog output
MIL-STD-1553 bus driver B, negative signal
digital input
Receiver B enable. If low, forces RXB and
low (HI-1573) or High (HI-1574)
power supply
Ground for channel B
digital output
Receiver B output, inverted
Receiver A output, inverted
17
RXA
digital output
Receiver A output, non-inverted
18
TXINHA
digital input
Transmit inhibit, channel A. If high BUSA,
disabled
19
TXA
digital input
Transmitter A digital data input, non-inverted
20
digital input
Transmitter A digital data input, inverted
BUSB
RXB
RXB
BUSA
TXA
PIN DESCRIPTIONS
FUNCTIONAL DESCRIPTION
The HI-1573 family of data bus transceivers contains differ-
ential voltage source drivers and differential receivers.
They are intended for applications using a MIL-STD-1553
A/B data bus. The device produces a trapezoidal output
waveform during transmission.
Data input to the device's transmitter section is from the
complementary CMOS inputs TXA/B and
/ .
The
transmitter accepts Manchester II bi-phase data and con-
verts it to differential voltages on
.
The transceiver outputs are either direct or transformer
coupled to the MIL-STD-1553 data bus.
Both coupling
methods produce a nominal voltage on the bus of 7.5 volts
peak to peak.
TRANSMITTER
TXA B
BUSA/B and
/
The transmitter is automatically inhibited and placed in the
high impedance state when both TXA/B and
/ are ei-
ther at a logic "1" or logic "0" simultaneously. A logic "1" ap-
plied to the TXINHA/B input will force the transmitter to the
high impedance state, regardless of the state of TXA/B and
/
BUSA B
TXA B
TXA B.
RECEIVER
The receiver accepts bi-phase differential data from the
MIL-STD-1553 bus through the same direct or transformer
coupled interface as the transmitter. The receiver's differ-
ential input stage drives a filter and threshold comparator
that produces CMOS data at the RXA/B and
/ output
pins.
RXA B
Each set of receiver outputs can be independently forced
to a logic "0" (HI-1573) or logic "1" (HI-1574) by setting
RXENA or RXENB low.
A direct coupled interface (see Figure 2) uses a 1:2.5 ratio
isolation transformer and two 55 ohm isolation resistors
between the transformer and the bus.
In a transformer coupled interface (see Figure 3), the
transceiver is connected to a 1:1.79 isolation transformer
which in turn is connected to a 1:1.4 coupling transformer.
The transformer coupled method also requires two
coupling resistors equal to 75% of the bus characteristic
impedence (Zo) between the coupling transformer and the
bus.
MIL-STD-1553 BUS INTERFACE
HI-1573, HI-1574
HOLT INTEGRATED CIRCUITS
3
HI-1573, HI-1574
TRANSMIT WAVEFORM - EXAMPLE PATTERN
TXA/B
TXA/B
BUSA/B - BUSA/B
RECEIVE WAVEFORMS - EXAMPLE PATTERN
RXA/B
RXA/B
Vin
(Line to Line)
Figure 1. Block Diagram
TXA/B
TXA/B
TXINHA/B
RXA/B
RXA/B
RXENA/B
Each Channel
Transmit
Logic
Receive
Logic
Slope
Control
Comparator
Input
Filter
BUSA/B
BUSA/B
TRANSMITTER
RECEIVER
Data Bus
Isolation
Transformer
Coupler
Network
Direct or
Transformer
HOLT INTEGRATED CIRCUITS
4
HI-1573, HI-1574
NOTE:
Stresses above absolute maximum
ratings or outside recommended operating
conditions may cause permanent damage to the
device. These are stress ratings only. Operation
at the limits is not recommended.
Supply voltage (
Logic input voltage range
Power dissipation at 25C
1.0 W
ceramic DIL, derate
7mW/C
Solder Temperature
275C for 10 sec.
Junction Temperature
175C
Storage Temperature
-65C to +150C
VDD)
-0.3 V to +5 V
-0.3 V dc to +3.6 V
Receiver differential voltage
10 Vp-p
Driver peak output current
+1.0 A
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
Temperature Range
Industrial Screening.........-40C to +85C
Hi-Temp Screening........-55C to +125C
Military Screening..........-55C to +125C
VDD....................................... 3.3V... 5%
DC ELECTRICAL CHARACTERISTICS
VDD = 3.3 V, GND = 0V, T = Operating Temperature Range (unless otherwise specified).
A
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Operating Voltage
VDD
3.15
3.30
3.45
V
Total Supply Current
ICC1
Not Transmitting
4
10
mA
ICC2
Transmit one channel @
225
250
mA
50% duty cycle
ICC3
Transmit one channel @
0
mA
100% duty cycle
Power Dissipation
PD1
Not Transmitting
0.06
W
PD2
Transmit one channel @
0.3
0.5
W
100% duty cycle
Min. Input Voltage
(HI)
V
Digital inputs
70%
V
Max. Input Voltage
(LO)
V
Digital inputs
30%
V
Min. Input Current
(HI)
I
Digital inputs
20
A
Max. Input Current
(LO)
I
Digital inputs
-20
A
Min. Output Voltage
(HI)
V
I
= -1.0mA, Digital outputs
90%
V
Max. Output Voltage
(LO)
V
I
= 1.0mA, Digital outputs
10%
V
Input resistance
R
Differential
20
Kohm
Input capacitance
C
Differential
5
pF
Common mode rejection ratio
CMRR
40
dB
Input Level
V
Differential
9
Vp-p
Input common mode voltage
V
-5.0
5.0
V-pk
Threshold Voltage - Direct-coupled
Detect
1.15
20.0
No Detect
0.28
Theshold Voltage -
Detect
0.86
14.0
No Detect
0.20
425
50
V
1 Mhz Sine Wave
Vp-p
V
(Measured at Point "A " in Figure 2)
Vp-p
Transformer-coupled
V
1 MHz Sine Wave
Vp-p
V
(Measured at Point "A " in Figure 3)
Vp-p
=
IH
IL
IH
IL
OH
OUT
IH
OUT
D
DD
DD
DD
DD
RECEIVER
(Measured at Point "A " in Figure 2 unless otherwise specified)
IN
IN
IN
ICM
THD
THND
THD
THND
D
T
HOLT INTEGRATED CIRCUITS
5
HI-1573, HI-1574
DC ELECTRICAL CHARACTERISTICS (cont.)
VDD = 3.3 V, GND = 0V, T = Operating Temperature Range (unless otherwise specified).
A
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Receiver Enable Delay
tREN
From RXENA/B rising or falling edge to
40
ns
RXA/B or
Driver Delay
tDT
TXA/B, TXA/B to BUSA/B, BUSA/B
150
ns
Rise time
tr
35 ohm load
100
300
ns
Fall Time
tf
35 ohm load
100
300
ns
Inhibit Delay
tDI-H
Inhibited output
100
ns
tDI-L
Active output
150
ns
RECEIVER
TRANSMITTER
(Measured at Point "A " in Figure 2)
(Measured at Point "A " in Figure 2)
D
D
Receiver Delay
tDR
From input zero crossing to RXA/B or
450
ns
RXA/B
RXA/B
AC ELECTRICAL CHARACTERISTICS
VDD = 3.3 V, GND = 0V, T =Operating Temperature Range (unless otherwise specified).
A
TXA/B
TXA/B
TXINHA/B
TRANSMITTER
RECEIVER
1:2.5
Point "A "
D
55
W
55
W
35
W
2.5:1
55
W
55
W
35
W
RXENA/B
BUSA/B
BUSA/B
RXA/B
RXA/B
Figure 2. Direct Coupled Test Circuits
Isolation
Transformer
Isolation
Transformer
Point "A "
D
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Output Voltage
Direct coupled
35 ohm load
6.0
9.0
Vp-p
(Measured at Point "A " in Figure 2)
70
18.0
27.0
Vp-p
Output Noise
V
Differential, inhibited
10.0
mVp-p
Output Dynamic Offset Voltage
V
-90
90
mV
-250
250
mV
Output resistance
R
Differential, not transmitting
10
Kohm
Output Capacitance
C
1 MHz sine wave
15
pF
TRANSMITTER
(Measured at Point "A " in Figure 2 unless otherwise specified)
D
D
V
Transformer coupled
V
ohm load
(Measured at Point "A " in Figure 3)
Direct coupled
35 ohm load
(Measured at Point "A " in Figure 2)
Transformer coupled
V
70 ohm load
(Measured at Point "A " in Figure 3)
OUT
OUT
DYN
T
D
T
ON
DYN
OUT
OUT
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