8237A Direct Memory Access (DMA) controller, fabricated
using Harris' advanced 2 micron CMOS process. Pin
compatible with NMOS designs, the 82C37A offers
increased functionality, improved performance, and
dramatically reduced power consumption. The fully static
design permits gated clock operation for even further
reduction of power.
allowing external devices to transfer data directly to or from
system memory. Memory-to-memory transfer capability is
also provided, along with a memory block initialization fea-
ture. DMA requests may be generated by either hardware or
software, and each channel is independently programmable
with a variety of features for flexible operation.
address latch, such as the 82C82, to demultiplex the most
significant 8-bits of address. The 82C37A can be used with
industry standard microprocessors such as 80C286, 80286,
80C86, 80C88, 8086, 8088, 8085, Z80, NSC800, 80186 and
others. Multimode programmability allows the user to select
from three basic types of DMA services, and reconfiguration
under program control is possible even with the clock to the
controller stopped. Each channel has a full 64K address and
word count range, and may be programmed to autoinitialize
these registers following DMA termination (end of process).
operations. This input may be driven from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for
the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for
registers, the First/Last Flip-Flop, and the mode register counter. The Mask register is set to ignore
requests. Following a Reset, the controller is in an idle cycle.
accommodate slow memories or I/O devices. READY must not make transitions during its specified
set-up and hold times. See Figure 12 for timing. READY is ignored in verify transfer mode.
relinquished control of the system busses. HLDA is a synchronous input and must not transition
during its specified set-up time. There is an implied hold time (HLDA inactive) of TCH from the rising
edge of CLK, during which time HLDA must not transition.
inputs used by peripheral circuits to obtain DMA service. In Fixed Priority, DREQ0 has the highest
priority and DREQ3 has the lowest priority. A request is generated by activating the DREQ line of a
channel. DACK will acknowledge the recognition of a DREQ signal. Polarity of DREQ is
programmable. RESET initializes these lines to active high. DREQ must be maintained until the
corresponding DACK goes active. DREQ will not be recognized while the clock is stopped. Unused
DREQ inputs should be pulled High or Low (inactive) and the corresponding mask bit set.
bus. The outputs are enabled in the Program condition during the I/O Read to output the contents
of a register to the CPU. The outputs are disabled and the inputs are read during an I/O Write cycle
when the CPU is programming the 82C37A control registers. During DMA cycles, the most signifi-
cant 8-bits of the address are output onto the data bus to be strobed into an external latch by ADSTB.
In memory-to-memory operations, data from the memory enters the 82C37A on the data bus during
the read-from-memory transfer, then during the write-to-memory transfer, the data bus outputs write
the data into the new memory location.
trol signal used by the CPU to read the control registers. In the Active cycle, it is an output control
signal used by the 82C37A to access data from the peripheral during a DMA Write transfer.
trol signal used by the CPU to load information into the 82C37A. In the Active cycle, it is an output
control signal used by the 82C37A to load data to the peripheral during a DMA Read transfer.
concerning the completion of DMA services is available at the bidirectional EOP pin.
low. A pulse is generated by the 82C37A when terminal count (TC) for any channel is reached,
except for channel 0 in memory-to-memory mode. During memory-to-memory transfers, EOP will
be output when the TC for channel 1 occurs.
the service, and if autoinitialize is enabled, the base registers will be written to the current registers
of that channel. The mask bit and TC bit in the status word will be set for the currently active channel
by EOP unless the channel is programmed for autoinitialize. In that case, the mask bit remains clear.
cycle, they are inputs and are used by the 82C37A to address the control register to be loaded or
read. In the Active cycle, they are outputs and provide the lower 4-bits of the output address.
address. These lines are enabled only during the DMA service.
When a DREQ occurs and the corresponding mask bit is clear, or a software DMA request is made,
the 82C37A issues HRQ. The HLDA signal then informs the controller when access to the system
busses is permitted. For stand-alone operation where the 82C37A always controls the busses, HRQ
may be tied to HLDA. This will result in one S0 state before the transfer.
has been granted a DMA cycle. The sense of these lines is programmable. RESET initializes them
to active low.
onto the system address bus. AEN can also be used to disable other system bus drivers during DMA
transfers. AEN is active high.
byte. It will drive directly the strobe input of external transparent octal latches, such as the 82C82.
During block operations, ADSTB will only be issued when the upper address byte must be updated,
thus speeding operation through elimination of S1 states. ADSTB timing is referenced to the falling
edge of the 82C37A clock.
from the selected memory location during a DMA Read or a memory-to-memory transfer.
to the selected memory location during a DMA Write or a memory-to-memory transfer.
improve the data transfer rate in systems which must
transfer data from an I/O device to memory, or move a block
of memory to an I/O device. It will also perform memory-to-
memory block moves, or fill a block of memory with data
from a single location. Operating modes are provided to
handle single byte transfers as well as discontinuous data
streams, which allows the 82C37A to control data movement
with software transparency.
signal generator, which permits data to be transferred
directly from an I/O device to memory or vice versa without
ever being stored in a temporary register. This can greatly
increase the data transfer rate for sequential operations,
compared with processor move or repeated string
instructions. Memory-to-memory operations require
temporary internal storage of the data byte between
generation of the source and destination addresses, so
memory-to-memory transfers take place at less than half the
rate of I/O operations, but still much faster than with central
processor techniques. The maximum data transfer rates
obtainable with the 82C37A are shown in Figure 1.
timing and control block, priority block, and internal registers
are the main components. Figure 2 lists the name and size
of the internal registers. The timing and control block derives
internal timing from clock input, and generates external
control signals. The Priority Encoder block resolves priority
contention between DMA channels requesting service
data bus pins are basically connected in parallel with the
system busses. An external latch is required for the upper
address byte. While inactive, the controller's outputs are in a
high impedance state. When activated by a DMA request
and bus control is relinquished by the host, the 82C37A
drives the busses and generates the control signals to
perform the data transfer. The operation performed by
activating one of the four DMA request inputs has previously
been programmed into the controller via the Command,
Mode, Address, and Word Count registers.
to an I/O device, the starting address of the data is loaded
into the 82C37A Current and Base Address registers for a
particular channel, and the length of the block is loaded into
the channel's Word Count register. The corresponding Mode
register is programmed for a memory-to-I/O operation (read
transfer), and various options are selected by the Command
register and the other Mode register bits. The channel's
mask bit is cleared to enable recognition of a DMA request
(DREQ). The DREQ can either be a hardware signal or a
controller outputs the data address, simultaneous MEMR
and IOW pulses, and selects an I/O device via the DMA
acknowledge (DACK) outputs. The data byte flows directly
from the RAM to the I/O device. After each byte is
transferred, the address is automatically incremented (or
decremented) and the word count is decremented. The
operation is then repeated for the next byte. The controller
stops transferring data when the Word Count register
underflows, or an external EOP is applied.
generated by each clock cycle must be considered. The
DMA controller operates in two major cycles, active and idle.
After being programmed, the controller is normally idle until
a DMA request occurs on an unmasked channel, or a
software request is given. The 82C37A will then request
control of the system busses and enter the active cycle. The
active cycle is composed of several internal states,
depending on what options have been selected and what
type of operation has been requested.
composed of one full clock period. State I (SI) is the idle
state. It is entered when the 82C37A has no valid DMA
requests pending, at the end of a transfer sequence, or
when a Reset or Master Clear has occurred. While in SI, the
DMA controller is inactive but may be in the Program
Condition (being programmed by the processor).
has requested a hold but the processor has not yet returned
an acknowledge. The 82C37A may still be programmed until
it has received HLDA from the CPU. An acknowledge from
the CPU will signal the DMA transfer may begin. S1, S2, S3,
and S4 are the working state of the DMA service. If more
time is needed to complete a transfer than is available with
normal timing, wait states (SW) can be inserted between S3
and S4 in normal transfers by the use of the Ready line on
the 82C37A. For compressed transfers, wait states can be
inserted between S2 and S4. See timing Figures 14 and 15.
to memory (or vice versa) with IOR and MEMW (or MEMR
and IOW) being active at the same time. The data is not read
into or driven out of the 82C37A in I/O-to-memory or
memory-to-I/O DMA transfers.
to memory to complete each transfer. The states, which
resemble the normal working states, use two-digit numbers
for identification. Eight states are required for a single transfer.
The first four states (S11, S12, S13, S14) are used for the
read-from-memory half and the last four state (S21, S22, S23,
S24) for the write-to-memory half of the transfer.
enter the idle cycle and perform "SI" states. In this cycle, the
82C37A will sample the DREQ lines on the falling edge of
every clock cycle to determine if any channel is requesting a
stopped, DMA requests will be ignored. The device will
respond to CS (chip select), in case of an attempt by the
microprocessor to write or read the internal registers of the
82C37A. When CS is low and HLDA is low, the 82C37A
enters the Program Condition. The CPU can now establish,
change or inspect the internal definition of the part by read-
ing from or writing to the internal registers.
vided that HLDA is low and at least one rising clock edge has
occurred after HLDA was driven low, so the controller is in an SI
state. Address lines A0-A3 are inputs to the device and select
which registers will be read or written. The IOR and IOW lines
are used to select and time the read or write operations. Due to
the number and size of the internal registers, an internal flip-flop
called the First/Last Flip-Flop is used to generate an additional
bit of address. The bit is used to determine the upper or lower
byte of the 16-bit Address and Work Count registers. The flip-
flop is reset by Master Clear or RESET. Separate software
commands can also set or reset this flip-flop.
82C37A in the Program Condition. These commands are
decoded as sets of addresses with CS, IOR, and IOW. The
commands do not make use of the data bus. Instructions
include Set and Clear First/Last Flip-Flop, Master Clear,
Clear Mode Register Counter, and Clear Mask Register.
request or an unmasked channel requests a DMA service,
the device will issue HRQ to the microprocessor and enter
the Active cycle. It is in this cycle that the DMA service will
take place, in one of four modes:
is programmed to make one transfer only. The word count
will be decremented and the address decremented or
incremented following each transfer. When the word count
"rolls over" from zero to FFFFH, a terminal count bit in the
status register is set, an EOP pulse is generated, and the
channel will autoinitialize if this option has been selected. If
not programmed to autoinitialize, the mask bit will be set,
along with the TC bit and EOP pulse.
DREQ is held active throughout the single transfer, HRQ will
go inactive and release the bus to the system. It will again go
active and, upon receipt of a new HLDA, another single
transfer will be performed, unless a higher priority channel
takes over. In 8080A, 8085A, 80C88, or 80C86 systems, this
will ensure one full machine cycle execution between DMA
transfers. Details of timing between the 82C37A and other
bus control protocols will depend upon the characteristics of
the microprocessor involved.
is activated by DREQ or software request and continues
making transfers during the service until a TC, caused by
word count going to FFFFH, or an external End of Process
(EOP) is encountered. DREQ need only be held active until
DACK becomes active. Again, an Autoinitialization will occur
at the end of the service if the channel has been
programmed for that option.
device continues making transfers until a TC or external EOP is
encountered, or until DREQ goes inactive. Thus, transfer may
continue until the I/O device has exhausted its data capacity.
After the I/O device has had a chance to catch up, the DMA
service is reestablished by means of a DREQ. During the time
between services when the microprocessor is allowed to oper-
ate, the intermediate values of address and word count are
stored in the 82C37A Current Address and Current Word
Count registers. Higher priority channels may intervene in the
demand process, once DREQ has gone inactive. Only an EOP
can cause an Autoinitialization at the end of service. EOP is
generated either by TC or by an external signal.
one 82C37A for simple system expansion. The HRQ and
HLDA signals from the additional 82C37A are connected to
the DREQ and DACK signals respectively of a channel for
additional device to propagate through the priority network
circuitry of the preceding device. The priority chain is
preserved and the new device must wait for its turn to
acknowledge requests. Since the cascade channel of the
initial 82C37A is used only for prioritizing the additional
device, it does not output an address or control signals of its
own. These could conflict with the outputs of the active chan-
nel in the added device. The initial 82C37A will respond to
DREQ and generate DACK but all other outputs except HRQ
will be disabled. An external EOP will be ignored by the initial
device, but will have the usual effect on the added device.
initial device using two of the initial device's channels. This
forms a two-level DMA system. More 82C37As could be
added at the second level by using the remaining channels
of the first level. Additional devices can also be added by
cascading into the channels of the second level devices,
forming a third level.
level device (closest to the microprocessor). After RESET,
the DACK outputs are programmed to be active low and are
held in the high state. If they are used to drive HLDA directly,
the second level device(s) cannot be programmed until
DACK polarity is selected as active high on the initial device.
Also, the initial device's mask bits function normally on
cascaded channels, so they may be used to inhibit second-
ferent types of transfers. These are Read, Write and Verify.
Write transfers move data from an I/O device to the memory
by activating MEMW and IOR. Read transfers move data from
memory to an I/O device by activating MEMR and IOW.
as in Read or Write transfers generating addresses and
responding to EOP, etc., however the memory and I/O
control lines all remain inactive. Verify mode is not permitted
for memory-to-memory operation. READY is ignored during
channel may be set up as an Autoinitialize channel. During
Autoinitialization, the original values of the Current Address
and Current Word Count registers are automatically restored
from the Base Address and Base Word Count registers of
the channel following EOP. The base registers are loaded
simultaneously with the current registers by the micropro-
cessor and remain unchanged throughout the DMA service.
The mask bit is not set when the channel is in Autoinitialize
mode. Following Autoinitialization, the channel is ready to
perform another DMA service, without CPU intervention, as
soon as a valid DREQ is detected, or software request
one memory address space to another with minimum of
program effort and time, the 82C37A includes a memory-to-
memory transfer feature. Setting bit 0 in the Command
register selects channels 0 and 1 to operate as memory-to-
memory transfer channels.
DREQ for channel 0. The 82C37A requests a DMA service
in the normal manner. After HLDA is true, the device, using
four-state transfers in Block Transfer mode, reads data from
the memory. The channel 0 Current Address register is the
source for the address used and is decremented or
incremented in the normal manner. The data byte read from
the memory is stored in the 82C37A internal Temporary reg-
ister. Another four-state transfer moves the data to memory
using the address in channel one's Current Address register
and incrementing or decrementing it in the normal manner.
The channel 1 Current Word Count is decremented.
TC is generated causing an EOP output, terminating the
service, and setting the channel 1 TC bit in the Status
register. The channel 1 mask bit will also be set, unless the
channel 1 mode register is programmed for autoinitialization.
Channel 0 word count decrementing to FFFFH will not set
the channel 0 TC bit in the status register nor generate an
EOP, nor set the channel 0 mask bit in this mode. It will
cause an autoinitialization of channel 0, if that option has
desired, the channel 0 and channel 1 word counts must be
set to equal values before the transfer begins. Otherwise, if
channel 0 underflows before channel 1, it will autoinitialize
and set the data source address back to the beginning of the
block. If the channel 1 word count underflows before channel
0, the memory-to-memory DMA service will terminate, and
channel 1 will autoinitialize but channel 0 will not.
programmed to retain the same address for all transfers.
This allows a single byte to be written to a block of memory.
This channel 0 address hold feature is selected by setting bit
1 in the Command register.
memory-to-memory transfers, but will only relinquish the
system busses after the transfer is complete (i.e. after an
cause the channel 0 Address and Word Count registers to
autoinitialize, even if the Mode register is programmed for
autoinitialization. An external EOP will autoinitialize the
channel 1 registers, if so programmed. Data comparators in
block search schemes may use the EOP input to terminate
the service when a match is found. The timing of memory-to-
memory transfers is found in Figure 13. Memory-to-memory
operations can be detected as an active AEN with no DACK
available as software selectable options. The first is Fixed
Priority which fixes the channels in priority order based upon
the descending value of their numbers. The channel with the
lowest priority is 3 followed by 2, 1 and the highest priority
channel, 0. After the recognition of any one channel for ser-
vice, the other channels are prevented from interfering with
the service until it is completed.
get service becomes the lowest priority channel with the
others rotating accordingly. The next lower channel from the
channel serviced has highest priority on the following
request. Priority rotates every time control of the system
busses is returned to the processor.
device requesting service is guaranteed to be recognized
after no more than three higher priority services have
occurred. This prevents any one channel from monopolizing
evaluated every time a HLDA is returned to the 82C37A.
throughput where system characteristics permit, the 82C37A
can compress the transfer time to two clock cycles. From
Figure 12 it can be seen that state S3 is used to extend the
access time of the read pulse. By removing state S3, the
read pulse width is made equal to the write pulse width and
a transfer consists only of state S2 to change the address
and state S4 to perform the read/write. S1 states will still
occur when A8-A15 need updating (see Address
Generation). Timing for compressed transfers is found in
Figure 15. EOP will output in S2 if compressed timing is
selected. Compressed timing is not allowed for memory-to-
82C37A multiplexes the eight higher order address bits on
the data lines. State S1 is used to output the higher order
placed on the address bus. The falling edge of Address
Strobe (ADSTB) is used to load these bits from the data
lines to the latch. Address Enable (AEN) is used to enable
the bits onto the address bus through a three-state enable.
The lower order address bits are output by the 82C37A
directly. Lines A0-A7 should be connected to the address
bus. Figure 12 shows the time relationships between CLK,
AEN, ADSTB, DB0-DB7 and A0-A7.
include multiple transfers, the addresses generated will be
sequential. For many transfers the data held in the external
address latch will remain the same. This data need only
change when a carry or borrow from A7 to A8 takes place in
the normal sequence of addresses. To save time and speed
transfers, the 82C37A executes S1 states only when
updating of A8-A15 in the latch is necessary. This means for
long services, S1 states and Address Strobes may occur
only once every 256 transfers, a savings of 255 clock cycles
for each 256 transfers.
processor anytime that HLDA is inactive, and at least one
rising clock edge has occurred after HLDA went low. It is the
responsibility of the host to assure that programming and
HLDA are mutually exclusive.
an unmasked channel while the 82C37A is being pro-
grammed. For instance, the CPU may be starting to repro-
gram the two byte Address register of channel 1 when
channel 1 receives a DMA request. If the 82C37A is enabled
(bit 2 in the Command register is 0), and channel 1 is
unmasked, a DMA service will occur after only one byte of
the Address register has been reprogrammed. This condi-
tion can be avoided by disabling the controller (setting bit 2
in the Command register) or masking the channel before
programming any of its registers. Once the programming is
complete, the controller can be enabled/unmasked.
loaded with some known value, even if some channels are
unused. This will aid in debugging.
Current Address register. This register holds the value of the
address used during DMA transfers. The address is auto-
matically incremented or decremented by one after each
transfer and the values of the address are stored in the Cur-
rent Address register during the transfer. This register is writ-
ten or read by the microprocessor in successive 8-bit bytes.
See Figure 6 for programming information. It may also be
reinitialized by an Autoinitialize back to its original value.
Autoinitialize takes place only after an EOP. In memory-to-
memory mode, the channel 0 Current Address register can
be prevented from incrementing or decrementing by setting
the address hold bit in the Command register.
Current Word Count register. This register determines the
number of transfers to be performed. The actual number of
transfers will be one more than the number programmed in
the Current Word Count register (i.e., programming a count
of 100 will result in 101 transfers). The word count is
decremented after each transfer. When the value in the
register goes from zero to FFFFH, a TC will be generated.
This register is loaded or read in successive 8-bit bytes by
the microprocessor in the Program Condition. See Figure 6
for programming information. Following the end of a DMA
service it may also be reinitialized by an Autoinitialization
back to its original value. Autoinitialization can occur only
when an EOP occurs. If it is not Autoinitialized, this register
will have a count of FFFFH after TC.
channel has a pair of Base Address and Base Word Count
registers. These 16-bit registers store the original value of
their associated current registers. During Autoinitialize these
values are used to restore the current registers to their
original values. The base registers are written simulta-
neously with their corresponding current register in 8-bit
bytes in the Program Condition by the microprocessor. See
Figure 6 for programming information. These registers can-
not be read by the microprocessor.
tion of the 82C37A. It is programmed by the microprocessor
and is cleared by RESET or a Master Clear instruction. The
following diagram lists the function of the Command register
bits. See Figure 4 for Read and Write addresses.
associated with it. When the register is being written to by
the microprocessor in the Program condition, bits 0 and 1
determine which channel Mode register is to be written.
When the processor reads a Mode register, bits 0 and 1 will
both be ones. See the following diagram and Figure 4 for
Mode register functions and addresses.
for DMA service which are initiated by software as well as by
a DREQ. Each channel has a request bit associated with it in
the 4-bit Request register. These are non-maskable and
subject to prioritization by the Priority Encoder network.
Each register bit is set or reset separately under software
control. The entire register is cleared by a Reset or Master
Clear instruction. To set or reset a bit, the software loads the
proper form of the data word. See Figure 4 for register
address coding, and the following diagram for Request
register format. A software request for DMA operation can
be made in block or single modes. For memory-to-memory
transfers, the software request for channel 0 should be set.
When reading the Request register, bits 4-7 will always read
as ones, and bits 0-3 will display the request bits of channels
Channel 0 address hold enable
If bit 0 = 0
If bit 0 = 1
Extended write selection
If bit 3 = 1
DREQ sense active low
DACK sense active high
Channel 1 select
Channel 2 select
Channel 3 select
If bits 6 and 7 = 11
Address decrement select
Single mode select
Block mode select
Cascade mode select
Select Channel 1
Select Channel 2
Select Channel 3
Set request bit
bit which can be set to disable an incoming DREQ. Each
mask bit is set when its associated channel produces an EOP
if the channel is not programmed to Autoinitialize. Each bit of
the 4-bit Mask register may also be set or cleared separately
or simultaneously under software control. The entire register
is also set by a Reset or Master clear. This disables all hard-
ware DMA requests until a Clear Mask Register instruction
allows them to occur. The instruction to separately set or clear
the mask bits is similar in form to that used with the Request
register. Refer to the following diagram and Figure 4 for
details. When reading the Mask register, bits 4-7 will always
read as logical ones, and bits 0-3 will display the mask bits of
channels 0-3, respectively. The 4 bits of the Mask register
may be cleared simultaneously by using the Clear Mask Reg-
ister command (see software commands section).
out of the 82C37A by the microprocessor. It contains
information about the status of the devices at this point. This
information includes which channels have reached a terminal
count and which channels have pending DMA requests. Bits
0-3 are set every time a TC is reached by that channel or an
external EOP is applied. These bits are cleared upon RESET,
Master Clear, and on each Status Read. Bits 4-7 are set
whenever their corresponding channel is requesting service,
regardless of the mask bit state. If the mask bits are set, soft-
ware can poll the Status register to determine which channels
have DREQs, and selectively clear a mask bit, thus allowing
user defined service priority. Status bits 4-7 are updated while
the clock is high, and latched on the falling edge. Status Bits
4-7 are cleared upon RESET or Master Clear.
hold data during memory-to-memory transfers. Following the
completion of the transfers, the last byte moved can be read
by the microprocessor. The Temporary register always
contains the last byte transferred in the previous memory-to-
memory operation, unless cleared by a Reset or Master
Select Channel 1 mask bit
Select Channel 2 mask bit
Select Channel 3 mask bit
Set mask bit
Set Channel 0 mask bit
Set Channel 1 mask bit
Set Channel 2 mask bit
Set Channel 3 mask bit
executed by reading or writing to the 82C37A. These com-
mands do not depend on the specific data pattern on the
data bus, but are activated by the I/O operation itself. On
read type commands, the data value is not guaranteed.
These commands are:
prior to writing or reading new address or word count infor-
mation to the 82C37A. This command initializes the flip-flop
to a known state (low byte first) so that subsequent accesses
to register contents by the microprocessor will address
upper and lower bytes in the correct sequence.
to select the high byte first on read and write operations to
address and word count registers.
as the hardware Reset. The Command, Status, Request,
and Temporary registers, and Internal First/Last Flip-Flop
and mode register counter are cleared and the Mask register
is set. The 82C37A will enter the idle cycle.
of all four channels, enabling them to accept DMA requests.
location is available for reading the Mode registers, an inter-
nal two-bit counter has been included to select Mode regis-
ters during read operation. To read the Mode registers, first
execute the Clear Mode Register Counter command, then
do consecutive reads until the desired channel is read. Read
order is channel 0 first, channel 3 last. The lower two bits on
all Mode registers will read as ones.
driven by external signals to terminate DMA operation.
Because EOP is an open drain pin an external pull-up resis-
tor to V
125ns. It is important to note that the 82C37A will not accept
external EOP signals when it is in a SI (Idle) state. The
controller must be active to latch EXT EOP. Once latched,
the EXT EOP will be acted upon during the next S2 state,
unless the 82C37A enters an idle state first. In the latter
case, the latched EOP is cleared. External EOP pulses
occurring between active DMA transfers in demand mode
will not be recognized, since the 82C37A is in an SI state.
82C37A DMA controller and the 80C88 Microprocessor. In
this application, the 82C37A DMA controller is used to
improve system performance by allowing an I/O device to
transfer data directly to or from system memory.
and is inverted to meet the clock high and low times required
by the 82C37A DMA controller. The four OR gates are used
to support the 80C88 Microprocessor in minimum mode by
producing the control signals used by the processor to
access memory or I/O. A decoder is used to generate chip
select for the DMA controller and memory. The most signifi-
cant bits of the address are output on the address/data bus.
Therefore, the 82C82 octal latch is used to demultiplex the
(AEN) are "ORed" together to insure that the DMA controller
does not have bus contention with the microprocessor.
receiving the DMA request, the DMA controller will issue a
Hold request (HRQ) to the processor. The system busses
are not released to the DMA controller until a Hold Acknowl-
edge signal is returned to the DMA controller from the
80C88 processor. After the Hold Acknowledge has been
received, addresses and control signals are generated by
the DMA controller to accomplish the DMA transfers. Data is
transferred directly from the I/O device to memory (or vice
versa) with IOR and MEMW (or MEMR and IOW) being
active. Note that data is not read into or driven out of the
DMA controller in I/O-to-memory or memory-to-I/O data
82C37A DMA controller and the 80C286 Microprocessor.
clock generator PCLK signal which is inverted to provide
proper READY setup and hold times to the DMA controller in
an 80C286 system. The Read and Write signals from the
DMA controller may be wired directly to the Read/Write con-
trol signals from the 82C288 Bus Controller. The octal latch
80C286 address bus so that memory chip selects may still
be generated during DMA transfers. The transceiver on A0-
A7 is controlled by AEN and is not necessary, but may be
used to drive a heavily loaded system address bus during
transfers. The data bus transceivers simply isolate the DMA
controller from the local microprocessor bus and allow pro-
gramming on the upper or lower half of the data bus.
82C288 SIGNALS AND
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to V
Operating Temperature Range
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IOL = +3.2mA for EOP pin 36 only.
referenced to device GND
must switch between VIHC +0.4V and VILC -0.4V
4. GND = 0V
5. R1 = 1.2k
12. DO0 - DO6 are outputs from the 82C82 Octal Latching Bus Driver
Thickness: Metal 1: 8k